03.03.2020 16:34, Denis Plotnikov wrote:
zstd significantly reduces cluster compression time.
It provides better compression performance maintaining
the same level of the compression ratio in comparison with
zlib, which, at the moment, is the only compression
method available.
The performance te
03.03.2020 16:34, Denis Plotnikov wrote:
The patch enables processing the image compression type defined
for the image and chooses an appropriate method for image clusters
(de)compression.
Signed-off-by: Denis Plotnikov
---
block/qcow2-threads.c | 71 --
> -Original Message-
> From: Daniel Cho
> Sent: Monday, February 24, 2020 3:15 PM
> To: Zhang, Chen
> Cc: Dr. David Alan Gilbert ; Zhanghailiang
> ; qemu-devel@nongnu.org; Jason
> Wang
> Subject: Re: The issues about architecture of the COLO checkpoint
>
> Hi Zhang,
>
> Thanks for yo
Markus Armbruster writes:
> Signed-off-by: Markus Armbruster
> ---
[...]
> diff --git a/scripts/qapi/schema.py b/scripts/qapi/schema.py
> index c8bcfe2c49..e132442c04 100644
> --- a/scripts/qapi/schema.py
> +++ b/scripts/qapi/schema.py
[...]
> @@ -614,7 +614,7 @@ class
> QAPISchemaObjectTypeVar
John Snow writes:
> Repeatable results. run `pylint iotests.py` and you should get a pass.
Start your sentences with a capital letter, please.
>
> Signed-off-by: John Snow
> ---
> tests/qemu-iotests/pylintrc | 20
> 1 file changed, 20 insertions(+)
> create mode 100644 t
On Tue, Mar 3, 2020 at 5:41 PM Auger Eric wrote:
>
> Hi Zhangfei,
> On 3/3/20 4:23 AM, Zhangfei Gao wrote:
> > Hi Eric
> >
> > On Thu, Feb 27, 2020 at 9:50 PM Auger Eric wrote:
> >>
> >> Hi Daniel,
> >>
> >> On 2/27/20 12:17 PM, Daniel P. Berrangé wrote:
> >>> On Fri, Feb 14, 2020 at 02:27:35PM +
A portion of a recent patch got lost due to a merge snafu. That patch is
now commit 88f632fbb1 ("dp8393x: Mask EOL bit from descriptor addresses").
This patch restores the portion that got lost.
Signed-off-by: Finn Thain
---
hw/net/dp8393x.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions
> cmd646_update_irq() only seems to raise PCI interrupt, should it also
> have
> an option to use INT 14 and 15 in legacy mode similar to what my
> patch
> does for via-ide?
Looking through /qemu/hw/ide/cmd646.c it doesn't look like QEMU has
support for legacy mode. At the very least, it looks l
Since the new capability KVM_DIRTY_LOG_INITIALLY_SET of
KVM_CAP_MANUAL_DIRTY_LOG_PROTECT2 has been introduced in the
kernel, tweak the userspace side to detect and enable this
capability.
Signed-off-by: Jay Zhou
---
accel/kvm/kvm-all.c | 21 ++---
linux-headers/linux/kvm.h
On Tue, Mar 03, 2020 at 11:32:49AM +0100, Greg Kurz wrote:
> On Tue, 3 Mar 2020 14:43:51 +1100
> David Gibson wrote:
>
> > The Real Mode Area (RMA) needs to fit within the NUMA node owning memory
> > at address 0. That's usually node 0, but can be a later one if there are
> > some nodes which h
On 2020/3/4 上午6:44, Finn Thain wrote:
Hi Jason,
The patch in this pull request (since merged) differs from the patch that
I sent. In particular, the change below is missing from commit 88f632fbb1
("dp8393x: Mask EOL bit from descriptor addresses") in mainline.
--- a/hw/net/dp8393x.c
+++ b/hw/
From: Bin Meng
At present the board serial number is hard-coded to 1, and passed
to OTP model during initialization. Firmware (FSBL, U-Boot) uses
the serial number to generate a unique MAC address for the on-chip
ethernet controller. When multiple QEMU 'sifive_u' instances are
created and connect
At present the board serial number is hard-coded to 1, and passed
to OTP model during initialization. Firmware (FSBL, U-Boot) uses
the serial number to generate a unique MAC address for the on-chip
ethernet controller. When multiple QEMU 'sifive_u' instances are
created and connected to the same su
Split the file into clear machine and SoC sections.
Signed-off-by: Alistair Francis
---
hw/riscv/sifive_u.c | 107 ++--
1 file changed, 54 insertions(+), 53 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 156a003642..9a0145b5b4 1
At present the board serial number is hard-coded to 1, and passed
to OTP model during initialization. Firmware (FSBL, U-Boot) uses
the serial number to generate a unique MAC address for the on-chip
ethernet controller. When multiple QEMU 'sifive_u' instances are
created and connected to the same su
The RISC-V spec specifies that when a write happens and the D bit is
clear the implementation will set the bit in the PTE. It does not
describe that the PTE being dirty means that we should provide write
access. This patch removes the write access granted to pages when the
dirty bit is set.
Follow
Description copied from Linux kernel commit from Gustavo A. R. Silva
(see [3]):
--v-- description start --v--
The current codebase makes use of the zero-length array language
extension to the C90 standard, but the preferred mechanism to
declare variable-length types such as these ones is a
I'm happy to do this. It will take a while for me to collect the
results though. I'll chime in once I have the results.
> That should give the ultimate answer to our guessing.
Agreed.
Thanks,
Jasper Lowell.
On Thu, 2020-02-27 at 12:38 +0100, BALATON Zoltan wrote:
> On Thu, 27 Feb 2020, jasper.lo
I haven't.
I did a pull this morning on master and everything seems to be working
again. The problem was likely the same.
Thanks,
Jasper Lowell.
On Thu, 2020-02-27 at 12:35 +0100, BALATON Zoltan wrote:
> On Thu, 27 Feb 2020, jasper.low...@bt.com wrote:
> > > I'll submit a RFC V2 patch with a pro
Signed-off-by: Alistair Francis
---
linux-user/riscv/syscall32_nr.h | 295 +++
linux-user/riscv/syscall64_nr.h | 301
linux-user/riscv/syscall_nr.h | 294 +--
3 files changed, 598 insertions(+), 292 deletio
New y2038 safe 32-bit architectures (like RISC-V) don't support old
syscalls with a 32-bit time_t. The kernel defines new *_time64 versions
of these syscalls. Add some more #ifdefs to syscall.c in linux-user to
allow us to compile without these old syscalls.
Signed-off-by: Alistair Francis
---
l
Add support for the clock_gettime64/clock_settime64 syscalls. Currently
we only support these syscalls when running on 64-bit hosts.
Signed-off-by: Alistair Francis
---
linux-user/syscall.c | 43 +++
1 file changed, 43 insertions(+)
diff --git a/linux-use
Description copied from Linux kernel commit from Gustavo A. R. Silva
(see [3]):
--v-- description start --v--
The current codebase makes use of the zero-length array language
extension to the C90 standard, but the preferred mechanism to
declare variable-length types such as these ones is a
This series updates the RISC-V syscall_nr.sh based on the 5.5 kernel.
There are two parts to this. One is just adding the new syscalls, the
other part is updating the RV32 syscalls to match the fact that RV32 is
a 64-bit time_t architectures (y2038) safe.
We need to make some changes to syscall.c
This is a tree-wide cleanup inspired by a Linux kernel commit
(from Gustavo A. R. Silva).
--v-- description start --v--
The current codebase makes use of the zero-length array language
extension to the C90 standard, but the preferred mechanism to
declare variable-length types such as these
On Tue, 3 Mar 2020, Mark Cave-Ayland wrote:
On 02/03/2020 21:40, BALATON Zoltan wrote:
I had a quick look at the schematics linked from the page above, and they
confirm
that the VIA IDE interface is connected directly to IRQs 14 and 15 and not to
the PCI
interrupt pins.
Where did you see tha
On 3/3/20 7:36 PM, Peter Maydell wrote:
On Tue, 3 Mar 2020 at 18:33, Philippe Mathieu-Daudé wrote:
Nitpick: you don't need to include the bracket symbol in the diff:
@@
-resetfn(CPUState *cpu)
+resetfn(DeviceState *dev)
{
(simply indent it with a space).
I think this was pr
On 3/3/20 8:57 PM, John Snow wrote:
On 2/27/20 9:14 AM, Philippe Mathieu-Daudé wrote:
On 2/27/20 1:06 AM, John Snow wrote:
The right way to solve this is to come up with a virtual environment
infrastructure that sets all the paths correctly, and/or to create
installable python modules that can
Hi Andrew,
Please Cc all the maintainers:
./scripts/get_maintainer.pl -f hw/net/e1000e.c
Dmitry Fleytman (maintainer:e1000e)
Jason Wang (odd fixer:Network devices)
qemu-devel@nongnu.org (open list:All patches CC here)
On 3/3/20 7:29 PM, and...@daynix.com wrote:
From: Andrew Melnychen
On Tue, Mar 3, 2020 at 1:40 AM Laurent Vivier wrote:
>
> Le 02/03/2020 à 20:31, Lirong Yuan a écrit :
> > This change adds the support for AT_EXECFN auxval.
> >
> > Signed-off-by: Lirong Yuan
> > ---
> > Changelog since v1:
> > - remove implementation for AT_EXECFD auxval.
> >
> > linux-user/elf
Hi Jason,
The patch in this pull request (since merged) differs from the patch that
I sent. In particular, the change below is missing from commit 88f632fbb1
("dp8393x: Mask EOL bit from descriptor addresses") in mainline.
--- a/hw/net/dp8393x.c
+++ b/hw/net/dp8393x.c
@@ -525,8 +525,8 @@ static
On Tue, Mar 03, 2020 at 10:05:11AM +, Peter Maydell wrote:
> The CPUClass has a 'reset' method. This is a legacy from when
> TYPE_CPU used not to inherit from TYPE_DEVICE. We don't need it any
> more, as we can simply use the TYPE_DEVICE reset. The 'cpu_reset()'
> function is kept as the API
On 2/27/20 9:45 AM, Markus Armbruster wrote:
> Signed-off-by: Markus Armbruster
I wrote some pylint cleanup for iotests recently, too. Are you targeting
a subset of pylint errors to clean here?
(Do any files pass 100%?)
Consider checking in a pylintrc file that lets others run the same
subse
On 2/27/20 6:25 AM, Vladimir Sementsov-Ogievskiy wrote:
> 25.02.2020 3:56, John Snow wrote:
>> It's easier to work with than a list of tuples, because we can check the
>> keys for membership.
>>
>> Signed-off-by: John Snow
>> ---
>> python/qemu/machine.py | 10 +-
>> tests/qem
On 2/27/20 5:54 AM, Vladimir Sementsov-Ogievskiy wrote:
>
> Clean code movement, no changes. If test passes, it should be correct :)
>
> The only thing: I'd prefer not exporting global variables and use
> bitmaps.GROUPS instead (even then, it's not very good interface but..)
>
> with or witho
On 2/27/20 5:44 AM, Vladimir Sementsov-Ogievskiy wrote:
> 25.02.2020 3:56, John Snow wrote:
>> This is a new job-creating command.
>>
>> Signed-off-by: John Snow
>> ---
>> qapi/block-core.json | 18 ++
>> qapi/transaction.json | 2 ++
>> blockdev.c | 78
On 2/27/20 1:11 AM, Vladimir Sementsov-Ogievskiy wrote:
>
> Still, if user pass disabled bitmap, it will be invalid immediately after
> job finish.
Yes ... In truth, I really want to augment this job to provide a defined
point-in-time semantic so it can be fully useful in all circumstances.
A
On 2/27/20 6:44 AM, Max Reitz wrote:
>> I'll just clean up the logging series I had to do it at a more
>> fundamental level.
> OK. So you’re looking to basically get VM.qmp() to log automatically if
> necessary? (or maybe qmp_log() to not log unless necessary)
>
> Max
>
Yes. If this series
On 2/27/20 7:59 AM, Max Reitz wrote:
> On 27.02.20 01:06, John Snow wrote:
>> This doesn't fix everything in here, but it does help clean up the
>> pylint report considerably.
>>
>> This should be 100% style changes only; the intent is to make pylint
>> more useful by working on establishing a b
On 2/27/20 8:47 AM, Max Reitz wrote:
> On 27.02.20 01:06, John Snow wrote:
>> Like script_main, but doesn't require a single point of entry.
>> Replace all existing initialization sections with this drop-in replacement.
>>
>> This brings debug support to all existing script-style iotests.
>>
>>
On 02/03/2020 21:40, BALATON Zoltan wrote:
>> I had a quick look at the schematics linked from the page above, and they
>> confirm
>> that the VIA IDE interface is connected directly to IRQs 14 and 15 and not
>> to the PCI
>> interrupt pins.
>
> Where did you see that? What I got from trying to
On Tue, Mar 3, 2020 at 5:12 PM Priyamvad Acharya
wrote:
> > These errors are probably due to the Makefile.objs changes in your commit:
>
> If I am not wrong, we need to add a rule i.e " common-obj-$(CONFIG_TESTPCI)
> += testpci.o " in Makefile.objs to compile custom device in Qemu.
> Shall I shou
Hi Alex,
First thanks for all your reviews, I'll add the tags in the next version of
this series.
On Tue, Mar 3, 2020 at 1:09 PM Alex Bennée wrote:
>
> Niek Linnenbank writes:
>
> > Various Allwinner System on Chip designs contain multiple processors
> > that can be configured and reset using
Since the topology routines have changed, update
the unit tests to use the new APIs.
Signed-off-by: Babu Moger
---
tests/test-x86-cpuid.c | 115
1 file changed, 68 insertions(+), 47 deletions(-)
diff --git a/tests/test-x86-cpuid.c b/tests/test-x
Check and Load the apicid handlers from X86CPUDefinition if available.
Update the calling convention for the apicid handlers.
Signed-off-by: Babu Moger
---
hw/i386/pc.c |6 +++---
hw/i386/x86.c | 11 +++
2 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/hw/i386/pc.c
If the system is numa configured the pkg_offset needs
to be adjusted for EPYC cpu models. Fix it calling the
model specific handler.
Signed-off-by: Babu Moger
---
hw/i386/pc.c |1 +
target/i386/cpu.c |4 ++--
target/i386/cpu.h |1 +
3 files changed, 4 insertions(+), 2 deletions(
Apicid calculation depends on knowing the total number of numa nodes
for EPYC cpu models. Right now, we are calculating the arch_id while
parsing the numa(parse_numa). At this time, it is not known how many
total numa nodes are configured in the system.
Move the arch_id inside x86_cpus_init. At th
Load the model specific handlers if available or else default handlers
will be loaded. Add the model specific handlers if apicid decoding
differs from the standard sequential numbering.
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 34 ++
target/i386/cpu.h |
On 2/27/20 9:21 AM, Max Reitz wrote:
> On 27.02.20 01:06, John Snow wrote:
>> We can turn logging on/off globally instead of per-function.
>>
>> Remove use_log from run_job, and use python logging to turn on
>> diffable output when we run through a script entry point.
>>
>> iotest 245 changes ou
Introduce model specific apicid functions inside X86MachineState.
These functions will be loaded from X86CPUDefinition.
Signed-off-by: Babu Moger
---
hw/i386/x86.c |5 +
include/hw/i386/x86.h |9 +
2 files changed, 14 insertions(+)
diff --git a/hw/i386/x86.c b/hw/i38
Add the new EPYC model specific handlers to fix the apicid decoding.
The APIC ID is decoded based on the sequence sockets->dies->cores->threads.
This works fine for most standard AMD and other vendors' configurations,
but this decoding sequence does not follow that of AMD's APIC ID enumeration
str
These functions add support for building EPYC mode topology given the smp
details like numa nodes, cores, threads and sockets.
The new apic id decoding is mostly similar to current apic id decoding
except that it adds a new field node_id when numa configured. Removes all
the hardcoded values. Subs
Update structures X86CPUTopoIDs and CPUX86State to hold the number of
nodes per package. This is required to build EPYC mode topology.
Signed-off-by: Babu Moger
---
hw/i386/pc.c |1 +
hw/i386/x86.c |1 +
include/hw/i386/topology.h |1 +
target/i386/cpu.c
On 2/27/20 9:14 AM, Philippe Mathieu-Daudé wrote:
> On 2/27/20 1:06 AM, John Snow wrote:
>> The right way to solve this is to come up with a virtual environment
>> infrastructure that sets all the paths correctly, and/or to create
>> installable python modules that can be imported normally.
>>
>
Use the new functions from topology.h and delete the unused code. Given the
sockets, nodes, cores and threads, the new functions generate apic id for EPYC
mode. Removes all the hardcoded values.
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 162 +++---
The function pc_cpu_pre_plug takes care of initialization of CPUX86State.
So, remove the initialization here.
Suggested-by: Igor Mammedov
Signed-off-by: Babu Moger
---
hw/i386/x86.c |4
1 file changed, 4 deletions(-)
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index 03b8962c98..79badcc
For consistancy rename apicid_from_topo_ids to x86_apicid_from_topo_ids.
No functional change.
Signed-off-by: Babu Moger
Reviewed-by: Igor Mammedov
---
hw/i386/pc.c |2 +-
include/hw/i386/topology.h |6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/
This is an effort to re-arrange few data structure for better readability.
1. Add X86CPUTopoInfo which will have all the topology informations
required to build the cpu topology. There is no functional changes.
2. Introduce init_topo_info to initialize X86CPUTopoInfo members from
X86MachineS
Store the smp sockets in CpuTopology. The socket information required to
build the apic id in EPYC mode. Right now socket information is not passed
to down when decoding the apic id. Add the socket information here.
Signed-off-by: Babu Moger
Reviewed-by: Eduardo Habkost
Reviewed-by: Igor Mammed
Rename few data structures related to X86 topology. X86CPUTopoIDs will
have individual arch ids. Next patch introduces X86CPUTopoInfo which will
have all topology information(like cores, threads etc..).
Signed-off-by: Babu Moger
Reviewed-by: Eduardo Habkost
---
hw/i386/pc.c | 4
Now that we have all the parameters in X86CPUTopoInfo, we can just
pass the structure to calculate the offsets and width.
Signed-off-by: Babu Moger
Reviewed-by: Igor Mammedov
---
include/hw/i386/topology.h | 68 ++--
target/i386/cpu.c | 23 ++
* Jagannathan Raman (jag.ra...@oracle.com) wrote:
> In some cases, for example MMIO read, QEMU has to wait for the remote to
> complete a command before proceeding. An eventfd based mechanism is
> added to synchronize QEMU & remote process.
>
> Signed-off-by: John G Johnson
> Signed-off-by: Jagan
This series fixes APIC ID encoding problem reported on AMD EPYC cpu models.
https://bugzilla.redhat.com/show_bug.cgi?id=1728166
Currently, the APIC ID is decoded based on the sequence
sockets->dies->cores->threads. This works for most standard AMD and other
vendors' configurations, but this decodi
On 2/27/20 9:11 AM, Philippe Mathieu-Daudé wrote:
> On 2/27/20 1:06 AM, John Snow wrote:
>> Repeatable results. run `pylint iotests.py` and you should get a pass.
>>
>> Signed-off-by: John Snow
>> ---
>> tests/qemu-iotests/pylintrc | 20
>> 1 file changed, 20 insertions(
* Jagannathan Raman (jag.ra...@oracle.com) wrote:
> Allow RAM MemoryRegion to be created from an offset in a file, instead
> of allocating at offset of 0 by default. This is needed to synchronize
> RAM between QEMU & remote process.
> This will be needed for the following patches.
>
> Signed-off-b
On Tue, Mar 03, 2020 at 10:05:11AM +, Peter Maydell wrote:
> The CPUClass has a 'reset' method. This is a legacy from when
> TYPE_CPU used not to inherit from TYPE_DEVICE. We don't need it any
> more, as we can simply use the TYPE_DEVICE reset. The 'cpu_reset()'
> function is kept as the API
On 3/3/20 7:06 AM, Alex Bennée wrote:
> If we want to use @skipUnless decorations on the class we need a
> newer version of avocado.
>
> Signed-off-by: Alex Bennée
> ---
> tests/requirements.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 3/3/20 7:06 AM, Alex Bennée wrote:
> This is used for some of the vm-build tests so lets detect it and
> behave sanely when it is not installed.
>
> Signed-off-by: Alex Bennée
> ---
> configure | 13 +
> tests/vm/Makefile.include | 14 +++---
> 2 files chan
On 3/3/20 2:05 AM, Peter Maydell wrote:
> The CPUClass has a 'reset' method. This is a legacy from when
> TYPE_CPU used not to inherit from TYPE_DEVICE. We don't need it any
> more, as we can simply use the TYPE_DEVICE reset. The 'cpu_reset()'
> function is kept as the API which most places use
On 3/3/20 9:49 AM, Peter Maydell wrote:
> Fix a couple of comment typos.
>
> Signed-off-by: Peter Maydell
> ---
> Noticed these while writing the other patches...
> ---
> target/arm/helper.c| 2 +-
> target/arm/translate.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
Reviewed-
On 3/3/20 9:49 AM, Peter Maydell wrote:
> A write to the CONTROL register can change our current EL (by
> writing to the nPRIV bit). That means that we can't assume
> that s->current_el is still valid in trans_MSR_v7m() when
> we try to rebuild the hflags.
>
> Add a new helper rebuild_hflags_m32_n
On Tue, 3 Mar 2020 at 18:33, Philippe Mathieu-Daudé wrote:
> Nitpick: you don't need to include the bracket symbol in the diff:
>
>@@
>-resetfn(CPUState *cpu)
>+resetfn(DeviceState *dev)
> {
>
> (simply indent it with a space).
I think this was probably leftover from trying to get
On 3/3/20 9:49 AM, Peter Maydell wrote:
> For M-profile CPUs, the FAULTMASK value affects the CPU's MMU index
> (it changes the NegPri bit). We update the hflags after calls
> to the v7m_msr helper in trans_MSR_v7m() but forgot to do so
> in trans_CPS_v7m().
>
> Signed-off-by: Peter Maydell
> ---
On 3/3/20 9:49 AM, Peter Maydell wrote:
> Some of an M-profile CPU's cached hflags state depends on state that's
> in our NVIC object. We already do an hflags rebuild when the NVIC
> registers are written, but we also need to do this on NVIC reset,
> because there's no guarantee that this will happ
On 3/3/20 3:19 PM, Philippe Mathieu-Daudé wrote:
On 3/3/20 11:05 AM, Peter Maydell wrote:
The CPUClass has a 'reset' method. This is a legacy from when
TYPE_CPU used not to inherit from TYPE_DEVICE. We don't need it any
more, as we can simply use the TYPE_DEVICE reset. The 'cpu_reset()'
funct
From: Andrew Melnychenko
https://bugzilla.redhat.com/show_bug.cgi?id=1737400
Fixed setting max_queue_num if there are no peers in NICConf. qemu_new_nic()
creates NICState with 1 NetClientState(index 0) without peers, set
max_queue_num to 0 - It prevents undefined behavior and possible crashes,
Peter Maydell writes:
> On Fri, 28 Feb 2020 at 15:36, Peter Maydell wrote:
>>
>> Hi; this series does a complete conversion of qemu-doc from
>> Texinfo to rST, including the hxtool-generated parts and
>> creation of the qemu.1 manpage from rST.
>>
>
> Advance notice: I would like to put these
On 02/03/20 20:59, Sunil Muthuswamy wrote:
>> You'd be using it to include a signed tags in a pull requests; that is,
>> the git tag that you ask to pull has a cryptographic signature attached
>> to it.
> Great. Is there a link that I can use to read up on how to get the GPG key
> and how to includ
Fix a couple of comment typos.
Signed-off-by: Peter Maydell
---
Noticed these while writing the other patches...
---
target/arm/helper.c| 2 +-
target/arm/translate.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 2eec81
Some of an M-profile CPU's cached hflags state depends on state that's
in our NVIC object. We already do an hflags rebuild when the NVIC
registers are written, but we also need to do this on NVIC reset,
because there's no guarantee that this will happen before the
CPU reset.
This fixes an assertio
This patchset fixes three hflags-mismatch assertions I ran
into while doing some work on M-profile. The last patch
is just comment typos that I noticed in the process.
thanks
-- PMM
Peter Maydell (4):
hw/intc/armv7m_nvic: Rebuild hflags on reset
target/arm: Update hflags in trans_CPS_v7m()
For M-profile CPUs, the FAULTMASK value affects the CPU's MMU index
(it changes the NegPri bit). We update the hflags after calls
to the v7m_msr helper in trans_MSR_v7m() but forgot to do so
in trans_CPS_v7m().
Signed-off-by: Peter Maydell
---
target/arm/translate.c | 5 -
1 file changed, 4
A write to the CONTROL register can change our current EL (by
writing to the nPRIV bit). That means that we can't assume
that s->current_el is still valid in trans_MSR_v7m() when
we try to rebuild the hflags.
Add a new helper rebuild_hflags_m32_newel() which, like the
existing rebuild_hflags_a32_n
On 03/03/20 18:35, Peter Maydell wrote:
> Advance notice: I would like to put these into a pull
> request at the end of this week. This is your opportunity
> to say "that would be a bad idea", "I need X more time
> to review it", etc :-)
>
On the contrary, it's a great idea. :)
Paolo
On Fri, 28 Feb 2020 at 15:36, Peter Maydell wrote:
>
> Hi; this series does a complete conversion of qemu-doc from
> Texinfo to rST, including the hxtool-generated parts and
> creation of the qemu.1 manpage from rST.
>
Advance notice: I would like to put these into a pull
request at the end of th
On Wed, Feb 05, 2020 at 09:17:40AM -0500, Peter Xu wrote:
> This is still RFC because the kernel counterpart is still under
> review. However please feel free to read into the code a bit if you
> want; they've even got rich comments so not really in WIP status
> itself. Any kind of comments are g
; into
> staging (2020-03-03 12:03:59 +)
>
> are available in the Git repository at:
>
> https://gitlab.com/dagrh/qemu.git tags/pull-virtiofs-20200303
>
> for you to fetch changes up to bdfd66788349acc43cd3f1298718ad491663cfcc:
>
On Tue, 3 Mar 2020 at 16:37, Markus Armbruster wrote:
>
> Based-on: <20200227144531.24309-1-arm...@redhat.com>
>
> This series extends QMP introspection to cover deprecation.
> Additionally, new option -compat lets you configure what to do when
> deprecated interfaces get used. This is intended f
Am 30.01.2020 um 13:34 hat Maxim Levitsky geschrieben:
> Signed-off-by: Maxim Levitsky
> Reviewed-by: Dr. David Alan Gilbert
Very long subject line. I suppose the license notice should be in the
body instead.
> block/monitor/block-hmp-cmds.c | 56 --
> include/b
> These errors are probably due to the Makefile.objs changes in your
commit:
If I am not wrong, we need to add a rule i.e *"
common-obj-$(CONFIG_TESTPCI) += testpci.o "* in Makefile.objs to compile
custom device in Qemu.
Shall I should remove that rule to remove the errors?
On Tue, 3 Mar 2020 at
Am 30.01.2020 um 13:34 hat Maxim Levitsky geschrieben:
> This is only used by hmp_drive_add.
> The code is just a bit shorter this way.
>
> No functional changes
>
> Signed-off-by: Maxim Levitsky
> Reviewed-by: Markus Armbruster
Shouldn't the subject say "inline" rather than "uninline"?
Kevin
Am 28.02.2020 um 12:16 hat Stefan Hajnoczi geschrieben:
> On Mon, Feb 24, 2020 at 03:29:48PM +0100, Kevin Wolf wrote:
> > This series adds a new tool 'qemu-storage-daemon', which can be used to
> > export and perform operations on block devices. There is some overlap
> > between qemu-img/qemu-nbd a
The value of @qmp_schema_qlit is generated from an expression tree.
Tree nodes are created in several places. Factor out the common code
into _make_tree(). This isn't much of a win now. It will pay off
when we add feature flags in the next few commits.
Signed-off-by: Markus Armbruster
---
scr
In v4.1.0, we added feature flags just to struct types (commit
6a8c0b5102^..f3ed93d545), to satisfy an immediate need (commit
c9d4070991 "file-posix: Add dynamic-auto-read-only QAPI feature"). In
v4.2.0, we added them to commands (commit 23394b4c39 "qapi: Add
feature flags to commands") to satisfy
This policy makes deprecated commands fail like this:
---> {"execute": "query-cpus"}
<--- {"error": {"class": "CommandNotFound", "desc": "Deprecated command
query-cpus disabled by policy"}}
When the command is removed, the error will change to
<--- {"error": {"class": "CommandNotFou
This policy suppresses deprecated command results and deprecated
events, and thus permits "testing the future".
Example:
---> {"execute": "query-cpus-fast"}
<--- {"return": [{"thread-id": 9805, "props": {"core-id": 0, "thread-id":
0, "socket-id": 0}, "qom-path": "/machine/unattached/devi
QAPISchemaObjectTypeVariants represents both object type and alternate
type variants. Rename to QAPISchemaVariants.
Rename QAPISchemaObjectTypeVariant the same way.
Signed-off-by: Markus Armbruster
---
scripts/qapi/schema.py | 22 +++---
1 file changed, 11 insertions(+), 11 del
Signed-off-by: Markus Armbruster
---
scripts/qapi/commands.py | 6 +++---
scripts/qapi/doc.py| 10 +-
scripts/qapi/introspect.py | 10 +-
scripts/qapi/schema.py | 36 --
scripts/qapi/types.py | 4 ++--
script
Add feature 'deprecated' to the deprecated QMP commands, so their
deprecation becomes visible in output of query-qmp-schema. Looks like
this:
{"name": "query-cpus",
"ret-type": "[164]",
"meta-type": "command",
"arg-type": "0",
---> "features": ["deprecated"]}
Management applic
We generate the value of qmp_schema_qlit from an expression tree. The
function doing that is named to_qlit(), and its inputs are accumulated
in QAPISchemaGenIntrospectVisitor._qlits. We call both its input and
its output "qlit". This is confusing.
Use "tree" for input, and "qlit" only for outpu
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