> -Original Message-
> From: Michael S. Tsirkin [mailto:m...@redhat.com]
> Sent: Monday, February 17, 2020 9:09 PM
> To: miaoyubo
> Cc: peter.mayd...@linaro.org; shannon.zha...@gmail.com; Xiexiangyou
> ; imamm...@redhat.com; qemu-
> de...@nongnu.org
> Subject: Re: [RFC v2 1/1] arm: acpi:
On Fri, 2020-02-14 at 14:21 +, Daniel P. Berrangé wrote:
> On Fri, Feb 14, 2020 at 03:00:34PM +0100, Marc-André Lureau wrote:
> > Hi
> >
> > On Fri, Feb 14, 2020 at 2:24 PM Boeuf, Sebastien
> > wrote:
> > > Hi Marc-Andre,
> > >
> > > On Tue, 2020-02-11 at 22:24 +0100, Marc-André Lureau wrote
On Fri, 2020-02-14 at 15:00 +0100, Marc-André Lureau wrote:
> Hi
>
> On Fri, Feb 14, 2020 at 2:24 PM Boeuf, Sebastien
> wrote:
> > Hi Marc-Andre,
> >
> > On Tue, 2020-02-11 at 22:24 +0100, Marc-André Lureau wrote:
> > > Hi
> > >
> > > On Tue, Feb 11, 2020 at 4:24 PM Boeuf, Sebastien
> > > wrot
x27;fdt' after reset the machine (2020-02-17 11:27:23 +1100)
>>>
>>> are available in the Git repository at:
>>>
>>> g...@github.com:aik/qemu.git tags/qemu-slof-20200217
>>>
>>> for you to fetch changes up to ea9a03e5
On 2/17/20 6:34 PM, Igor Mammedov wrote:
Switch to using generic main RAM allocation. To do this set
MachineClass::default_ram_id to m68k_mac.ram and use
MachineState::ram instead of manually initializing
RAM memory region.
Signed-off-by: Igor Mammedov
Acked-by: Laurent Vivier
---
hw/m68k/q8
Public bug reported:
I'm using Arch Linux with qemu 4.2 and blktrace to monitor discard
commands as they are sent to the hardware. Blktrace shows nothing as
the VM is trimming the SSDs.
I downgraded to qemu 4.1.1 and blktrace shows lots of discard commands
as the VM is trimming.
Kernel version
On 2/17/20 6:34 PM, Igor Mammedov wrote:
memory_region_allocate_system_memory() API is going away, so
replace it with memdev allocated MemoryRegion. The later is
initialized by generic code, so board only needs to opt in
to memdev scheme by providing
MachineClass::default_ram_id
and using Mach
On 2/17/20 6:34 PM, Igor Mammedov wrote:
memory_region_allocate_system_memory() API is going away, so
replace it with memdev allocated MemoryRegion. The later is
initialized by generic code, so board only needs to opt in
to memdev scheme by providing
MachineClass::default_ram_id
and using Mach
On 2/17/20 8:11 PM, Richard Henderson wrote:
On 2/17/20 9:33 AM, Igor Mammedov wrote:
memory_region_allocate_system_memory() API is going away, so
replace it with memdev allocated MemoryRegion. The later is
initialized by generic code, so board only needs to opt in
to memdev scheme by providing
On 2/17/20 6:33 PM, Igor Mammedov wrote:
memory_region_allocate_system_memory() API is going away, so
replace it with memdev allocated MemoryRegion. The later is
initialized by generic code, so board only needs to opt in
to memdev scheme by providing
MachineClass::default_ram_id
and using Mach
On 2/17/20 6:33 PM, Igor Mammedov wrote:
memory_region_allocate_system_memory() API is going away, so
replace it with memdev allocated MemoryRegion. The later is
initialized by generic code, so board only needs to opt in
to memdev scheme by providing
MachineClass::default_ram_id
and using Mach
On 2/17/20 6:33 PM, Igor Mammedov wrote:
memory_region_allocate_system_memory() API is going away, so
replace it with memdev allocated MemoryRegion. The later is
initialized by generic code, so board only needs to opt in
to memdev scheme by providing
MachineClass::default_ram_id
and using Mach
On 2/17/20 7:56 PM, Richard Henderson wrote:
On 2/17/20 9:33 AM, Igor Mammedov wrote:
/* We need to initialize our memory */
if (machine->ram_size > (FSL_IMX25_SDRAM0_SIZE + FSL_IMX25_SDRAM1_SIZE)) {
-warn_report("RAM size " RAM_ADDR_FMT " above max supported, "
+erro
On 2/17/20 9:27 PM, Niek Linnenbank wrote:
Hi Philippe,
On Wed, Feb 12, 2020 at 11:12 PM Philippe Mathieu-Daudé
mailto:phi...@redhat.com>> wrote:
On 2/12/20 10:47 PM, Niek Linnenbank wrote:
> Hi all,
>
> Short status update regarding this series.
>
> Currently I a
Cc'ing Niek.
On 2/17/20 9:48 PM, Guenter Roeck wrote:
Instantiate EHCI and OHCI controllers on Allwinner A10.
The first patch in the series moves the declaration of EHCISysBusState
from hcd-ohci.c to hcd-ohci.h. This lets us add the structure to
AwA10State. Similar, TYPE_SYSBUS_OHCI is moved to
On 2/17/20 10:08 PM, Guenter Roeck wrote:
Up to now, the mainstone machine only boots if two flash images are
provided. This is not really necessary; the machine can boot from initrd
or from SD without it. At the same time, having to provide dummy flash
images is a nuisance and does not add any r
On 2/17/20 10:09 PM, Guenter Roeck wrote:
Up to now, the z2 machine only boots if a flash image is provided.
This is not really necessary; the machine can boot from initrd or from
SD without it. At the same time, having to provide dummy flash images
is a nuisance and does not add any real value.
Register 0x818 is documented as 'undefined', and register
0x82c is not documented. Refuse their access.
Acked-by: Helge Deller
Signed-off-by: Philippe Mathieu-Daudé
---
hw/hppa/dino.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/hppa/dino.c b/hw/hppa/dino.c
index be
Easy fix for the overrun reported by Coverity.
Since v1:
- Fixed description to cover CID 1419387 (reported by Peter)
(no code change)
Supersedes: <20200213234148.8434-1-f4...@amsat.org>
Philippe Mathieu-Daudé (4):
hw/hppa/dino: Add comments with register name
hw/hppa/dino: Fix reg800_keep
Only 24 bits of the PCIROR register are documented
(see pp. 37 of datasheet referenced in this file header).
Acked-by: Helge Deller
Signed-off-by: Philippe Mathieu-Daudé
---
hw/hppa/dino.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/hppa/dino.c b/hw/hppa/dino.c
index
Add a comment with the name of each register in the 0x800-0x8ff range.
Acked-by: Helge Deller
Signed-off-by: Philippe Mathieu-Daudé
---
hw/hppa/dino.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/hw/hppa/dino.c b/hw/hppa/dino.c
index 9797a7f0d9.
Coverity reports:
*** CID 1419387: Memory - illegal accesses (OVERRUN)
/hw/hppa/dino.c: 267 in dino_chip_read_with_attrs()
261 val = s->ilr & s->imr & s->icr;
262 break;
263 case DINO_TOC_ADDR:
264 val = s->toc_addr;
265 break
On Tue, Feb 18, 2020 at 7:19 AM Philippe Mathieu-Daudé wrote:
> On Mon, Feb 17, 2020 at 6:37 PM Peter Maydell
> wrote:
> > On Thu, 13 Feb 2020 at 23:44, Philippe Mathieu-Daudé
> > wrote:
> >
> >
> > > Fixes: Covertiy CID 1419393 and 1419394 (commit 18092598a5)
> > > Signed-off-by: Philippe Mat
On Mon, Feb 17, 2020 at 6:37 PM Peter Maydell wrote:
> On Thu, 13 Feb 2020 at 23:44, Philippe Mathieu-Daudé wrote:
>
>
> > Fixes: Covertiy CID 1419393 and 1419394 (commit 18092598a5)
> > Signed-off-by: Philippe Mathieu-Daudé
>
> I think this also fixes CID 1419387 ?
Ah I missed this one, indeed
On 2/17/20 11:35 PM, Laurent Vivier wrote:
This series copies the files syscall.tbl from linux v5.5 and generates
the file syscall_nr.h from them.
[...]
Laurent Vivier (22):
linux-user: introduce parameters to generate syscall_nr.h
linux-user,alpha: add syscall table generation support
On 2/17/20 9:06 PM, Dr. David Alan Gilbert wrote:
* Philippe Mathieu-Daudé (phi...@redhat.com) wrote:
Fix warning reported by Clang static code analyzer:
CC tools/virtiofsd/fuse_lowlevel.o
tools/virtiofsd/fuse_lowlevel.c:195:9: warning: Value stored to 'error' is
never read
As I understand the above algorithm, we find a vfio_dma
overlapping the request and populate the bitmap for that range. Then
we go back and put_user() for each byte that we touched. We could
instead simply work on a one byte buffer as we enumerate the requested
range and do a put_user() ev
05943fb4ca41f626078014c0327781815c6584c5:
ppc: free 'fdt' after reset the machine (2020-02-17 11:27:23 +1100)
are available in the Git repository at:
g...@github.com:aik/qemu.git tags/qemu-slof-20200217
for you to fetch changes up to ea9a03e5aa023c5391bab5259898475d0298aac2:
pseries: Update SLOF firmware i
This test case has the same tests as tests/virtio-blk-test.c except for
tests have block_resize.
Signed-off-by: Coiby Xu
---
tests/Makefile.include | 3 +-
tests/qtest/Makefile.include| 2 +
tests/qtest/libqos/vhost-user-blk.c | 126 +
tests/qtest/libqos/vhost-user-b
By making use of libvhost, multiple block device drives can be exported
and each drive can serve multiple clients simultaneously.
Since vhost-user-server needs a block drive to be created first, delay
the creation of this object.
Signed-off-by: Coiby Xu
---
Makefile.target | 1
Sharing QEMU devices via vhost-user protocol
Signed-off-by: Coiby Xu
---
util/Makefile.objs | 3 +
util/vhost-user-server.c | 427 +++
util/vhost-user-server.h | 56 +
3 files changed, 486 insertions(+)
create mode 100644 util/vhost-user-server.c
vhost-user-blk could have played as vhost-user backend but it only supports raw
file and don't support VIRTIO_BLK_T_DISCARD and VIRTIO_BLK_T_WRITE_ZEROES
operations on raw file (ioctl(fd, BLKDISCARD) is only valid for real
block device).
In the future Kevin's qemu-storage-daemon will be used to re
Previously libvhost dispatch events in its own GMainContext. Now vhost-user
client's kick event can be dispatched in block device drive's AioContext
thus IOThread is supported. And also allow vu_message_read and
vu_kick_cb to be replaced so QEMU can run them as coroutines.
Signed-off-by: Coiby Xu
v4:
* add object properties in class_init
* relocate vhost-user-blk-test
* other changes including using SocketAddress, coding style, etc.
v3:
* separate generic vhost-user-server code from vhost-user-blk-server
code
* re-write vu_message_read and kick hander function as coroutines to
d
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
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https://bugs.launchpad.net/bugs/1836501
Title:
cpu_address
This supports SError injection, which will be used by "virt" board to
simulating the behavior of NMI injection in next patch. As Peter Maydell
suggested, this adds a new interrupt (ARM_CPU_SERROR), which is parallel
to CPU_INTERRUPT_HARD. The backend depends on if kvm is enabled or not.
kvm_vcpu_io
This implements the backend to support HMP/QMP "nmi" command, which is
used to inject NMI interrupt to crash guest for debugging purpose. As
ARM architecture doesn't have NMI supported, so we're simulating the
behaviour by injecting SError or data abort to guest for "virt" board.
An additonal IRQ
This series simulates the behavior of receiving NMI interrupt for "virt"
board. First of all, a new interrupt (SError) is supported for each CPU.
The backend is either sending error events through kvm module or emulating
the bahavior when TCG is enabled. The outcome is SError or data abort is
raise
This supports virtual SError injection, which can be used to inject
SError to guest running on the emulated hypervisor. The functionality
is enabled only when we're in non-secured mode and {HCR.TGE, HCR.AMO}
are set to {0, 1}. Also, it can be masked by PState.A bit. Apart from
that, the implementat
Public bug reported:
QEMU emulator version 4.2.50
kernel 5.3.0-29-generic
host Ubuntu 19.10
guest: Android 8.1
While trying to compile I get the following error
qemu/slirp/src/misc.c:146: undefined reference to
`g_spawn_async_with_fds'
** Affects: qemu
Importance: Undecided
Statu
This patch enables the playback of audio on a Mac OS 9 or Mac OS X guest.
Signed-off-by: John Arbuckle
---
v4 changes:
- Switched to using HWADDR_PRIx in several debug statements.
v3 changes:
- Updated the location of patched code in hw/ppc/kconfig.
- Removed setting the props variable in scream
On 12/5/19 10:17 AM, Peter Maydell wrote:
> On Fri, 11 Oct 2019 at 14:50, Richard Henderson
> wrote:
>>
>> This is DC GVA and DC GZVA.
>>
>> Signed-off-by: Richard Henderson
>> ---
>> v2: Use allocation_tag_mem + memset.
>> v3: Require pre-cleaned addresses.
>> ---
>
>> diff --git a/target/arm/m
On 12/5/19 10:58 AM, Peter Maydell wrote:
> On Fri, 11 Oct 2019 at 14:50, Richard Henderson
> wrote:
>>
>> This data access was forgotten in the previous patch.
>>
>> Fixes: 3a471103ac1823ba
>> Signed-off-by: Richard Henderson
>> ---
>> target/arm/translate-a64.c | 2 +-
>> 1 file changed, 1 ins
chine (2020-02-17 11:27:23 +1100)
>>
>> are available in the Git repository at:
>>
>> g...@github.com:aik/qemu.git tags/qemu-slof-20200217
>>
>> for you to fetch changes up to ea9a03e5aa023c5391bab5259898475d02
> are available in the Git repository at:
>>
>> g...@github.com:aik/qemu.git tags/qemu-slof-20200217
>>
>> for you to fetch changes up to ea9a03e5aa023c5391bab5259898475d0298aac2:
>>
>> pseries: Update SLOF firmware image (2020-02-17 13:08:59 +1100)
&
Public bug reported:
On 32-bit and 64-bit ARM platforms, setting HCR.TSW is supposed to "Trap
data or unified cache maintenance instructions that operate by Set/Way."
Quoting the ARM manual:
If EL1 is using AArch64 state, accesses to DC ISW, DC CSW, DC CISW are trapped
to EL2, reported using EC
Anything else I should supply to move status away from incomplete?
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https://bugs.launchpad.net/bugs/1859920
Title:
daemoniz not working on MacOS
Status in QEMU:
Incomplete
Bug desc
The Xunlong Orange Pi PC machine is a functional ARM machine
based on the Allwinner H3 System-on-Chip. It supports mainline
Linux, U-Boot, NetBSD and is covered by acceptance tests.
This commit adds a documentation text file with a description
of the machine and instructions for the user.
Signed-
The Allwinner System on Chip families sun4i and above contain
an integrated storage controller for Secure Digital (SD) and
Multi Media Card (MMC) interfaces. This commit adds support
for the Allwinner SD/MMC storage controller with the following
emulated features:
* DMA transfers
* Direct FIFO I
From: Philippe Mathieu-Daudé
This test boots Ubuntu Bionic on a OrangePi PC board.
As it requires 1GB of storage, and is slow, this test is disabled
on automatic CI testing.
It is useful for workstation testing. Currently Avocado timeouts too
quickly, so we can't run userland commands.
The ker
The Allwinner Sun8i System on Chip family includes an Ethernet MAC (EMAC)
which provides 10M/100M/1000M Ethernet connectivity. This commit
adds support for the Allwinner EMAC from the Sun8i family (H2+, H3, A33, etc),
including emulation for the following functionality:
* DMA transfers
* MII int
From: Philippe Mathieu-Daudé
The kernel image and DeviceTree blob are built by the Armbian
project (based on Debian):
https://www.armbian.com/orange-pi-pc/
The SD image is from the kernelci.org project:
https://kernelci.org/faq/#the-code
If ARM is a target being built, "make check-acceptance" w
Allwinner System-on-Chips usually contain a Real Time Clock (RTC)
for non-volatile system date and time keeping. This commit adds a generic
Allwinner RTC device that supports the RTC devices found in Allwinner SoC
family sun4i (A10), sun7i (A20) and sun6i and newer (A31, H2+, H3, etc).
The followin
The Security Identifier device found in various Allwinner System on Chip
designs gives applications a per-board unique identifier. This commit
adds support for the Allwinner Security Identifier using a 128-bit
UUID value as input.
Signed-off-by: Niek Linnenbank
---
include/hw/arm/allwinner-h3.h
From: Philippe Mathieu-Daudé
This test boots U-Boot then NetBSD (stored on a SD card) on
a OrangePi PC board.
As it requires ~1.3GB of storage, it is disabled by default.
U-Boot is built by the Debian project [1], and the SD card image
is provided by the NetBSD organization [2].
Once the compr
In the Allwinner H3 SoC the SDRAM controller is responsible
for interfacing with the external Synchronous Dynamic Random
Access Memory (SDRAM). Types of memory that the SDRAM controller
supports are DDR2/DDR3 and capacities of up to 2GiB. This commit
adds emulation support of the Allwinner H3 SDRAM
From: Philippe Mathieu-Daudé
This test boots a Linux kernel on a OrangePi PC board and verify
the serial output is working.
The kernel image and DeviceTree blob are built by the Armbian
project (based on Debian):
https://www.armbian.com/orange-pi-pc/
The cpio image used comes from the linux-bui
The Allwinner H3 System on Chip has an System Control
module that provides system wide generic controls and
device information. This commit adds support for the
Allwinner H3 System Control module.
Signed-off-by: Niek Linnenbank
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daud
Various Allwinner System on Chip designs contain multiple processors
that can be configured and reset using the generic CPU Configuration
module interface. This commit adds support for the Allwinner CPU
configuration interface which emulates the following features:
* CPU reset
* CPU status
Sign
The Clock Control Unit is responsible for clock signal generation,
configuration and distribution in the Allwinner H3 System on Chip.
This commit adds support for the Clock Control Unit which emulates
a simple read/write register interface.
Signed-off-by: Niek Linnenbank
Reviewed-by: Philippe Mat
From: Philippe Mathieu-Daudé
This test boots a Linux kernel on a OrangePi PC board and verify
the serial output is working.
The kernel image and DeviceTree blob are built by the Armbian
project (based on Debian):
https://www.armbian.com/orange-pi-pc/
If ARM is a target being built, "make check-
The Xunlong Orange Pi PC is an Allwinner H3 System on Chip
based embedded computer with mainline support in both U-Boot
and Linux. The board comes with a Quad Core Cortex A7 @ 1.3GHz,
1GiB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and
various other I/O. This commit add support for the Xunlong
O
A real Allwinner H3 SoC contains a Boot ROM which is the
first code that runs right after the SoC is powered on.
The Boot ROM is responsible for loading user code (e.g. a bootloader)
from any of the supported external devices and writing the downloaded
code to internal SRAM. After loading the SoC b
Dear QEMU developers,
Hereby I would like to contribute the following set of patches to QEMU
which add support for the Allwinner H3 System on Chip and the
Orange Pi PC machine. The following features and devices are supported:
* SMP (Quad Core Cortex A7)
* Generic Interrupt Controller configura
The Allwinner H3 System on Chip contains multiple USB 2.0 bus
connections which provide software access using the Enhanced
Host Controller Interface (EHCI) and Open Host Controller
Interface (OHCI) interfaces. This commit adds support for
both interfaces in the Allwinner H3 System on Chip.
Signed-
The Allwinner H3 is a System on Chip containing four ARM Cortex A7
processor cores. Features and specifications include DDR2/DDR3 memory,
SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and
various I/O modules. This commit adds support for the Allwinner H3
System on Chip.
Signed-off-
On 12/5/19 8:12 AM, Peter Maydell wrote:
> For arm_cpu_tlb_fill() which handles prefetch/data aborts
> we just have a separate much simpler codepath for
> CONFIG_USER_ONLY which doesn't call arm_deliver_fault().
> I think being consistent here about how we handle the
> CONFIG_USER_ONLY case would h
Split into syscall32_nr.h (n32) and syscall64_nr.h (n64)
o32 interface is in mips/syscall_nr.h
Signed-off-by: Laurent Vivier
---
linux-user/mips64/syscall32_nr.h | 375
linux-user/mips64/syscall64_nr.h | 351 +++
linux-user/mips64/syscall_nr.h | 719 +-
5943fb4ca41f626078014c0327781815c6584c5:
> > >
> > > ppc: free 'fdt' after reset the machine (2020-02-17 11:27:23 +1100)
> > >
> > > are available in the Git repository at:
> > >
> > > g...@github.com:aik/qemu.git tags/
Add a script to update the file from strace github and run it
Signed-off-by: Laurent Vivier
---
linux-user/mips/syscall-args-o32.c.inc | 874 -
scripts/update-mips-syscall-args.sh| 57 ++
2 files changed, 493 insertions(+), 438 deletions(-)
create mode 100755 script
Copy syscall.tbl and syscallhdr.sh from linux/arch/ppc/kernel/syscalls v5.5
Update syscallhdr.sh to generate QEMU syscall32_nr.h and syscall64_nr.h
and to not generate the entry if entry point is sys_ni_syscall.
Fix ppc/signal.c to define do_sigreturn() for TARGET_ABI32.
Signed-off-by: Laurent Vi
Copy syscall.tbl and syscallhdr.sh from linux/arch/sh/kernel/syscalls v5.5
Update syscallhdr.sh to generate QEMU syscall_nr.h
Signed-off-by: Laurent Vivier
---
configure| 1 +
linux-user/Makefile.objs | 1 +
linux-user/sh4/Makefile.objs | 5 +
linux-user/sh4/syscall
We don't support other 32bit architecture.
Update file to comply with coding style (TAB).
Signed-off-by: Laurent Vivier
---
linux-user/s390x/syscall_nr.h | 313 +-
1 file changed, 123 insertions(+), 190 deletions(-)
diff --git a/linux-user/s390x/syscall_nr.h b/li
Run scripts/update-syscalltbl.sh with linux commit 0bf999f9c5e7
Signed-off-by: Laurent Vivier
---
linux-user/arm/syscall.tbl| 2 ++
linux-user/hppa/syscall.tbl | 2 ++
linux-user/i386/syscall_32.tbl| 2 ++
linux-user/m68k/syscall.tbl | 4 +++-
linux-user/microblaze/syscal
Copy syscall.tbl and syscallhdr.sh from linux/arch/sparc/kernel/syscalls v5.5
Update syscallhdr.sh to generate QEMU syscall_nr.h
Signed-off-by: Laurent Vivier
---
configure| 3 +
linux-user/Makefile.objs | 2 +
linux-user/sparc/Makefile.objs | 5 +
linux-u
Copy syscall_n32.tbl, syscall_n64.tbl and syscallhdr.sh from
linux/arch/parisc/kernel/syscalls v5.5
Update syscallhdr.sh to generate QEMU syscall_nr.h
Move the offsets (6000 for n32 and 5000 for n64) from the file to
the Makefile.objs to be passed to syscallhdr.sh
Signed-off-by: Laurent Vivier
-
Copy syscall_32.tbl and syscallhdr.sh from linux/arch/x86/kernel/syscalls v5.5
Update syscallhdr.sh to generate QEMU syscall_nr.h
Disable arch_prctl in syscall_32.tbl because linux-user/syscall.c only
defines do_arch_prctl() with TARGET_ABI32, and TARGET_ABI32 is never
defined for TARGET_I386 (Thi
Copy syscall.tbl and syscallhdr.sh from linux/arch/arm/tools/syscalls v5.5
Update syscallhdr.sh to generate QEMU syscall_nr.h
Signed-off-by: Laurent Vivier
---
configure| 1 +
linux-user/Makefile.objs | 3 +-
linux-user/arm/Makefile.objs | 8 +
linux-user/arm/syscal
Copy syscall_64.tbl and syscallhdr.sh from linux/arch/x86/kernel/syscalls v5.5
Update syscallhdr.sh to generate QEMU syscall_nr.h
Signed-off-by: Laurent Vivier
---
configure| 1 +
linux-user/Makefile.objs | 1 +
linux-user/x86_64/Makefile.objs | 5 +
linux-
Move content of mips_syscall_args to mips-syscall-args-o32.c.inc to
ease automatic update. No functionnal change
Signed-off-by: Laurent Vivier
---
linux-user/mips/cpu_loop.c | 440 +
linux-user/mips/syscall-args-o32.c.inc | 438
2 file
Copy syscall.tbl and syscallhdr.sh from
linux/arch/mips/kernel/syscalls/syscall_o32.tbl v5.5
Update syscallhdr.sh to generate QEMU syscall_nr.h
Move the offset (4000) from the file to the Makefile.objs to be passed
to syscallhdr.sh
Rename on the fly fadvise64 to fadvise64_64.
Signed-off-by: Laure
Copy syscall.tbl and syscallhdr.sh from linux/arch/xtensa/kernel/syscalls v5.5
Update syscallhdr.sh to generate QEMU syscall_nr.h
Signed-off-by: Laurent Vivier
---
configure | 1 +
linux-user/Makefile.objs| 1 +
linux-user/xtensa/Makefile.objs | 5 +
linux-use
Copy syscall.tbl and syscallhdr.sh from linux/arch/microblaze/kernel/syscalls
v5.5
Update syscallhdr.sh to generate QEMU syscall_nr.h
Signed-off-by: Laurent Vivier
---
configure | 1 +
linux-user/Makefile.objs| 1 +
linux-user/microblaze/Makefile.objs |
Split into syscall32_nr.h (ppc, ppc64abi32) and syscall64_nr.h (ppc64, ppc64le)
Signed-off-by: Laurent Vivier
---
linux-user/ppc/syscall32_nr.h | 390 +
linux-user/ppc/syscall64_nr.h | 381
linux-user/ppc/syscall_nr.h | 394 +
Copy syscall.tbl from linux/arch/s390x/kernel/syscalls v5.5
Copy syscallhdr.sh from m68k.
Signed-off-by: Laurent Vivier
---
configure | 1 +
linux-user/Makefile.objs | 1 +
linux-user/s390x/Makefile.objs | 5 +
linux-user/s390x/syscall.tbl | 440 +++
Copy syscall.tbl and syscallhdr.sh from linux/arch/m68k/kernel/syscalls v5.5
Update syscallhdr.sh to generate QEMU syscall_nr.h
Signed-off-by: Laurent Vivier
---
configure | 1 +
linux-user/Makefile.objs | 1 +
linux-user/m68k/Makefile.objs | 5 +
linux-user/m68k/s
Copy syscall.tbl and syscallhdr.sh from linux/arch/alpha/kernel/syscalls v5.5
Update syscallhdr.sh to generate QEMU syscall_nr.h
Signed-off-by: Laurent Vivier
---
configure | 1 +
linux-user/Makefile.objs | 2 +
linux-user/alpha/Makefile.objs | 5 +
linux-user/al
This will be used when we'll import syscall.tbl from the kernel
Signed-off-by: Laurent Vivier
---
Makefile.target | 3 ++-
configure | 3 +++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/Makefile.target b/Makefile.target
index 6e61f607b14a..9babf2643e0b 100644
--- a/Makefi
scripts/update-syscalltbl.sh has the list of syscall.tbl to update and
can copy them from the linux source directory
Signed-off-by: Laurent Vivier
---
MAINTAINERS | 1 +
scripts/update-syscalltbl.sh | 49
2 files changed, 50 insertions(+)
c
Copy syscall.tbl and syscallhdr.sh from linux/arch/parisc/kernel/syscalls v5.5
Update syscallhdr.sh to generate QEMU syscall_nr.h
Signed-off-by: Laurent Vivier
---
configure | 1 +
linux-user/Makefile.objs | 1 +
linux-user/hppa/Makefile.objs | 5 +
linux-user/hppa
This series copies the files syscall.tbl from linux v5.5 and generates
the file syscall_nr.h from them.
This is done for all the QEMU targets that have a syscall.tbl
in the linux source tree: mips, mips64, i386, x86_64, sparc, s390x,
ppc, arm, microblaze, sh4, xtensa, m68k, hppa and alpha.
tilegx
I tested in AArch64 mode and it worked for me. Looking at the patch, we
might be missing trapping for "TTBCR"in AA32 though.
--
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https://bugs.launchpad.net/bugs/1855072
Title:
ARM: HCR.TV
On 12/3/19 6:07 AM, Peter Maydell wrote:
> The load-literal case is implicitly tag-unchecked because
> the address calculation doesn't go via clean_data_tbi(), right?
Yes.
r~
Up to now, the z2 machine only boots if a flash image is provided.
This is not really necessary; the machine can boot from initrd or from
SD without it. At the same time, having to provide dummy flash images
is a nuisance and does not add any real value. Make it optional.
Signed-off-by: Guenter Ro
Up to now, the mainstone machine only boots if two flash images are
provided. This is not really necessary; the machine can boot from initrd
or from SD without it. At the same time, having to provide dummy flash
images is a nuisance and does not add any real value. Make it optional.
Signed-off-by:
On Tue, 18 Feb 2020 00:43:48 +0530
Kirti Wankhede wrote:
> On 2/14/2020 4:50 AM, Alex Williamson wrote:
> > On Fri, 14 Feb 2020 01:41:35 +0530
> > Kirti Wankhede wrote:
> >
> >>
> >>
> >>
> >> +static int vfio_iova_dirty_bitmap(struct vfio_iommu *iommu,
> >> dma_addr_t io
Instantiate EHCI and OHCI controllers on Allwinner A10. OHCI ports are
modeled as companions of the respective EHCI ports.
With this patch applied, USB controllers are discovered and instantiated
when booting the cubieboard machine with a recent Linux kernel.
ehci-platform 1c14000.usb: EHCI Host
We'll use this property in a follow-up patch to insantiate an EHCI
bus with companion support.
Reviewed-by: Gerd Hoffmann
Signed-off-by: Guenter Roeck
---
v3: Rebased to master
Added Gerd's Reviewed-by: tag
v2: Added patch
hw/usb/hcd-ehci-sysbus.c | 2 ++
1 file changed, 2 insertions(+)
d
We need to be able to use OHCISysBusState outside hcd-ohci.c, so move it
to its include file.
Reviewed-by: Gerd Hoffmann
Signed-off-by: Guenter Roeck
---
v3: Rebased to master
Added Gerd's Reviewed-by: tag
v2: no changes
hw/usb/hcd-ohci.c | 15 ---
hw/usb/hcd-ohci.h | 16 ++
Instantiate EHCI and OHCI controllers on Allwinner A10.
The first patch in the series moves the declaration of EHCISysBusState
from hcd-ohci.c to hcd-ohci.h. This lets us add the structure to
AwA10State. Similar, TYPE_SYSBUS_OHCI is moved to be able to use it
outside its driver.
The second patch
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