Re: [PATCH 2/2] tests/acceptance/integratorcp: Verify Tux is displayed on framebuffer

On 31/01/2020 22.11, Philippe Mathieu-Daudé wrote: > Add a test that verifies the Tux logo is displayed on the framebuffer. > > We simply follow the OpenCV "Template Matching with Multiple Objects" > tutorial, replacing Lionel Messi by Tux: > https://docs.opencv.org/4.2.0/d4/dc6/tutorial_py_templa

Re: [PATCH 1/2] tests/acceptance: Extract boot_integratorcp() from test_integratorcp()

On 31/01/2020 22.11, Philippe Mathieu-Daudé wrote: > As we want to re-use this code, extract it as a new function. > Since we are using the PL011 serial console, add a Avocado tag > to ease filtering of tests. > > Signed-off-by: Philippe Mathieu-Daudé > --- > tests/acceptance/machine_arm_integra

[PATCH v3] target/arm/monitor: query-cpu-model-expansion crashed qemu when using machine type none

Commit e19afd56 mentioned that target-arm only supports queryable cpu models 'max', 'host', and the current type when KVM is in use. The logic works well until using machine type none. For machine type none, cpu_type will be null if cpu option is not set by command line, strlen(cpu_type) will term

[Bug 1859291] Re: RISC-V incorrect exception generated

Do you have steps to reproduce this? -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1859291 Title: RISC-V incorrect exception generated Status in QEMU: New Bug description: When using 'ecall'

Re: [Bug 1859291] [NEW] RISC-V incorrect exception generated

Do you have steps to reproduce this? Alistair On Sat, Jan 11, 2020 at 8:25 AM Teodori Serge wrote: > > Public bug reported: > > When using 'ecall' from supervisor mode, user exception is raised > instead of supervisor exception. The problem is located under > 'target/riscv/insn_trans/trans_privi

[PATCH v2 30/35] target/riscv: Implement second stage MMU

Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu.h| 1 + target/riscv/cpu_helper.c | 193 ++ 2 files changed, 175 insertions(+), 19 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index aa04e5cca7..a

[PATCH v2 28/35] target/riscv: Respect MPRV and SPRV for floating point ops

mark_fs_dirty() is the only place in translate.c that uses the virt_enabled bool. Let's respect the contents of MSTATUS.MPRV and HSTATUS.SPRV when setting the bool as this is used for performing floating point operations when V=0. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt ---

[PATCH v2 35/35] target/riscv: Allow enabling the Hypervisor extension

Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu.c | 5 + target/riscv/cpu.h | 1 + 2 files changed, 6 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b27066f6a7..c47d10b739 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@

[PATCH v2 27/35] target/riscv: Mark both sstatus and msstatus_hs as dirty

Mark both sstatus and vsstatus as dirty (3). Signed-off-by: Alistair Francis --- target/riscv/translate.c | 12 1 file changed, 12 insertions(+) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index afa2d6eea2..61fe9f03be 100644 --- a/target/riscv/translate.c +++ b

[PATCH v2 33/35] target/riscv: Add support for the 32-bit MSTATUSH CSR

Signed-off-by: Alistair Francis --- target/riscv/cpu.c| 3 +++ target/riscv/cpu.h| 10 ++ target/riscv/cpu_bits.h | 3 +++ target/riscv/cpu_helper.c | 17 + target/riscv/csr.c| 25 + target/riscv/op_helper.c | 4 6

[PATCH v2 26/35] target/riscv: Disable guest FP support based on virtual status

When the Hypervisor extension is in use we only enable floating point support when both status and vsstatus have enabled floating point support. Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/cpu_helper.c b/target

[PATCH v2 31/35] target/riscv: Raise the new execptions when 2nd stage translation fails

Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu_helper.c | 24 ++-- 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 5f96631637..da994aba57 100644 --- a/target/riscv/cpu

[PATCH v2 29/35] target/riscv: Allow specifying MMU stage

Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu_helper.c | 37 - 1 file changed, 28 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 827a38324c..cd2d9341b9 100644 --- a/tar

[PATCH v2 24/35] target/riscv: Remove the hret instruction

The hret instruction does not exist in the new spec versions, so remove it from QEMU. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/insn32.decode | 1 - target/riscv/insn_trans/trans_privileged.inc.c | 5 - 2 files changed, 6 deletions(-)

[PATCH v2 23/35] target/riscv: Add hfence instructions

Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/insn32.decode| 23 ++- .../riscv/insn_trans/trans_privileged.inc.c | 40 +++ 2 files changed, 54 insertions(+), 9 deletions(-) diff --git a/target/riscv/insn32.decode b/tar

[PATCH v2 20/35] target/riscv: Generate illegal instruction on WFI when V=1

Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/op_helper.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index e87c9115bc..455eb28907 100644 --- a/target/riscv/op_helper.c +++ b/target/ri

[PATCH v2 16/35] target/riscv: Extend the MIE CSR to support virtulisation

Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/csr.c | 24 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index c0e942684d..918678789a 100644 --- a/target/riscv/csr.c +++ b/target/riscv

[PATCH v2 25/35] target/riscv: Only set TB flags with FP status if enabled

Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5b889a0065..aa04e5cca7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -332,7 +332,10 @@ static inline void cpu_

[PATCH v2 17/35] target/riscv: Extend the SIP CSR to support virtulisation

Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/csr.c | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 918678789a..2e6700bbeb 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -7

[PATCH v2 34/35] target/riscv: Add the MSTATUS_MPV_ISSET helper macro

Add a helper macro MSTATUS_MPV_ISSET() which will determine if the MSTATUS_MPV bit is set for both 32-bit and 64-bit RISC-V. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu_bits.h | 11 +++ target/riscv/cpu_helper.c | 4 ++-- target/riscv/op_helper.c

[PATCH v2 14/35] target/riscv: Add virtual register swapping function

Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu.h| 11 +++ target/riscv/cpu_bits.h | 7 + target/riscv/cpu_helper.c | 61 +++ 3 files changed, 79 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/

[PATCH v2 11/35] target/riscv: Add Hypervisor CSR access functions

Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/csr.c | 136 - 1 file changed, 134 insertions(+), 2 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index c63b2f980c..bee639e92e 100644 --- a/target/riscv/c

[PATCH v2 13/35] target/riscv: Add Hypervisor machine CSRs accesses

Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/csr.c | 27 +++ 1 file changed, 27 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 3fa8d2cfda..f7333286bd 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -98

[PATCH v2 19/35] target/ricsv: Flush the TLB on virtulisation mode changes

To ensure our TLB isn't out-of-date we flush it on all virt mode changes. Unlike priv mode this isn't saved in the mmu_idx as all guests share V=1. The easiest option is just to flush on all changes. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu_helper.c | 5 +

[PATCH v2 32/35] target/riscv: Set htval and mtval2 on execptions

Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu_helper.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index da994aba57..10786a077b 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/c

[PATCH v2 22/35] target/riscv: Add Hypervisor trap return support

Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/op_helper.c | 62 +--- 1 file changed, 52 insertions(+), 10 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 455eb28907..804936e9d5 100644 --- a/ta

[PATCH v2 21/35] target/riscv: Add hypvervisor trap support

Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 69 +-- 1 file changed, 59 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 98017df33b..e7728cb0ca 100644 --- a/target/riscv/cpu_helper.c +++

[PATCH v2 09/35] target/riscv: Print priv and virt in disas log

Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/translate.c | 8 1 file changed, 8 insertions(+) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 14dc71156b..afa2d6eea2 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate

[PATCH v2 12/35] target/riscv: Add Hypervisor virtual CSRs accesses

Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/csr.c | 116 + 1 file changed, 116 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index bee639e92e..3fa8d2cfda 100644 --- a/target/riscv/csr.c +++ b/targe

[PATCH v2 07/35] target/riscv: Add the force HS exception mode

Add a FORCE_HS_EXCEP mode to the RISC-V virtulisation status. This bit specifies if an exeption should be taken to HS mode no matter the current delegation status. This is used when an exeption must be taken to HS mode, such as when handling interrupts. Signed-off-by: Alistair Francis --- target

[PATCH v2 18/35] target/riscv: Add support for virtual interrupt setting

Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu_helper.c | 33 - 1 file changed, 28 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index e9d75b45d6..3984a1f1ac 100644 --- a/target/

[PATCH v2 05/35] target/riscv: Rename the H irqs to VS irqs

Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu.c | 6 +++--- target/riscv/cpu_bits.h | 12 ++-- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2f62f5ea19..f7a35c74c2 100644 --- a/target/

[PATCH v2 08/35] target/riscv: Fix CSR perm checking for HS mode

Update the CSR permission checking to work correctly when we are in HS-mode. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/csr.c | 18 ++ 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index c

[PATCH v2 15/35] target/riscv: Set VS bits in mideleg for Hyp extension

Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/csr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index f7333286bd..c0e942684d 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -448,6 +448,9 @@ static int r

[PATCH v2 06/35] target/riscv: Add the virtulisation mode

Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu.h| 4 target/riscv/cpu_bits.h | 3 +++ target/riscv/cpu_helper.c | 18 ++ 3 files changed, 25 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c7f7ae5c38..a9

[PATCH v2 02/35] target/riscv: Add the Hypervisor extension

Signed-off-by: Alistair Francis Reviewed-by: Chih-Min Chao Reviewed-by: Palmer Dabbelt --- target/riscv/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 95de9e58a2..010125efd6 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -67,

[PATCH v2 04/35] target/riscv: Add support for the new execption numbers

The v0.5 Hypervisor spec add new execption numbers, let's add support for those. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu.c| 8 target/riscv/cpu_bits.h | 35 +++ target/riscv/cpu_helper.c | 7 +-- t

[PATCH v2 01/35] target/riscv: Convert MIP CSR to target_ulong

The MIP CSR is a xlen CSR, it was only 32-bits to allow atomic access. Now that we don't use atomics for MIP we can change this back to a xlen CSR. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 2 +- 2 files changed, 2 insertions

[PATCH v2 10/35] target/riscv: Dump Hypervisor registers if enabled

Dump the Hypervisor registers and the current Hypervisor state. While we are editing this code let's also dump stvec and scause. Signed-off-by: Alistair Francis Signed-off-by: Atish Patra Reviewed-by: Palmer Dabbelt --- target/riscv/cpu.c | 33 + 1 file changed

[PATCH v2 03/35] target/riscv: Add the Hypervisor CSRs to CPUState

Add the Hypervisor CSRs to CPUState and at the same time (to avoid bisect issues) update the CSR macros for the v0.5 Hyp spec. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu.h | 21 + target/riscv/cpu_bits.h | 34 +--

[PATCH v2 00/35] Add RISC-V Hypervisor Extension v0.5

This patch series adds the RISC-V Hypervisor extension v0.5. This is the latest draft spec of the Hypervisor extension. The Hypervisor extension is disabled by default, so this series should result in no changes to anyone using QEMU unless they enable the extension. The extention can be enabled wi

Re: [PATCH v1 15/36] target/riscv: Convert mstatus to pointers

On Fri, Jan 31, 2020 at 9:31 AM Alistair Francis wrote: > > On Thu, Jan 30, 2020 at 6:48 AM Palmer Dabbelt > wrote: > > > > On Tue, 21 Jan 2020 11:02:01 GMT (+), alistai...@gmail.com wrote: > > > On Wed, Jan 8, 2020 at 11:30 AM Palmer Dabbelt > > > wrote: > > >> > > >> On Mon, 09 Dec 2019

[PATCH 0/1] tests/acceptance: Count Raspberry Pi logos displayed on framebuffer

This is a simple Avocado test that use OpenCV to find the 4 Raspberry Pi logo on the framebuffer screen dump. The resulting match can be visualised at: https://pasteboard.co/ISzNHtx.png It is very fast, around 11 seconds on my laptop. The test probably won't stay in boot_linux_console.py but wil

[PATCH 1/1] tests/acceptance: Count Raspberry Pi logos displayed on framebuffer

Add a test that verifies that each core properly displays the Raspberry Pi logo on the framebuffer device. We simply follow the OpenCV "Template Matching with Multiple Objects" tutorial, replacing Lionel Messi by a raspberrry: https://docs.opencv.org/4.2.0/d4/dc6/tutorial_py_template_matching.html

Re: [PATCH v11 2/2] docs: qcow2: introduce compression type feature

On Fri 31 Jan 2020 07:15:33 PM CET, Vladimir Sementsov-Ogievskiy wrote: > I'm OK with it too, as well as I'm OK with the stricter variant, when > we don't allow incompatible images with zlib set. I don't see any > serious difference. I also think both options are fine. Berto

[PATCH v2] target/arm/monitor: query-cpu-model-expansion crashed qemu when using machine type none

>From commit e19afd56, we know target-arm restricts the list of queryable cpu models to 'max', 'host', and the current type when KVM is in use. The logic works well until using machine type none. For machine type none, cpu_type will be null, and strlen(cpu_type) will terminate process. So I add a

Re: [PATCH 10/11] target/arm: Implement ATS1E1 system registers

On 12/9/19 5:41 AM, Peter Maydell wrote: >> case 1: >> -mmu_idx = secure ? ARMMMUIdx_SE1 : ARMMMUIdx_Stage1_E1; >> +if (ri->crm == 9 && (env->uncached_cpsr & CPSR_PAN)) { >> +mmu_idx = secure ? ARMMMUIdx_SE1_PAN : >> ARMMMUIdx_Stage1_E1_PAN; >> +

Re: [PATCH] target/arm/monitor: query-cpu-model-expansion crashed qemu when using machine type none

Patchew URL: https://patchew.org/QEMU/20200131212742.18579-1-l...@suse.com/ Hi, This series seems to have some coding style problems. See output below for more information: Subject: [PATCH] target/arm/monitor: query-cpu-model-expansion crashed qemu when using machine type none Message-id: 202

Re: [PATCH v1 23/36] target/riscv: Add hypvervisor trap support

On Mon, Jan 20, 2020 at 12:34 AM Jiangyifei wrote: > > Hi Alistair, > > When I boot a riscv OS (the host) on the QEMU emulator and then boot a > guest riscv OS in the host. The guest riscv OS fails to boot. > > The riscv OS is a linux kernel in the riscv_kvm_v10 branch, the qemu emulator > is the

[PATCH] target/arm/monitor: query-cpu-model-expansion crashed qemu when using machine type none

>From commit e19afd56, we know target-arm restricts the list of queryable cpu models to 'max', 'host', and the current type when KVM is in use. The logic works well until using machine type none. For machine type none, cpu_type will be null, and strlen(cpu_type) will terminate process. So I add a

[Bug 1861404] Re: AVX instruction VMOVDQU implementation error for YMM registers

Because the sse code is sloppy, and it was interpreted as the sse instruction movdqu. AVX support was coded for GSoC last year, https://lists.nongnu.org/archive/html/qemu-devel/2019-08/msg05369.html but it has not been completely reviewed and committed. There is no support for AVX in master. -

[PATCH 1/2] tests/acceptance: Extract boot_integratorcp() from test_integratorcp()

As we want to re-use this code, extract it as a new function. Since we are using the PL011 serial console, add a Avocado tag to ease filtering of tests. Signed-off-by: Philippe Mathieu-Daudé --- tests/acceptance/machine_arm_integratorcp.py | 16 ++-- 1 file changed, 10 insertions(+),

[PATCH 0/2] tests/acceptance/integratorcp: Verify Tux is displayed on framebuffer

Hi, This is a simple Avocado test that use OpenCV to find the Tux logo on the framebuffer screen dump. It is very fast, around 4 seconds on my laptop. Tux found by OpenCV: https://pasteboard.co/ISz7kr8.png Regards, Phil. Based-on: <20200131170233.14584-1-th...@redhat.com> "tests/acceptance: A

[PATCH 2/2] tests/acceptance/integratorcp: Verify Tux is displayed on framebuffer

Add a test that verifies the Tux logo is displayed on the framebuffer. We simply follow the OpenCV "Template Matching with Multiple Objects" tutorial, replacing Lionel Messi by Tux: https://docs.opencv.org/4.2.0/d4/dc6/tutorial_py_template_matching.html When OpenCV and NumPy are installed, this t

[Bug 1823790] Re: QEMU mishandling of SO_PEERSEC forces systemd into tight loop

Could you test the attached patch? ** Patch added: "Implement SO_PEERSEC" https://bugs.launchpad.net/qemu/+bug/1823790/+attachment/5324494/+files/0001-linux-user-implement-TARGET_SO_PEERSEC.patch -- You received this bug notification because you are a member of qemu- devel-ml, which is subsc

Re: [RFC PATCH v1 5/8] vfio-ccw: Add support for the schib region

[Had two un-addressed QEMU comments on my todo list; let's do that now.] On 11/20/19 6:13 AM, Cornelia Huck wrote: > On Fri, 15 Nov 2019 04:34:34 +0100 > Eric Farman wrote: > >> From: Farhan Ali >> >> The schib region can be used to obtain the latest SCHIB from the host >> passthrough subchanne

Re: [PATCH v5 30/41] target/arm: Flush tlb for ASID changes in EL2&0 translation regime

On 1/31/20 5:11 AM, Peter Maydell wrote: >> { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, >>.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, >> - .access = PL2_RW, >> - /* no .writefn needed as this can't cause an ASID change; >> - * no .raw_writefn or .resetfn n

Re: [PATCH v5 02/41] target/arm: Enable HCR_E2H for VHE

On 1/31/20 5:06 AM, Peter Maydell wrote: > On Wed, 29 Jan 2020 at 23:56, Richard Henderson > wrote: >> >> Reviewed-by: Alex Bennée >> Signed-off-by: Richard Henderson >> --- >> target/arm/cpu.h| 7 --- >> target/arm/helper.c | 6 +- >> 2 files changed, 5 insertions(+), 8 deletions(-

Re: [PATCH rc4 01/29] target/avr: Add basic parameters for new AVR platform

On Friday, January 31, 2020, Aleksandar Markovic < aleksandar.marko...@rt-rk.com> wrote: > From: Michael Rolnik > > This includes definitions of various basic parameters needed > for integration of a new platform into QEMU. > > Hi, all. Just to keep everyone in the loop: I'll try to put togethe

[Bug 1860610] Re: cap_disas_plugin leaks memory

I run git blame in the capstone repository, and cs_free has been around for at least 4 years in the capstone ABI. I can not tell if the need to call cs_free is a (new) requirement. Documentation capstone is a little informal... -- You received this bug notification because you are a member of qem

Re: [PATCH] block/backup-top: fix flags handling

On 1/31/20 12:48 PM, Vladimir Sementsov-Ogievskiy wrote: backup-top "supports" write-unchanged, by skipping CBW operation in backup_top_co_pwritev. But it forgets to do the same in backup_top_co_pwrite_zeroes, as well as declare support for BDRV_REQ_WRITE_UNCHANGED. Fix this, and, while being he

Re: [PATCH v2 2/5] migretion/block-dirty-bitmap: refactor init_dirty_bitmap_migration

On 12/19/19 2:51 AM, Vladimir Sementsov-Ogievskiy wrote: In the subject: s/migretion/migration/ Split out handling one bs, it is needed for the following commit, which will handle BlockBackends in separate. s/in separate/separately/ Signed-off-by: Vladimir Sementsov-Ogievskiy --- migrat

Re: [PATCH v2 1/5] block: Mark commit and mirror as filter drivers

On 12/19/19 2:51 AM, Vladimir Sementsov-Ogievskiy wrote: From: Max Reitz The commit and mirror block nodes are filters, so they should be marked as such. Signed-off-by: Max Reitz Signed-off-by: Vladimir Sementsov-Ogievskiy [squash comment fix from another Max's patch and adjust commit ms

Re: [PATCH rc4 01/29] target/avr: Add basic parameters for new AVR platform

On Friday, January 31, 2020, Aleksandar Markovic < aleksandar.marko...@rt-rk.com> wrote: > From: Michael Rolnik > > This includes definitions of various basic parameters needed > for integration of a new platform into QEMU. > > [AM: Split a larger AVR introduction patch into logical units] > Sugg

Re: [PULL 0/5] Tracing patches

On Thu, 30 Jan 2020 at 21:38, Stefan Hajnoczi wrote: > > The following changes since commit 928173659d6e5dc368284f73f90ea1d129e1f57d: > > Merge remote-tracking branch > 'remotes/pmaydell/tags/pull-target-arm-20200130' into staging (2020-01-30 > 16:19:04 +) > > are available in the Git repo

[PATCH] block/backup-top: fix flags handling

backup-top "supports" write-unchanged, by skipping CBW operation in backup_top_co_pwritev. But it forgets to do the same in backup_top_co_pwrite_zeroes, as well as declare support for BDRV_REQ_WRITE_UNCHANGED. Fix this, and, while being here, declare also support for flags supported by source chil

Re: [PATCH rc4 01/29] target/avr: Add basic parameters for new AVR platform

On Friday, January 31, 2020, Aleksandar Markovic < aleksandar.marko...@rt-rk.com> wrote: > From: Michael Rolnik > > This includes definitions of various basic parameters needed > for integration of a new platform into QEMU. > > [AM: Split a larger AVR introduction patch into logical units] > Sugg

Re: [PATCH] tests/acceptance: Add a test for the integratorcp arm machine

On 1/31/20 3:02 PM, Thomas Huth wrote: There is a kernel and initrd available on github which we can use for testing this machine. Signed-off-by: Thomas Huth --- MAINTAINERS | 1 + tests/acceptance/machine_arm_integratorcp.py | 43 2

Re: [PATCH v11 2/2] docs: qcow2: introduce compression type feature

31.01.2020 20:49, Eric Blake wrote: On 1/31/20 11:34 AM, Alberto Garcia wrote: On Fri 31 Jan 2020 03:46:12 PM CET, Eric Blake wrote: +    If the incompatible bit "Compression type" is set: the field +    must be present and non-zero (which means non-zlib +  

Re: [PATCH 1/6] tests/boot_linux_console: add microvm acceptance test

On 1/30/20 9:51 PM, Philippe Mathieu-Daudé wrote: On 1/30/20 6:41 PM, Wainer dos Santos Moschetta wrote: On 1/27/20 2:36 PM, Liam Merwick wrote: Refactor test_x86_64_pc() to test_x86_64_machine() so that separate functions which specify the Avocado tag of ':avocado: tags=machine:' as being ei

Re: [PATCH 10/17] block: Add new BDRV_ZERO_OPEN flag

On 1/31/20 11:44 AM, Eric Blake wrote: Knowing that a file reads as all zeroes when created is useful, but limited in scope to drivers that can create images. However, there are also situations where pre-existing images can quickly be determined to read as all zeroes, even when the image was not

Re: [PATCH v11 2/2] docs: qcow2: introduce compression type feature

On 1/31/20 11:34 AM, Alberto Garcia wrote: On Fri 31 Jan 2020 03:46:12 PM CET, Eric Blake wrote: +If the incompatible bit "Compression type" is set: the field +must be present and non-zero (which means non-zlib +compression type). Othe

[PATCH 17/17] qcow2: Let qemu-img check cover all-zero bit

Since checking an images refcounts already visits every cluster, it's basically free to also check that the all-zero bit is correctly set. Only check for the active L1 table, and only output an error on the first non-zero cluster found. Signed-off-by: Eric Blake --- block/qcow2-refcount.c |

[PATCH 13/17] qcow2: Add new autoclear feature for all zero image

With the recent introduction of BDRV_ZERO_OPEN, we can optimize various qemu-img operations if we know the destination starts life with all zero content. For an image with no cluster allocations and no backing file, this was already trivial with BDRV_ZERO_CREATE; but for a fully preallocated image

[PATCH 12/17] gluster: Support BDRV_ZERO_OPEN

Since gluster already copies file-posix for lseek usage in block status, it also makes sense to copy it for learning if the image currently reads as all zeroes. Signed-off-by: Eric Blake --- block/gluster.c | 20 1 file changed, 20 insertions(+) diff --git a/block/gluster.c

[PATCH 09/17] block: Refactor bdrv_has_zero_init{,_truncate}

Having two slightly-different function names for related purposes is unwieldy, especially since I envision adding yet another notion of zero support in an upcoming patch. It doesn't help that bdrv_has_zero_init() is a misleading name (I originally thought that a driver could only return 1 when ope

[PATCH 15/17] qcow2: Implement all-zero autoclear bit

Wire up the autoclear bit just defined in the previous patch. When we create an image or clear it with .bdrv_make_empty, we know that it reads as all zeroes. Reading an image does not change the previous status, nor does writing zeroes, trimming (because we specifically set trimmed clusters to rea

[PATCH 14/17] qcow2: Expose all zero bit through .bdrv_known_zeroes

Now that qcow2 images have a way to track when the contents are known to be all zero, it is worth exposing this to clients such as qemu-img convert. (Of course, until the next patch wires up qcow2 to actually set the bit, this patch has no immediate effect; however, keeping it as a separate patch

[PATCH 03/17] qcow2: Avoid feature name extension on small cluster size

As the feature name table can be quite large (over 9k if all 64 bits of all three feature fields have names; a mere 8 features leaves only 8 bytes for a backing file name in a 512-byte cluster), it is unwise to emit this optional header in images with small cluster sizes. Update iotest 036 to skip

[PATCH 06/17] block: Improve bdrv_has_zero_init_truncate with backing file

When we added bdrv_has_zero_init_truncate(), we chose to blindly return 0 if a backing file was present, because we knew of the corner case where a backing layer larger than the current layer might leak the tail of the backing layer into the resized region. But as this setup is rare, it penalizes

[PATCH 11/17] file-posix: Support BDRV_ZERO_OPEN

A single lseek(SEEK_DATA) is sufficient to tell us if a raw file is completely sparse, in which case it reads as all zeroes. Not done here, but possible extension for the future: when working with block devices instead of files, there may be various ways with ioctl or similar to quickly probe if a

[PATCH 16/17] iotests: Add new test for qcow2 all-zero bit

Cover various scenarios to show that the bit gets set even for fully-allocated images, as well as scenarios where it is properly cleared. Signed-off-by: Eric Blake --- tests/qemu-iotests/285 | 107 +++ tests/qemu-iotests/285.out | 257 + tests/

[PATCH 10/17] block: Add new BDRV_ZERO_OPEN flag

Knowing that a file reads as all zeroes when created is useful, but limited in scope to drivers that can create images. However, there are also situations where pre-existing images can quickly be determined to read as all zeroes, even when the image was not just created by the same process. The o

[PATCH 00/17] Improve qcow2 all-zero detection

Based-on: <20200124103458.1525982-2-david.edmond...@oracle.com> ([PATCH v2 1/2] qemu-img: Add --target-is-zero to convert) I'm working on adding an NBD extension that reports whether an image is already all zero when the client first connects. I initially thought I could write the NBD code to jus

[PATCH 02/17] qcow2: List autoclear bit names in header

The feature table is supposed to advertise the name of all feature bits that we support; however, we forgot to update the table for autoclear bits. While at it, move the table to read-only memory in code, and tweak the qcow2 spec to name the second autoclear bit. Update iotests that are affected b

[PATCH 07/17] gluster: Drop useless has_zero_init callback

block.c already defaults to 0 if we don't provide a callback; there's no need to write a callback that always fails. Signed-off-by: Eric Blake --- block/gluster.c | 14 -- 1 file changed, 14 deletions(-) diff --git a/block/gluster.c b/block/gluster.c index 4fa4a77a4777..9d952c70981b

[PATCH 01/17] qcow2: Comment typo fixes

Various trivial typos noticed while working on this file. Signed-off-by: Eric Blake --- block/qcow2.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/block/qcow2.c b/block/qcow2.c index cef9d72b3a16..30fd3d13032a 100644 --- a/block/qcow2.c +++ b/block/qcow2.c @@ -174,7

[PATCH 08/17] sheepdog: Consistently set bdrv_has_zero_init_truncate

block_int.h claims that .bdrv_has_zero_init must return 0 if .bdrv_has_zero_init_truncate does likewise; but this is violated if only the former callback is provided if .bdrv_co_truncate also exists. When adding the latter callback, it was mistakenly added to only one of the three possible sheepdog

[PATCH 04/17] block: Improve documentation of .bdrv_has_zero_init

Several drivers supply .bdrv_has_zero_init that returns 1, but lack the .bdrv_has_zero_init_truncate callback (parallels and qed outright, vdi in some scenarios). A literal reading of the existing documentation says such drivers are broken, because bdrv_has_zero_init_truncate() defaults to zero if

[PATCH 05/17] block: Don't advertise zero_init_truncate with encryption

Commit 38841dcd correctly argued that having qcow2 blindly return 1 for .bdrv_has_zero_init() is wrong for preallocated images built on block devices, while .bdrv_has_zero_init_truncate() can still return 1 because it is only relied on when changing size with PREALLOC_MODE_OFF (and this is true eve

Re: [PATCH v1 15/36] target/riscv: Convert mstatus to pointers

On Thu, Jan 30, 2020 at 6:48 AM Palmer Dabbelt wrote: > > On Tue, 21 Jan 2020 11:02:01 GMT (+), alistai...@gmail.com wrote: > > On Wed, Jan 8, 2020 at 11:30 AM Palmer Dabbelt > > wrote: > >> > >> On Mon, 09 Dec 2019 10:11:19 PST (-0800), Alistair Francis wrote: > >> > To handle the new Hyper

Re: [Bug 1861404] [NEW] AVX instruction VMOVDQU implementation error for YMM registers

On Friday, January 31, 2020, Alex Bennée wrote: > ** Tags added: tcg testcase > > -- > You received this bug notification because you are a member of qemu- > devel-ml, which is subscribed to QEMU. > https://bugs.launchpad.net/bugs/1861404 > > Title: > AVX instruction VMOVDQU implementation erro

Re: [PATCH] target/arm: fix TCG leak for fcvt half->double

On Fri, 31 Jan 2020 at 16:50, Philippe Mathieu-Daudé wrote: > > On 1/31/20 4:34 PM, Alex Bennée wrote: > > When support for the AHP flag was added we inexplicably only freed the > > new temps in one of the two legs. Move those tcg_temp_free to the same > > level as the allocation to fix that leak.

Re: [PATCH v11 2/2] docs: qcow2: introduce compression type feature

On Fri 31 Jan 2020 03:46:12 PM CET, Eric Blake wrote: >> +If the incompatible bit "Compression type" is set: the >> field >> +must be present and non-zero (which means non-zlib >> +compression type). Otherwise, this field must not be >>

Re: [PATCH] tests/acceptance: Add a test for the integratorcp arm machine

On 1/31/20 6:02 PM, Thomas Huth wrote: There is a kernel and initrd available on github which we can use for testing this machine. Signed-off-by: Thomas Huth --- MAINTAINERS | 1 + tests/acceptance/machine_arm_integratorcp.py | 43 2 fi

[Bug 1860610] Re: cap_disas_plugin leaks memory

It looks like this will fail on all the other capstone cases as well. Is this an API change across versions? ** Tags added: plugin tcg ** Changed in: qemu Assignee: (unassigned) => Alex Bennée (ajbennee) -- You received this bug notification because you are a member of qemu- devel-ml, whic

Re: Improving QOM documentation [Was: Re: Making QEMU easier for management tools and applications]

Kashyap Chamarthy writes: > On Fri, Jan 31, 2020 at 12:02:05PM +0100, Paolo Bonzini wrote: >> Il ven 31 gen 2020, 11:36 Peter Maydell ha >> scritto: > > [...] > >> The advantage of putting them in the header is that you have them all in >> one place (inline functions and structs must be in the h

Re: [GSoC/Outreachy QEMU proposal] Extend support for ioctls in QEMU linux-user mode

On Thu, Jan 30, 2020 at 12:09:58PM +0100, Aleksandar Markovic wrote: > Stefan, there was an idea in this thread that this project contributes > (apart to QEMU) to another ooen source project (LTP). In my layman view, > this is an advantage. But, how does that fit into GSoC/Outreachy rules? That is

[Bug 1861404] Re: AVX instruction VMOVDQU implementation error for YMM registers

** Tags added: tcg testcase -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1861404 Title: AVX instruction VMOVDQU implementation error for YMM registers Status in QEMU: New Bug description: Hi

Re: [PATCH v11 1/2] docs: improve qcow2 spec about extending image header

On Fri 31 Jan 2020 03:22:18 PM CET, Vladimir Sementsov-Ogievskiy wrote: > Make it more obvious how to add new fields to the version 3 header and > how to interpret them. > > The specification is adjusted so that for new defined optional fields: > > 1. Software may support some of these optional fie

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