On 10/8/19 1:17 PM, Peter Maydell wrote:
> Switch the musicpal code away from bottom-half based ptimers to
> the new transaction-based ptimer API. This just requires adding
> begin/commit calls around the various places that modify the ptimer
> state, and using the new ptimer_init() function to cr
On 10/8/19 1:17 PM, Peter Maydell wrote:
> Switch the arm_timer.c code away from bottom-half based ptimers
> to the new transaction-based ptimer API. This just requires
> adding begin/commit calls around the various arms of
> arm_timer_write() that modify the ptimer state, and using the
> new ptime
On 10/8/19 1:17 PM, Peter Maydell wrote:
> Convert the ptimer test cases to the transaction-based ptimer API,
> by changing to ptimer_init(), dropping the now-unused QEMUBH
> variables, and surrounding each set of changes to the ptimer
> state in ptimer_transaction_begin/commit calls.
>
> Signed-o
On 10/8/19 1:17 PM, Peter Maydell wrote:
> Provide the new transaction-based API. If a ptimer is created
> using ptimer_init() rather than ptimer_init_with_bh(), then
> instead of providing a QEMUBH, it provides a pointer to the
> callback function directly, and has opted into the transaction
> API
On Tue, Oct 08, 2019 at 08:15:51PM +0100, Dr. David Alan Gilbert wrote:
>* Wei Yang (richardw.y...@linux.intel.com) wrote:
>> After previous cleanup, postcopy thread is running only when
>> PostcopyState is LISTENNING or RUNNING. This means it is not necessary
>> to spare a variable have_listen_thr
On 10/8/19 6:04 PM, Alistair Francis wrote:
> Instead of relying on atomics to access the MIP register let's update
> our helper function to instead just lock the IO mutex thread before
> writing. This follows the same concept as used in PPC for handling
> interrupts
>
> Signed-off-by: Alistair Fr
On Tue, Oct 08, 2019 at 10:00:57AM +0100, Alex Bennée wrote:
>
> Philippe Mathieu-Daudé writes:
>
> > Various logging improvements as once:
> > - Use 0x prefix for hex numbers
>
> You can use "%#"PRIxNN"" as an alternative I believe but anyway:
>
Unless the value given to the formatting string
On Tue, Oct 08, 2019 at 07:33:17AM -0400, Igor Mammedov wrote:
> rs6000mc_realize() violates memory_region_allocate_system_memory() contract
> by calling it multiple times which could break -mem-path. Replace it with
> plain memory_region_init_ram() instead.
>
> Signed-off-by: Igor Mammedov
Acke
On Tue, Oct 08, 2019 at 06:38:25PM +0100, Dr. David Alan Gilbert wrote:
>* Wei Yang (richardw.y...@linux.intel.com) wrote:
>> The only possible bit set in invalid_flags is
>> RAM_SAVE_FLAG_COMPRESS_PAGE at the beginning of function
>> ram_load_precopy(), which means it is not necessary to do
>> ano
On Tue, Oct 08, 2019 at 06:24:23PM +0100, Dr. David Alan Gilbert wrote:
>* Wei Yang (richardw.y...@linux.intel.com) wrote:
>> postcopy_ram_incoming_setup() and postcopy_ram_incoming_cleanup() are
>> counterpart. It is reasonable to map/unmap large zero page in these two
>> functions respectively.
>
Philippe Mathieu-Daudé 于2019年10月8日周二 下午10:32写道：
> The PIIX3/IDE is a PCI device within the PIIX3 chipset, it will be reset
> when the PCI bus it stands on is reset.
>
> Convert its reset handler into a proper Device reset method.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/ide/piix.c |
Ping for comments :)
On 9/29/2019 9:57 AM, Xu, Tao3 wrote:
UMONITOR, UMWAIT and TPAUSE are a set of user wait instructions.
UMONITOR arms address monitoring hardware using an address. A store
to an address within the specified address range triggers the
monitoring hardware to wake up the proces
Philippe Mathieu-Daudé 于2019年10月8日周二 下午10:49写道：
> The PIIX4/ISA is a PCI device within the PIIX4 chipset, it will be reset
> when the PCI bus it stands on is reset.
>
> Convert its reset handler into a proper Device reset method.
>
> Signed-off-by: Philippe Mathieu-Daudé
>
Reviewed-by: Li Qiang
On Tue, Oct 08, 2019 at 05:40:46PM +0100, Dr. David Alan Gilbert wrote:
>* Wei Yang (richardw.y...@linux.intel.com) wrote:
>> Currently, we set PostcopyState blindly to RUNNING, even we found the
>> previous state is not LISTENING. This will lead to a corner case.
>>
>> First let's look at the cod
Philippe Mathieu-Daudé 于2019年10月8日周二 下午10:28写道：
> The PIIX4/PM is a PCI device within the PIIX4 chipset, it will be reset
> when the PCI bus it stands on is reset.
>
> Convert its reset handler into a proper Device reset method.
>
> Reviewed-by: Igor Mammedov
> Signed-off-by: Philippe Mathieu-Da
On Tue, Oct 08, 2019 at 05:02:02PM +0100, Dr. David Alan Gilbert wrote:
>* Wei Yang (richardw.y...@linux.intel.com) wrote:
>> postcopy_ram_incoming_cleanup() does cleanup for
>> postcopy_ram_incoming_setup(), while the setup happens only after
>> migration enters LISTEN state.
>>
>> This means the
Laszlo Ersek 于2019年10月9日周三 上午4:27写道：
> On 10/08/19 17:04, Li Qiang wrote:
> > Philippe Mathieu-Daudé 于2019年10月7日周一 下午11:20写道：
> >
> >> We have been restricting our fw_cfg tests to the PC machine,
> >> which is a little-endian architecture.
> >> The fw_cfg device is also used on the SPARC and Pow
On Thu, Sep 26, 2019 at 07:34:09PM +0200, Philippe Mathieu-Daudé wrote:
> IEC binary prefixes ease code review: the unit is explicit.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/arm/raspi.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/arm/raspi.c b/hw
If the user supplied pflash to QEMU then change the reset code to jump
to the pflash base address instead of the DRAM base address.
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Bin Meng
---
hw/riscv/virt.c | 11 ++-
1 file change
Add the CFI01 PFlash to the RISC-V virt board. This is the same PFlash
from the ARM Virt board and the implementation is based on the ARM Virt
board. This allows users to specify flash files from the command line.
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
hw
Instead of using the DEFINE_MACHINE() macro to define the machine let's
do it manually. This allows us to specify machine properties.
This patch is no functional change.
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
hw/riscv/sifive_u.c | 44
The HiFive Unleashed uses is25wp256 SPI NOR flash. There is currently no
model of this in QEMU, so to allow boot firmware developers to use QEMU
to target the Unleashed let's add a chunk of memory to represent the QSPI0
memory mapped flash. This can be targeted using QEMU's -device loader
command l
Add a property that when set to true QEMU will jump from the ROM code to
the start of flash memory instead of DRAM which is the default
behaviour.
Signed-off-by: Alistair Francis
---
v3:
- Use the start_addr variable instead of editing reset vector
- Fix function names
hw/riscv/sifive_u.c
On reset only a single L2 cache way is enabled, the others are exposed
as memory that can be used by early boot firmware. This L2 region is
generally disabled using the WayEnable register at a later stage in the
boot process. To allow firmware to target QEMU and the HiFive Unleashed
let's add the L
Instead of using the DEFINE_MACHINE() macro to define the machine let's
do it manually. This allows us to use the machine object to create
RISCVVirtState. This is required to add children and aliases to the
machine.
This patch is no functional change.
Signed-off-by: Alistair Francis
Reviewed-by:
This series aims to improve the use of QEMU for developing boot code. It
does a few things:
- sifive_u machine:
- Adds a chunk of memory in the Flash area. This allows boot loaders
to use this memory. I can't find details on the QSPI flash used on
the real board, so this is the best be
On Sat, Oct 05, 2019 at 05:47:48PM +0200, Philippe Mathieu-Daudé wrote:
> This test boots a Linux kernel on a smdkc210 board and verify
> the serial output is working.
>
> The cpio image used comes from the linux-build-test project:
> https://github.com/groeck/linux-build-test
>
> Since this test
On Tue, Oct 08, 2019 at 05:49:07PM -0400, Cleber Rosa wrote:
> On Mon, Oct 07, 2019 at 05:28:49PM +0100, Peter Maydell wrote:
> > On Sat, 5 Oct 2019 at 16:47, Philippe Mathieu-Daudé wrote:
> > >
> > > This test boots a Linux kernel on a smdkc210 board and verify
> > > the serial output is working.
On 10/08/19 23:58, Laszlo Ersek wrote:
> On 10/07/19 19:55, Philippe Mathieu-Daudé wrote:
>> On 10/7/19 7:35 PM, John Snow wrote:
>>> On 10/7/19 8:33 AM, Peter Maydell wrote:
On Thu, 3 Oct 2019 at 20:33, John Snow wrote:
>
> The following changes since commit
> 7f21573c822805a8e6b
Instead of relying on atomics to access the MIP register let's update
our helper function to instead just lock the IO mutex thread before
writing. This follows the same concept as used in PPC for handling
interrupts
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c| 5 ++--
target/
On 10/07/19 19:55, Philippe Mathieu-Daudé wrote:
> On 10/7/19 7:35 PM, John Snow wrote:
>> On 10/7/19 8:33 AM, Peter Maydell wrote:
>>> On Thu, 3 Oct 2019 at 20:33, John Snow wrote:
The following changes since commit
7f21573c822805a8e6be379d9bcf3ad9effef3dc:
Merge remot
On Sat, Oct 05, 2019 at 05:47:45PM +0200, Philippe Mathieu-Daudé wrote:
> This file keeps the various QDev blocks separated by comments.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/sd/sdhci.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/hw/sd/sdhci.c b/hw/
On Mon, Oct 07, 2019 at 05:28:49PM +0100, Peter Maydell wrote:
> On Sat, 5 Oct 2019 at 16:47, Philippe Mathieu-Daudé wrote:
> >
> > This test boots a Linux kernel on a smdkc210 board and verify
> > the serial output is working.
> >
> > The cpio image used comes from the linux-build-test project:
>
On Sat, Oct 05, 2019 at 05:47:44PM +0200, Philippe Mathieu-Daudé wrote:
> This test boots a Linux kernel on a smdkc210 board and verify
> the serial output is working.
>
> The cpio image used comes from the linux-build-test project:
> https://github.com/groeck/linux-build-test
>
> If ARM is a tar
On Tue, 08 Oct 2019 13:51:46 PDT (-0700), Alistair Francis wrote:
The do_unassigned_access hook has been deprecated and RISC-V is the last
user of it. Let's instead update the RISC-V implementation to use
do_transaction_failed instead.
After this series I used the 'git grep' regexes in
docs/dev
From: Palmer Dabbelt
This converts our port over from cpu_do_unassigned_access to
cpu_do_transaction_failed, as cpu_do_unassigned_access has been
deprecated.
Signed-off-by: Palmer Dabbelt
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
The do_unassigned_access hook has been deprecated and RISC-V is the last
user of it. Let's instead update the RISC-V implementation to use
do_transaction_failed instead.
After this series I used the 'git grep' regexes in
docs/devel/loads-stores.rst and these are the memory accesses inside
target
On Tue, Oct 8, 2019 at 1:41 PM Alistair Francis wrote:
>
> On Tue, Oct 8, 2019 at 1:41 PM Palmer Dabbelt wrote:
> >
> > On Fri, 20 Sep 2019 07:20:34 PDT (-0700), Peter Maydell wrote:
> > > On Fri, 20 Sep 2019 at 15:17, Paolo Bonzini wrote:
> > >> I think it's simplest if all series (RISC-V, remo
From: Palmer Dabbelt
We directly access physical memory while walking the page tables on
RISC-V, but while doing so we were using cpu_ld*() which does not report
bus errors. This patch converts the page table walker over to use
address_space_ld*(), which allows bus errors to be detected.
Signed
On Tue, Oct 8, 2019 at 1:41 PM Palmer Dabbelt wrote:
>
> On Fri, 20 Sep 2019 07:20:34 PDT (-0700), Peter Maydell wrote:
> > On Fri, 20 Sep 2019 at 15:17, Paolo Bonzini wrote:
> >> I think it's simplest if all series (RISC-V, remove unassigned_access,
> >> this one) go through the RISC-V tree.
> >
On Fri, 20 Sep 2019 07:20:34 PDT (-0700), Peter Maydell wrote:
On Fri, 20 Sep 2019 at 15:17, Paolo Bonzini wrote:
I think it's simplest if all series (RISC-V, remove unassigned_access,
this one) go through the RISC-V tree.
I don't inherently object but IME the risc-v tree tends to move
compar
On Tue, Oct 8, 2019 at 1:12 PM Palmer Dabbelt wrote:
>
> On Mon, 30 Sep 2019 11:04:45 PDT (-0700), alistai...@gmail.com wrote:
> > On Fri, Sep 27, 2019 at 12:57 AM Bin Meng wrote:
> >>
> >> On Fri, Sep 27, 2019 at 8:55 AM Alistair Francis
> >> wrote:
> >> >
> >> > Add a property that when set to
On Tue, 8 Oct 2019 at 21:29, Laszlo Ersek wrote:
> In that case, the original initializer will remain in effect, from:
>
> QTestCtx ctx = {};
>
> (Admittedly, this is an ugly GNU-ism; for standard C, it should be
>
> QTestCtx ctx = { 0 };
>
> but the GNU-ism is used quite frequently in QEMU el
On 10/08/19 17:04, Li Qiang wrote:
> Philippe Mathieu-Daudé 于2019年10月7日周一 下午11:20写道：
>
>> We have been restricting our fw_cfg tests to the PC machine,
>> which is a little-endian architecture.
>> The fw_cfg device is also used on the SPARC and PowerPC
>> architectures, which can run in big-endian
On Fri, 20 Sep 2019 02:19:02 PDT (-0700), bmeng...@gmail.com wrote:
U-Boot expects this alias to be in place in order to fix up the mac
address of the ethernet node.
This is to keep in sync with Linux kernel commit below:
https://patchwork.kernel.org/patch/11133033/
Signed-off-by: Bin Meng
---
On Mon, 30 Sep 2019 11:04:45 PDT (-0700), alistai...@gmail.com wrote:
On Fri, Sep 27, 2019 at 12:57 AM Bin Meng wrote:
On Fri, Sep 27, 2019 at 8:55 AM Alistair Francis
wrote:
>
> Add a property that when set to true QEMU will jump from the ROM code to
> the start of flash memory instead of DR
On Thu, 26 Sep 2019 17:44:28 PDT (-0700), Alistair Francis wrote:
Add a property that when set to true QEMU will jump from the ROM code to
the start of flash memory instead of DRAM which is the default
behaviour.
Signed-off-by: Alistair Francis
---
hw/riscv/sifive_u.c | 27
On 10/7/19 11:28 AM, Alex Bennée wrote:
> diff --git a/accel/tcg/perf/jitdump.c b/accel/tcg/perf/jitdump.c
> index e1d6f2214e..e7b86173e0 100644
> --- a/accel/tcg/perf/jitdump.c
> +++ b/accel/tcg/perf/jitdump.c
> @@ -146,7 +146,20 @@ void start_jitdump_file(void)
>
> void append_load_in_jitdump_
On 10/7/19 11:28 AM, Alex Bennée wrote:
> Signed-off-by: Alex Bennée
> ---
> configure | 5 -
> 1 file changed, 5 deletions(-)
Merge this with the patch that removes CONFIG_PROFILER.
r~
Richard Henderson writes:
> On 10/7/19 11:28 AM, Alex Bennée wrote:
>> From: "Vanderson M. do Rosario"
>>
>> These commands allow the exploration of TBs generated by the TCG.
>> Understand which one hotter, with more guest/host instructions... and
>> examine their guest, host and IR code.
>>
>
On 10/7/19 11:28 AM, Alex Bennée wrote:
> +static uint32_t get_e_machine(void)
> +{
> +uint32_t e_machine = EM_NONE;
> +Elf64_Ehdr elf_header;
Not ideal, as this appears to not work on 32-bit hosts, but the two structures
do match up within the first 24 bytes, in which this is located.
Th
Richard Henderson writes:
> On 10/7/19 11:28 AM, Alex Bennée wrote:
>> We keep track of translations but can only do so up until the
>> translation cache is flushed. At that point we really have no idea if
>> we can re-create a translation because all the active tracking
>> information has been
* Wei Yang (richardw.y...@linux.intel.com) wrote:
> After previous cleanup, postcopy thread is running only when
> PostcopyState is LISTENNING or RUNNING. This means it is not necessary
> to spare a variable have_listen_thread to represent the state.
>
> Replace the check on have_listen_thread wit
On 10/7/19 11:28 AM, Alex Bennée wrote:
> @@ -337,7 +336,8 @@ int qemu_str_to_log_mask(const char *str)
> enable_collect_tb_stats();
> } else if (tb_stats_collection_enabled() &&
> g_str_has_prefix(*tmp, "dump_limit=")) {
> -max_num_hot_tbs_to_d
* Wei Yang (richardw.y...@linux.intel.com) wrote:
> There are two places to call function postcopy_ram_incoming_cleanup()
>
> postcopy_ram_listen_thread on migration success
> loadvm_postcopy_handle_listen one setup failure
>
> On success, the vm will never accept another migration. On fa
Eduardo, Igor,
On 10/08/19 12:52, Laszlo Ersek wrote:
> FW_CFG_MAX_CPUS exposes the (exclusive) maximum APIC ID to guest firmware,
> due to historical reasons. That value is not useful to edk2, however. For
> supporting VCPU hotplug, edk2 needs:
>
> - the boot CPU count (already exposed in FW_CFG
On Fri, 23 Aug 2019 16:39:03 PDT (-0700), Alistair Francis wrote:
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 5 +
target/riscv/cpu.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 06ee551ebe..39e1c130df 100644
--- a/target/r
On 10/7/19 11:28 AM, Alex Bennée wrote:
> From: "Vanderson M. do Rosario"
>
> These commands allow the exploration of TBs generated by the TCG.
> Understand which one hotter, with more guest/host instructions... and
> examine their guest, host and IR code.
>
> The goal of this command is to allo
* Wei Yang (richardw.y...@linux.intel.com) wrote:
> If mis->have_listen_thread is true, this means current PostcopyState
> must be LISTENING or RUNNING. While the check at the beginning of the
> function makes sure the state transaction happens when its previous
> PostcopyState is ADVISE or DISCARD
On Fri, 23 Aug 2019 16:38:58 PDT (-0700), Alistair Francis wrote:
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c| 6 ++
target/riscv/cpu.h| 7 +++
target/riscv/cpu_bits.h | 3 +++
target/riscv/cpu_helper.c | 7 +++
target/riscv/csr.c| 23 +++
On Fri, 23 Aug 2019 16:39:00 PDT (-0700), Alistair Francis wrote:
Add a helper macro MSTATUS_MPV_ISSET() which will determine if the
MSTATUS_MPV bit is set for both 32-bit and 64-bit RISC-V.
Signed-off-by: Alistair Francis
---
target/riscv/cpu_bits.h | 11 +++
target/riscv/cpu_helper
On 10/08/19 15:29, Philippe Mathieu-Daudé wrote:
> Hi Laszlo,
>
> On 10/8/19 12:52 PM, Laszlo Ersek wrote:
>> FW_CFG_MAX_CPUS exposes the (exclusive) maximum APIC ID to guest
>> firmware,
>> due to historical reasons. That value is not useful to edk2, however. For
>> supporting VCPU hotplug, edk2
Greg Kurz writes:
> On Tue, 08 Oct 2019 18:03:13 +0200
> Markus Armbruster wrote:
>
>> Vladimir Sementsov-Ogievskiy writes:
>>
>> > Here is introduced ERRP_AUTO_PROPAGATE macro, to be used at start of
>> > functions with errp OUT parameter.
>> >
>> > It has three goals:
>> >
>> > 1. Fix issue
On 10/08/19 15:35, Philippe Mathieu-Daudé wrote:
> On 10/8/19 12:52 PM, Laszlo Ersek wrote:
>> The enable_compat_apic_id_mode() function definition was removed earlier;
>
> "in 457cfcccdd1"
Thanks. I'll add that to the commit message if I need to post a v2.
>
>> there are no callers left. Remov
Daniel P. Berrangé writes:
> Given that we're aiming to convert to meson, how much effort do we really
> want to put into fixing this inconsistency ?
>
> I'd argue the best way to fix "clean" and "distclean" is to delete them
> entirely. Instead enforce that builddir != srcdir when running config
On 10/7/19 11:28 AM, Alex Bennée wrote:
> We keep track of translations but can only do so up until the
> translation cache is flushed. At that point we really have no idea if
> we can re-create a translation because all the active tracking
> information has been reset.
>
> Signed-off-by: Alex Ben
* Wei Yang (richardw.y...@linux.intel.com) wrote:
> Not necessary to do the check again.
>
> Signed-off-by: Wei Yang
Reviewed-by: Dr. David Alan Gilbert
> ---
> migration/migration.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/migration/migration.c b/migration/
On Fri, 23 Aug 2019 16:38:55 PDT (-0700), Alistair Francis wrote:
The qemu_log_mask(CPU_LOG_MMU,... calls trigger false positive
checkpatch errors which are being ignored.
Signed-off-by: Alistair Francis
---
target/riscv/cpu_helper.c | 94 +++
1 file changed
On Tue, 8 Oct 2019 at 15:55, Stefan Hajnoczi wrote:
>
> The following changes since commit 560009f2c8b57b7cdd31a5693ea86ab369382f49:
>
> Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging
> (2019-10-07 15:40:53 +0100)
>
> are available in the Git repository at:
>
> ht
Switch the cmsdk-apb-watchdog code away from bottom-half based
ptimers to the new transaction-based ptimer API. This just requires
adding begin/commit calls around the various places that modify the
ptimer state, and using the new ptimer_init() function to create the
timer.
Signed-off-by: Peter M
* Wei Yang (richardw.y...@linux.intel.com) wrote:
> The only possible bit set in invalid_flags is
> RAM_SAVE_FLAG_COMPRESS_PAGE at the beginning of function
> ram_load_precopy(), which means it is not necessary to do
> another check for RAM_SAVE_FLAG_COMPRESS_PAGE bit.
>
> Signed-off-by: Wei Yang
Switch the cmsdk-apb-watchdog code away from bottom-half based
ptimers to the new transaction-based ptimer API. This just requires
adding begin/commit calls around the various places that modify the
ptimer state, and using the new ptimer_init() function to create the
timer.
Signed-off-by: Peter M
* Wei Yang (richardw.y...@linux.intel.com) wrote:
> postcopy_ram_incoming_setup() and postcopy_ram_incoming_cleanup() are
> counterpart. It is reasonable to map/unmap large zero page in these two
> functions respectively.
>
> Signed-off-by: Wei Yang
Yes, OK.
> ---
> migration/postcopy-ram.c |
Switch the mss-timer code away from bottom-half based ptimers to
the new transaction-based ptimer API. This just requires adding
begin/commit calls around the various places that modify the ptimer
state, and using the new ptimer_init() function to create the timer.
Signed-off-by: Peter Maydell
-
* Wei Yang (richardw.y...@linux.intel.com) wrote:
> During migration, a tmp page is allocated so that we could place a whole
> host page during postcopy.
>
> Currently the page is allocated during load stage, this is a little bit
> late. And more important, if we failed to allocate it, the error i
Switch the ltick ptimer over to the ptimer transaction API.
Signed-off-by: Peter Maydell
---
hw/timer/exynos4210_mct.c | 31 +--
1 file changed, 25 insertions(+), 6 deletions(-)
diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
index 82803ef9a02..722
Switch the imx_epit.c code away from bottom-half based ptimers to
the new transaction-based ptimer API. This just requires adding
begin/commit calls around the various places that modify the ptimer
state, and using the new ptimer_init() function to create the timer.
Signed-off-by: Peter Maydell
Switch the exynos41210_rtc 1Hz ptimer over to the transaction-based
API. (We will switch the other ptimer used by this device in a
separate commit.)
Signed-off-by: Peter Maydell
---
hw/timer/exynos4210_rtc.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/hw/timer/
Switch the imx_epit.c code away from bottom-half based ptimers to
the new transaction-based ptimer API. This just requires adding
begin/commit calls around the various places that modify the ptimer
state, and using the new ptimer_init() function to create the timer.
Signed-off-by: Peter Maydell
Switch the exynos MCT LFRC timers over to the ptimer transaction API.
Signed-off-by: Peter Maydell
---
hw/timer/exynos4210_mct.c | 27 +++
1 file changed, 23 insertions(+), 4 deletions(-)
diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
index fcf91c75cc
Switch the exynos41210_rtc main ptimer over to the transaction-based
API, completing the transition for this device.
Signed-off-by: Peter Maydell
---
hw/timer/exynos4210_rtc.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/hw/timer/exynos4210_rtc.c b/hw/timer/ex
We want to switch the exynos MCT code away from bottom-half based ptimers to
the new transaction-based ptimer API. The MCT is complicated
and uses multiple different ptimers, so it's clearer to switch
it a piece at a time. Here we change over only the GFRC.
Signed-off-by: Peter Maydell
---
hw/ti
Switch the exynos4210_pwm code away from bottom-half based ptimers to
the new transaction-based ptimer API. This just requires adding
begin/commit calls around the various places that modify the ptimer
state, and using the new ptimer_init() function to create the timer.
Signed-off-by: Peter Mayde
Switch the digic-timer.c code away from bottom-half based ptimers to
the new transaction-based ptimer API. This just requires adding
begin/commit calls around the various places that modify the ptimer
state, and using the new ptimer_init() function to create the timer.
Signed-off-by: Peter Maydel
Switch the cmsdk-apb-dualtimer code away from bottom-half based
ptimers to the new transaction-based ptimer API. This just requires
adding begin/commit calls around the various places that modify the
ptimer state, and using the new ptimer_init() function to create the
timer.
Signed-off-by: Peter
Switch the arm_mptimer.c code away from bottom-half based ptimers to
the new transaction-based ptimer API. This just requires adding
begin/commit calls around the various places that modify the ptimer
state, and using the new ptimer_init() function to create the timer.
Signed-off-by: Peter Maydel
Switch the cmsdk-apb-timer code away from bottom-half based ptimers
to the new transaction-based ptimer API. This just requires adding
begin/commit calls around the various places that modify the ptimer
state, and using the new ptimer_init() function to create the timer.
Signed-off-by: Peter Mayd
Switch the allwinner-a10-pit code away from bottom-half based ptimers to
the new transaction-based ptimer API. This just requires adding
begin/commit calls around the various places that modify the ptimer
state, and using the new ptimer_init() function to create the timer.
Signed-off-by: Peter Ma
Currently the ptimer design uses a QEMU bottom-half as its
mechanism for calling back into the device model using the
ptimer when the timer has expired. Unfortunately this design
is fatally flawed, because it means that there is a lag
between the ptimer updating its own state and the device
callbac
Switch the arm_timer.c code away from bottom-half based ptimers
to the new transaction-based ptimer API. This just requires
adding begin/commit calls around the various arms of
arm_timer_write() that modify the ptimer state, and using the
new ptimer_init() function to create the timer.
Fixes: http
Convert the ptimer test cases to the transaction-based ptimer API,
by changing to ptimer_init(), dropping the now-unused QEMUBH
variables, and surrounding each set of changes to the ptimer
state in ptimer_transaction_begin/commit calls.
Signed-off-by: Peter Maydell
---
tests/ptimer-test.c | 106
Provide the new transaction-based API. If a ptimer is created
using ptimer_init() rather than ptimer_init_with_bh(), then
instead of providing a QEMUBH, it provides a pointer to the
callback function directly, and has opted into the transaction
API. All calls to functions which modify ptimer state:
Switch the musicpal code away from bottom-half based ptimers to
the new transaction-based ptimer API. This just requires adding
begin/commit calls around the various places that modify the ptimer
state, and using the new ptimer_init() function to create the timer.
Signed-off-by: Peter Maydell
--
Currently the ptimer design uses a QEMU bottom-half as its mechanism
for calling back into the device model using the ptimer when the
timer has expired. Unfortunately this design is fatally flawed,
because it means that there is a lag between the ptimer updating its
own state and the device callba
This is an example command line for a qemu VM with a vtnet interface
connected to a port of a VALE switch called 'vale1':
qemu-system-x86_64 fbsd-head.qcow2 -smp 2 -m 2G -vga std -device
e1000,netdev=mgmt,mac=00:AA:BB:CC:0a:99 -netdev
user,id=mgmt,hostfwd=tcp::20010-:22 -device
virtio-net-pci,netd
Il giorno mar 8 ott 2019 alle ore 11:53 Li-Wen Hsu ha
scritto:
> On Tue, Oct 8, 2019 at 5:49 PM Stefano Garzarella
> wrote:
> >
> > Hi Thomas,
> >
> > On Tue, Oct 8, 2019 at 10:49 AM Thomas Huth wrote:
> > >
> > > FreeBSD offers a package for "netmap", thus let's install it in our
> > > FreeBSD
On Mon, Oct 7, 2019 at 5:20 PM Jonathan Behrens wrote:
>
> Currently only PRV_U, PRV_S and PRV_M are supported, so this patch ensures
> that
> the privilege mode is set to one of them. Once support for the H-extension is
> added, this code will also need to properly update the virtualization stat
On Tue, Oct 8, 2019 at 2:00 AM Bin Meng wrote:
> My gdb does not list "priv" register after applying this patch.
I didn't try the patch, I didn't have time for that. I would expect
priv to be in the "info registers" output if you are adding it to the
cpu register set. Shrug. Anyways, defining
* Wei Yang (richardw.y...@linux.intel.com) wrote:
> Currently, we set PostcopyState blindly to RUNNING, even we found the
> previous state is not LISTENING. This will lead to a corner case.
>
> First let's look at the code flow:
>
> qemu_loadvm_state_main()
> ret = loadvm_process_command()
>
On Mon, Oct 7, 2019 at 5:16 PM Jonathan Behrens wrote:
>
> If the number of registers reported to the gdbstub code does not match the
> number in the associated XML file, then the register numbers used by the stub
> may get out of sync with a remote GDB instance.
>
> Signed-off-by: Jonathan Behren
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