** Description changed:
Up to date Arch Linux on host and guest. linux 5.2.11. QEMU 4.1.0.
Full command line at bottom.
Host gives QEMU two thin LVM volumes. The first is the root filesystem,
and the second is for heavy I/O, on a Samsung 970 Evo 1TB.
When maxing out the I/O on t
** Description changed:
Up to date Arch Linux on host and guest. linux 5.2.11. QEMU 4.1.0.
Full command line at bottom.
Host gives QEMU two thin LVM volumes. The first is the root filesystem,
and the second is for heavy I/O, on a Samsung 970 Evo 1TB.
When maxing out the I/O on t
Public bug reported:
Up to date Arch Linux on host and guest. linux 5.2.11. QEMU 4.1.0.
Full command line at bottom.
Host gives QEMU two thin LVM volumes. The first is the root filesystem,
and the second is for heavy I/O, on a Samsung 970 Evo 1TB.
When maxing out the I/O on the second virtual
On Wed, Sep 04, 2019 at 03:57:17PM -0400, Cleber Rosa wrote:
> On Sat, Aug 31, 2019 at 11:48:34AM +1000, David Gibson wrote:
> > On Fri, Aug 30, 2019 at 02:56:48PM -0300, Eduardo Habkost wrote:
> > > On Thu, Aug 29, 2019 at 11:31:25AM +1000, David Gibson wrote:
> > > > If I attempt to run "make che
On 9/5/2019 4:43 AM, Eduardo Habkost wrote:
On Wed, Sep 04, 2019 at 02:22:39PM +0800, Tao Xu wrote:
On 9/4/2019 1:52 AM, Eduardo Habkost wrote:
On Mon, Aug 05, 2019 at 03:13:02PM +0800, Tao Xu wrote:
Add MachineClass::auto_enable_numa field. When it is true, a NUMA node
is expected to be creat
On 9/4/19 4:29 PM, Alex Bennée wrote:
> Podman requires a little bit of additional magic to the uid mapping
> which was already done for the normal RunCommand. We simplify the
> logic by pushing it directly into the Docker::run method to avoid
> instantiating an extra Docker() object and ensure
The workaround that attempts to accomplish the same result as --userns=keep-id
does not appear to work well with UIDs much above 1000 (like mine, which is
above 2.)
Since we have official support for this "trick" now, use the supported method.
Signed-off-by: John Snow
---
tests/docker/docke
Patchew URL:
https://patchew.org/QEMU/20190904193059.26202-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190904193059.26202-1-richard.hender...@linaro.org
Type: series
Subject: [Qemu-devel] [PATCH
Now Buster is released we can stop relying on the movable feast that
is Sid for our cross-compiler for building tests.
Signed-off-by: Alex Bennée
---
tests/docker/Makefile.include | 2 +-
tests/docker/dockerfiles/debian-mips64-cross.docker | 5 ++---
2 files changed, 3 inse
On Wed, Sep 04, 2019 at 04:19:33PM +0200, Auger Eric wrote:
> Hi Michael,
>
> On 9/1/19 8:40 AM, Michael S. Tsirkin wrote:
> > On Thu, Aug 01, 2019 at 03:49:37PM +0200, Auger Eric wrote:
> >> Hi Michael,
> >>
> >> On 8/1/19 3:06 PM, Michael S. Tsirkin wrote:
> >>> On Thu, Aug 01, 2019 at 02:15:03P
From: Philippe Mathieu-Daudé
Per https://ccache.dev/manual/latest.html:
By default, ccache tries to give as few false cache hits as
possible. However, in certain situations it’s possible that
you know things that ccache can’t take for granted.
[The CCACHE_SLOPINESS environment variable]
Added a new boolean argument to blkconf_apply_backend_options()
to let the common block code know whether the chosen block
backend can handle host managed zoned block devices.
blkconf_apply_backend_options() then sets BLK_PERM_SUPPORT_HM_ZONED
permission accordingly. The raw code can then use this
Patchew URL:
https://patchew.org/QEMU/20190904203013.9028-1-alex.ben...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Subject: [Qemu-devel] [PATCH v1 00/42] current testing/next queue (podman,
docker, ci)
Message-id
The purpose of this patch is to recognize a zoned block device (ZBD)
when it is opened as a raw file. The new code initializes the zoned
model propery introduced by the previous commit.
This commit is Linux-specific as it gets the Zoned Block Device Model
value (none/host-managed/host-aware) from
Abort opening a zoned device as a raw file in case the chosen
block backend driver lacks proper support for this type of
storage.
Signed-off-by: Dmitry Fomichev
---
block/file-posix.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/block/file-posix.c b/block/file-posix.c
inde
On Wed, 2019-08-28 at 10:41 +0100, Stefan Hajnoczi wrote:
> On Fri, Aug 23, 2019 at 03:49:23PM -0400, Dmitry Fomichev wrote:
> > Dmitry Fomichev (4):
> > block: Add zoned device model property
> > raw: Recognize zoned backing devices
> > block/ide/scsi: Set BLK_PERM_SUPPORT_ZONED
> > raw: D
From: Philippe Mathieu-Daudé
These jobs build different components but use the same
host features. Put them in the same cache bucket.
Signed-off-by: Philippe Mathieu-Daudé
---
.travis.yml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/.travis.yml b/.travis.yml
index ab3e4ebaadf..ab4ee42
Now Jessie has entered LTS the powerpc architecture has been dropped
so we can no longer build the image from scratch. We will still
support a minimal powerpc-cross image for building testcases.
Signed-off-by: Alex Bennée
Cc: David Gibson
---
tests/docker/Makefile.include |
Currently, attaching zoned block devices (i.e., storage devices
compliant to ZAC/ZBC standards) using several virtio methods doesn't
work properly as zoned devices appear as regular block devices at the
guest. This may cause unexpected i/o errors and, potentially, some
data corruption.
To be more
Initial definitions for a simple machine using an AST2600 SoC (Cortex
CPU).
Differences with the AST2400 and the AST2500 SoCs are handled using
the ASPEED_IS_AST2600() macro. This is not optimal but it is not too
invasive either. We could modify the model to add custom instance_init
and realize ha
The AST2600 SoC has an extra controller to set the PHY registers.
Signed-off-by: Cédric Le Goater
---
include/hw/arm/aspeed_soc.h | 5 ++
include/hw/net/ftgmac100.h | 17
hw/arm/aspeed_soc.c | 25 ++
hw/net/ftgmac100.c | 162
4
From: Joel Stanley
The AST2600 has four watchdogs, and they each have a 0x40 of registers.
When running as part of an ast2600 system we must check a different
offset for the system reset control register in the SCU.
Signed-off-by: Joel Stanley
[clg: - reworked mode integration into new objet c
This commit adds Zoned Device Model (as defined in T10 ZBC and
T13 ZAC standards) as a block driver property, along with some
useful access functions.
A new backend driver permission, BLK_PERM_SUPPORT_HM_ZONED, is also
introduced. Only the drivers having this permission will be allowed
to open hos
From: Joel Stanley
To support the ast2600's four MACs allow SoCs to specify the number
they have, and create that many.
Signed-off-by: Joel Stanley
Signed-off-by: Cédric Le Goater
---
include/hw/arm/aspeed_soc.h | 5 -
hw/arm/aspeed_soc.c | 7 ++-
2 files changed, 10 insertion
The AST2600 timer replaces control register 2 with a interrupt status
register. It is set by hardware when an IRQ occurs and cleared by
software.
Based on previous work from Joel Stanley.
Signed-off-by: Cédric Le Goater
---
include/hw/timer/aspeed_timer.h | 1 +
hw/timer/aspeed_timer.c
From: Rashmica Gupta
The AST2600 has the same sets of 3.6v gpios as the AST2400 plus an
addtional two sets of 1.8V gpios.
Signed-off-by: Rashmica Gupta
Reviewed-by: Cédric Le Goater
Signed-off-by: Cédric Le Goater
---
hw/gpio/aspeed_gpio.c | 142 --
1
Currently this stops the mega:
make docker-test-build
from working. Once the source is patched to deal with the case this
workaround can be removed.
Signed-off-by: Alex Bennée
---
tests/docker/dockerfiles/ubuntu1804.docker | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tests/docker/d
The AST2600 timer has a third control register that is used to
implement a set-to-clear feature for the main control register.
On the AST2600, it is not configurable via 0x38 (control register 3)
as it is on the AST2500.
Based on previous work from Joel Stanley.
Signed-off-by: Cédric Le Goater
It cleanups the current models for the Aspeed AST2400 and AST2500 SoCs
and prepares ground for future SoCs.
Signed-off-by: Cédric Le Goater
---
include/hw/watchdog/wdt_aspeed.h | 18 -
hw/arm/aspeed_soc.c | 9 ++-
hw/watchdog/wdt_aspeed.c | 122 ---
This should have been marked when the docker recipe was added to
prevent it being used for cross compiling QEMU. Sort the
DEBIAN_PARTIAL_IMAGE list while we are at it.
Signed-off-by: Alex Bennée
---
tests/docker/Makefile.include | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
Hello,
The most important Aspeed models are reworked with an object class to
introduce the AST2600 variant. A model for the AST2600 SoC and a
simple AST2600 EVB machine is proposed at the end of the series. It
can boot the OpenBMC firmware image which is currently used for HW
bringup.
I would lik
From: Joel Stanley
AST2600 has extra registers. Increase the number of regs of the model
and introduce a new field in the class to customize the MemoryRegion
operations depending on the SoC model.
Signed-off-by: Joel Stanley
[clg: - improved commit log ]
- reworked mode integration into n
Now Buster is released we can stop relying on the movable feast that
is Sid for our cross-compiler for building tests.
Signed-off-by: Alex Bennée
---
tests/docker/Makefile.include | 4 ++--
tests/docker/dockerfiles/debian-ppc64-cross.docker | 7 +++
2 files changed, 5 in
Make sure the OF32S insns are enabled before allowing execution.
Include the missing bit for cpu "any".
Reviewed-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/cpu.c | 2 +-
target/openrisc/translate.c | 84 -
2 files changed,
This was added to the 1.3 spec.
Reviewed-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/disas.c | 1 +
target/openrisc/translate.c | 13 +
target/openrisc/insns.decode | 2 ++
3 files changed, 16 insertions(+)
diff --git a/target/openrisc/disas.c b/
From: Philippe Mathieu-Daudé
We are going to cache few gigabytes, increase the cache timeout
to avoid build failures when uploading our cache.
See https://docs.travis-ci.com/user/caching/#setting-the-timeout
Signed-off-by: Philippe Mathieu-Daudé
---
.travis.yml | 1 +
1 file changed, 1 insert
From: Joel Stanley
Signed-off-by: Joel Stanley
Signed-off-by: Cédric Le Goater
---
include/hw/arm/aspeed_soc.h | 1 +
hw/arm/aspeed_soc.c | 5 +
2 files changed, 6 insertions(+)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 9e06a6ad4fbd..ef5b93e5e9cf
Finish the race condition fix from the previous patch.
Reviewed-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
Reviewed-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/cpu.h| 2 ++
target/openrisc/cpu.c| 1 +
target/openrisc/fpu_helper.c | 13 +
target/openrisc/machine.c| 11 +++
target/openrisc/sys_helper.c | 18 --
5 file
The AST2600 SoC SMC controller is a SPI only controller now and has a
few extensions which we will need to take into account when SW
requires it.
- 4BYTE mode
- HCLK divider has changed (SPI Training)
- CE0-2 Read Timing Compensation registers
This is enough to support u-boot.
Signed-off-by:
From: Joel Stanley
The AST2600 SDMC controller is slightly different from its predecessor
(DRAM training). Max memory is now 2G on the AST2600.
Signed-off-by: Joel Stanley
[clg: - improved commit log ]
- reworked mode integration into new objet class ]
Signed-off-by: Cédric Le Goater
---
These registers are read-only and implementation specific.
Initiailize VR for the first time; take the OR1200 values
from the verilog source.
Note that moving fields within CPUOpenRISCState does not
affect migration.
Reviewed-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openr
On some images SHELL is pointing at a limited /bin/sh which doesn't
understand noprofile/norc. Given the run script is running bash just
invoke it directly.
Signed-off-by: Alex Bennée
---
tests/docker/run | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tests/docker/run b/
Use class handlers and class constants to differentiate the
characteristics of the memory controller and remove the 'silicon_rev'
property.
Signed-off-by: Cédric Le Goater
---
include/hw/misc/aspeed_sdmc.h | 19 +++-
hw/arm/aspeed_soc.c | 5 +-
hw/misc/aspeed_sdmc.c | 168 ++
We will need this context in the next patch.
Reviewed-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 96 +++--
1 file changed, 49 insertions(+), 47 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/tra
The AST2500 timer has a third control register that is used to
implement a set-to-clear feature for the main control register.
This models the behaviour expected by the AST2500 while maintaining
the same behaviour for the AST2400.
Based on previous work from Joel Stanley.
Signed-off-by: Cédric L
It prepares ground for register differences between SoCs.
Signed-off-by: Cédric Le Goater
---
include/hw/timer/aspeed_timer.h | 15 +
hw/arm/aspeed_soc.c | 3 +-
hw/timer/aspeed_timer.c | 107
3 files changed, 113 insertions(+), 12 dele
When building on a non-x86 host we need to setup the x86 build like
any other cross compiler.
Signed-off-by: Alex Bennée
---
tests/docker/Makefile.include | 6 +
.../dockerfiles/debian-amd64-cross.docker | 22 +++
2 files changed, 28 insertions(+)
create
These were added to the 1.3 spec. For OF32S, validate AVR.
But OF64A32 is itself new to 1.3 so no extra check needed.
Reviewed-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/helper.h | 4 ++
target/openrisc/disas.c | 24 ++
target/openrisc/fpu_helper.
From: Philippe Mathieu-Daudé
These jobs build different components but use the same
host features. Put them in the same cache bucket.
Signed-off-by: Philippe Mathieu-Daudé
---
.travis.yml | 13 +
1 file changed, 13 insertions(+)
diff --git a/.travis.yml b/.travis.yml
index ab4ee42
This prevents us trying to do builds which we can't complete.
Signed-off-by: Alex Bennée
---
tests/docker/Makefile.include | 9 +
1 file changed, 9 insertions(+)
diff --git a/tests/docker/Makefile.include b/tests/docker/Makefile.include
index cb0961a69e4..46f95320e54 100644
--- a/tests/
Now that the two updates from v1.3 are implemented,
update the "any" cpu to enable it.
Reviewed-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index f
The specification of this insn is round-to-zero.
Reviewed-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/fpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c
index b9d2ebbb8c..4cc5b2
Debian Sid was only ever a stop gap and thanks to the much better
cross compiler in the Buster release we don't need it any more. Send
it on its merry way.
Signed-off-by: Alex Bennée
---
tests/docker/Makefile.include | 2 +-
tests/docker/dockerfiles/debian-sid.docker | 41 -
From: Philippe Mathieu-Daudé
Avocado tests download artifacts from various sources.
These sources sometime have network issues resulting in build
failures. Cache Avocado cache to reduce build failure.
See https://docs.travis-ci.com/user/caching/#arbitrary-directories
Signed-off-by: Philippe Mat
This is hardware support for double-precision floating-point using
pairs of 32-bit registers. Fix latent bugs in the heretofore unused
helper_itofd and helper_ftoid. Include the bit for cpu "any".
Change the default cpu for linux-user to "any".
Reviewed-by: Stafford Horne
Signed-off-by: Richard
From: Philippe Mathieu-Daudé
We always install the same packages ever and ever, cache them.
See https://docs.travis-ci.com/user/caching/#pip-cache
Signed-off-by: Philippe Mathieu-Daudé
---
.travis.yml | 1 +
1 file changed, 1 insertion(+)
diff --git a/.travis.yml b/.travis.yml
index 8c376d22
Update the CPUCFG bits to arch v1.3.
Include support for AVRP for cpu "any".
Signed-off-by: Richard Henderson
---
target/openrisc/cpu.h| 11 +++
target/openrisc/cpu.c| 8 ++--
target/openrisc/sys_helper.c | 6 ++
3 files changed, 19 insertions(+), 6 deletions(-)
From: Philippe Mathieu-Daudé
By default, ccache is not installed on macOS environments.
See https://docs.travis-ci.com/user/caching/#ccache-on-macos
Signed-off-by: Philippe Mathieu-Daudé
---
.travis.yml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/.travis.yml b/.travis.yml
index 5a87
The writes to cpu_R[0] are now a race across threads, now that we
do code generation in parallel. Stage the change by introducing
a function to return the temp for R0.
Reviewed-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 213 ---
These SPRs are read-only. The writes can simply be ignored,
as we already do for other read-only (or missing) registers.
There is no reason to mask the value in env->vr.
Reviewed-by: Stafford Horne
Signed-off-by: Richard Henderson
---
target/openrisc/cpu.h| 3 ---
target/openrisc/sys_
Now Buster is released we can stop relying on the movable feast that
is Sid for our cross-compiler for building tests.
Signed-off-by: Alex Bennée
---
tests/docker/Makefile.include| 2 +-
tests/docker/dockerfiles/debian-riscv64-cross.docker | 5 ++---
2 files changed, 3 in
Now Buster is released we can stop relying on the movable feast that
is Sid for our cross-compiler for building tests.
Signed-off-by: Alex Bennée
---
tests/docker/Makefile.include| 2 +-
tests/docker/dockerfiles/debian-powerpc-cross.docker | 8 +++-
2 files changed, 4
On Wed, Sep 04, 2019 at 02:22:39PM +0800, Tao Xu wrote:
> On 9/4/2019 1:52 AM, Eduardo Habkost wrote:
> > On Mon, Aug 05, 2019 at 03:13:02PM +0800, Tao Xu wrote:
> > > Add MachineClass::auto_enable_numa field. When it is true, a NUMA node
> > > is expected to be created implicitly.
> > >
> > > Ack
The following changes since commit a8b5ad8e1faef0d1bb3e550530328e8ec76fe87c:
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
(2019-09-04 17:22:34 +0100)
are available in the Git repository at:
https://github.com/rth7680/qemu.git tags/pull-or1k-20190904
Now Buster is released we can stop relying on the movable feast that
is Sid for our cross-compiler for building tests.
Signed-off-by: Alex Bennée
---
tests/docker/Makefile.include | 2 +-
tests/docker/dockerfiles/debian-hppa-cross.docker | 5 ++---
2 files changed, 3 insertio
For whatever reason this doesn't trigger normally but because
compile_prog uses QEMU_CFLAGS we end up trying to build a -pie
--no-pie build which confuses compilers on some non-x86 hosts.
Signed-off-by: Alex Bennée
---
configure | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
Now Buster is released we can stop relying on the movable feast that
is Sid for our cross-compiler for building tests.
Signed-off-by: Alex Bennée
---
tests/docker/Makefile.include| 2 +-
tests/docker/dockerfiles/debian-sparc64-cross.docker | 5 ++---
2 files changed, 3 in
The Debian QEMU packages require a bunch of cross compilers for
building firmware which aren't available on all host architectures.
Using --arch-only skips this particular requirement and allows us to
install just the dependencies we need.
Signed-off-by: Alex Bennée
---
tests/docker/dockerfiles/
From: Paolo Bonzini
Rename Makefile.probe to Makefile.prereqs and make it actually
define rules for the tests.
Rename Makefile to Makefile.target, since it is not a toplevel
makefile.
Rename Makefile.include to Makefile.qemu and disentangle it
from the QEMU Makefile.target, so that it is invoke
From: Philippe Mathieu-Daudé
These jobs build different components but use the same
host features. Put them in the same cache bucket.
Signed-off-by: Philippe Mathieu-Daudé
---
.travis.yml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/.travis.yml b/.travis.yml
index 63cbf41e573..17aca3
We need to add additional packages to the base images to be able to
build QEMU so lets avoid building with it.
Signed-off-by: Alex Bennée
---
tests/docker/Makefile.include | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/docker/Makefile.include b/tests/docker/Makefile.in
From: Philippe Mathieu-Daudé
We will set the CACHE_NAME variable to improve the caching
of various jobs using the same characteristics. Document it
first.
See https://docs.travis-ci.com/user/caching/#caches-and-build-matrices
Signed-off-by: Philippe Mathieu-Daudé
---
.travis.yml | 6 ++
1
Hi All,
Here is the current status of my testing/next queue. It brings
together a number of different series as well as some CI fixes that
may be coming in view different trees. So in order we have:
Some fixes to for podman. This is a relatively new alternative to
docker and it works well but nee
This was only added in Python 3.6 and not all the build hosts have
that recent a python3. However those that do will complain if
everything isn't properly utf-8 clean:
./tests/docker/docker.py --engine auto build qemu:debian-amd64
tests/docker/dockerfiles/debian-amd64.docker --add-current-use
From: Paolo Bonzini
Avoid the repeated inclusions of config-target.mak, which have
risks of namespace pollution, and instead build minimal configuration
files in a configuration script. The same configuration files can
also be included in Makefile and Makefile.qemu
Signed-off-by: Paolo Bonzini
From: Cleber Rosa
The LinuxInitrd.test_with_2gib_file_should_work_with_linux_v4_16 test,
from tests/acceptance/linux_initrd.py, is currently failing to fetch
the "vmlinuz" file. The reason for the failure is that the Fedora
project retires older versions from the "dl.fedoraproject.org" URL,
and
From: Thomas Huth
Most of the code in hw/misc/ does not directly depend on CPU-specific
code. Mark it as "common" so that the code can be shared between e.g.
qemu-system-arm and qemu-system-aarch64, or between the various mips
flavours, instead of recompiling it for each and every target again
an
You can assume the failures most people are interested in are the
cross-compile failures that are specific to the cross compile target.
Set DEF_TARGET_LIST based on what we use for shippable, the user can
always override by calling with TARGET_LIST set.
Signed-off-by: Alex Bennée
---
tests/docke
Another image that can't be used directly to build QEMU.
Signed-off-by: Alex Bennée
---
tests/docker/Makefile.include | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/docker/Makefile.include b/tests/docker/Makefile.include
index 8d7f9376578..2c8cb790ad0 100644
--- a/test
Now Buster is released we can stop relying on the movable feast that
is Sid for our cross-compiler for building tests.
Signed-off-by: Alex Bennée
---
tests/docker/Makefile.include| 2 +-
tests/docker/dockerfiles/debian-sh4-cross.docker | 5 ++---
2 files changed, 3 insertions
On Sat, Aug 31, 2019 at 11:48:34AM +1000, David Gibson wrote:
> On Fri, Aug 30, 2019 at 02:56:48PM -0300, Eduardo Habkost wrote:
> > On Thu, Aug 29, 2019 at 11:31:25AM +1000, David Gibson wrote:
> > > If I attempt to run "make check-acceptance" on my POWER9, RHEL8.1
> > > machine when the openssl-d
From: Paolo Bonzini
For i386 specifically, this allows using the host GCC
to compile the i386 tests. But, it should really be
done for all targets, unless we want to pass $(EXTRA_CFLAGS)
directly as part of $(CC).
Signed-off-by: Paolo Bonzini
Message-Id: <20190807143523.15917-2-pbonz...@redhat
Now Buster is released we can stop relying on the movable feast that
is Sid for our cross-compiler for building tests.
Signed-off-by: Alex Bennée
---
tests/docker/Makefile.include | 2 +-
tests/docker/dockerfiles/debian-alpha-cross.docker | 7 +++
2 files changed, 4 inse
Now Buster is released we can stop relying on the movable feast that
is Sid for our cross-compiler for building tests.
Signed-off-by: Alex Bennée
---
tests/docker/Makefile.include | 2 +-
tests/docker/dockerfiles/debian-m68k-cross.docker | 5 ++---
2 files changed, 3 insertio
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 42 ++
target/arm/t16.decode | 4
2 files changed, 6 insertions(+), 40 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index d409afd5
On Sat, Aug 31, 2019 at 7:54 PM Bin Meng wrote:
>
> As of today, the QEMU 'sifive_u' machine is a special target that does
> not boot the upstream OpenSBI/U-Boot firmware images built for the real
> SiFive HiFive Unleashed board. Hence OpenSBI supports a special platform
> "qemu/sifive_u". For U-B
From: Philippe Mathieu-Daudé
Using the 'multiple caching features' means explode the YAML array,
thus it eases the git workflow (it is easier to move patches around).
See https://docs.travis-ci.com/user/caching#enabling-multiple-caching-features
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-b
Now Buster is released we can unify our cross build images for both
QEMU and tests.
Signed-off-by: Alex Bennée
---
tests/docker/Makefile.include| 5 ++---
.../docker/dockerfiles/debian-arm64-cross.docker | 4 ++--
.../dockerfiles/debian-buster-arm64-cross.docker | 16 --
Podman requires a little bit of additional magic to the uid mapping
which was already done for the normal RunCommand. We simplify the
logic by pushing it directly into the Docker::run method to avoid
instantiating an extra Docker() object and ensure the CC command
always runs as the current user.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 15 ++-
target/arm/t16.decode | 9 +
2 files changed, 11 insertions(+), 13 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 73c8863134..8399a2c1f6 100644
We might as well not repeat ourselves. At the same time allow it to be
overridden which we will use later from docker targets.
Signed-off-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
---
tests/docker/common.rc | 4
tests/docker/test-build | 1 -
tests/docker/test-mingw | 1 -
tests
This hides the new build artefacts from the re-organised TCG tests when
you are doing an in-source build.
Signed-off-by: Alex Bennée
---
tests/tcg/.gitignore | 5 +
1 file changed, 5 insertions(+)
create mode 100644 tests/tcg/.gitignore
diff --git a/tests/tcg/.gitignore b/tests/tcg/.gitign
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 48 --
target/arm/t16.decode | 8 +++
2 files changed, 17 insertions(+), 39 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index d8a4
Now that everything is converted, remove the rest of
the legacy decode.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 27 ++-
1 file changed, 2 insertions(+), 25 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/tra
The introduction of podman support inadvertently broke configure's
detect of the container support as the configure probe didn't specify
an engine type. To fix this in docker.py:
- only (re)set USE_ENGINE if --engine is specified
- enhance the output so docker is no longer just yes
In the con
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 12 +---
target/arm/t16.decode | 7 +++
2 files changed, 8 insertions(+), 11 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 4ae73d1c92..d8a4c7bf99 100644
--- a
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 9 ++---
target/arm/t16.decode | 6 ++
2 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 4f4c77fc89..3238ccbf1e 100644
--- a/target
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 94 +++---
target/arm/t16.decode | 33 +++
2 files changed, 38 insertions(+), 89 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
in
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 26 +++---
target/arm/t16.decode | 12
2 files changed, 15 insertions(+), 23 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index ed52018c17..a48
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