Signed-off-by: Wei Yang
---
hw/i386/acpi-build.c | 22 ++
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index bec0bed53e..a7aeb215fc 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -383,12 +383,25 @@
Signed-off-by: Wei Yang
---
hw/i386/acpi-build.c | 21 ++---
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 4b480efff9..a661fff51d 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -339,9 +339,22 @@ st
Signed-off-by: Wei Yang
---
hw/i386/acpi-build.c | 22 ++
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index f48cc5b292..bec0bed53e 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -371,11 +371,24 @@
Different arch would handle the main madt table differently. Add a
helper function to achieve this goal.
Signed-off-by: Wei Yang
---
hw/acpi/piix4.c | 1 +
hw/i386/acpi-build.c | 13 +++--
hw/isa/lpc_ich9.c| 1 +
include/hw/acpi/
struct madt_input is introduced to represent one sub madt table.
With help of madt_sub[] for related sub madt table, build_madt could
be agnostic.
Signed-off-by: Wei Yang
---
hw/i386/acpi-build.c | 103 +++
1 file changed, 65 insertions(+), 38 deletions(-
Signed-off-by: Wei Yang
---
hw/i386/acpi-build.c | 37 -
1 file changed, 24 insertions(+), 13 deletions(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index a661fff51d..f48cc5b292 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -35
On 12/05/2019 20:21, Michael S. Tsirkin wrote:
On Fri, May 10, 2019 at 03:42:00PM +0200, Laurent Vivier wrote:
Add a new RNG backend using QEMU builtin getrandom function.
This patch applies on top of
"[PATCH v5 00/24] Add qemu_getrandom and ARMv8.5-RNG etc"
Based-on: 20190510012458.22706-
The only remaining caller of pci_get_bus_devfn() is pci_nic_init_nofail(),
itself an old compatibility function. Fold the two together to avoid
re-using the stale interface.
While we're there replace the explicit fprintf()s with error_report().
Signed-off-by: David Gibson
---
hw/pci/pci.c | 60
Signed-off-by: Wei Yang
---
hw/acpi/cpu.c| 14 ++
hw/i386/acpi-build.c | 33 +
2 files changed, 23 insertions(+), 24 deletions(-)
diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c
index 35e57f9824..cb5970d659 100644
--- a/hw/acpi/cpu.c
+++ b/hw/acpi/c
Signed-off-by: Wei Yang
---
hw/acpi/cpu.c| 15 +++
hw/acpi/piix4.c | 1 +
hw/i386/acpi-build.c | 39 +++-
hw/isa/lpc_ich9.c| 1 +
include/hw/acpi/acpi_dev_interface.h | 5
incl
This is a preparation for MADT refactor.
Signed-off-by: Wei Yang
---
hw/acpi/cpu.c| 33 +++--
hw/acpi/piix4.c | 1 -
hw/i386/acpi-build.c | 71
hw/isa/lpc_ich9.c| 1 -
include/
On Sun, May 12, 2019 at 02:13:30PM -0400, Michael S. Tsirkin wrote:
> On Tue, May 07, 2019 at 02:48:38PM +1000, David Gibson wrote:
> > On Fri, Apr 26, 2019 at 04:40:17PM +1000, Alexey Kardashevskiy wrote:
> > >
> > >
> > > On 24/04/2019 14:19, David Gibson wrote:
> > > > Since c2077e2c "pci: Adj
The is_bridge field in PCIDevice acts as a bool, but is declared as an int.
Declare it as a bool for clarity, and change everything that writes it to
use true/false instead of 0/1 to match.
Signed-off-by: David Gibson
Reviewed-by: Greg Kurz
---
hw/pci-bridge/dec.c| 4 ++--
hw/pc
pci_bus_is_root() currently relies on a method in the PCIBusClass.
But it's always known if a PCI bus is a root bus when we create it, so
using a dynamic method is overkill.
This replaces it with an IS_ROOT bit in a new flags field, which is set on
root buses and otherwise clear. As a bonus this
Now MADT is highly depend in architecture and machine type and leaves
duplicated code in different architecture. The series here tries to generalize
it.
MADT contains one main table and several sub tables. These sub tables are
highly related to architecture. Here we introduce one method to make it
c2077e2c "pci: Adjust PCI config limit based on bus topology"
introduced checking the availability of extended config space for
PCI-E devices which are in a bus topology that doesn't permit extended
config space access (e.g. under PCI-E to PCI then PCI to PCI-E
bridges).
This caused some problems
These functions have an explicit test for accesses above the device's
config size. But pci_host_config_{read,write}_common() which they're
about to call already have checks against the config space limit and
do the right thing. So, remove the redundant tests.
Signed-off-by: David Gibson
Reviewe
Since c2077e2c "pci: Adjust PCI config limit based on bus topology",
pci_adjust_config_limit() has been used in the config space read and write
paths to only permit access to extended config space on buses which permit
it. Specifically it prevents access on devices below a vanilla-PCI bus via
some
On Thu, 09 May 2019 01:27:40 +0900,
Philippe Mathieu-Daudé wrote:
>
> On 5/8/19 4:56 PM, Yoshinori Sato wrote:
> > This implementation supported only ICUa.
> > Hardware manual.
> > https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf
> >
> > Signed-off-by: Yos
On 09/05/2019 22.50, Collin Walling wrote:
> On 5/9/19 5:58 AM, Christian Borntraeger wrote:
>>
>>
>> On 02.05.19 00:31, Collin Walling wrote:
>>> DIAGNOSE 0x318 (diag318) is a privileged s390x instruction that must
>>> be intercepted by SIE and handled via KVM. Let's introduce some
>>> functions t
On Mon, May 13, 2019 at 11:10:28AM +0530, Aravinda Prasad wrote:
>
>
> On Friday 10 May 2019 09:55 PM, Greg Kurz wrote:
> > On Mon, 22 Apr 2019 12:33:16 +0530
> > Aravinda Prasad wrote:
> >
> >> Memory error such as bit flips that cannot be corrected
> >> by hardware are passed on to the kernel
On Fri, May 10, 2019 at 04:02:56PM +0100, Mark Cave-Ayland wrote:
> On 09/05/2019 01:49, Anton Blanchard wrote:
>
> > We were using set_cpu_vsr*() when we should have used get_cpu_vsr*().
> >
> > Fixes: 8b3b2d75c7c0 ("introduce get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}()
> > helpers for VSR regist
On Thu, 09 May 2019 01:16:58 +0900,
Philippe Mathieu-Daudé wrote:
>
> On 5/8/19 4:56 PM, Yoshinori Sato wrote:
> > This module supported only non FIFO type.
> > Hardware manual.
> > https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf
> >
> > Signed-off-by: Yo
On Friday 10 May 2019 09:55 PM, Greg Kurz wrote:
> On Mon, 22 Apr 2019 12:33:16 +0530
> Aravinda Prasad wrote:
>
>> Memory error such as bit flips that cannot be corrected
>> by hardware are passed on to the kernel for handling.
>> If the memory address in error belongs to guest then
>> the gu
On Friday 10 May 2019 03:22 PM, David Gibson wrote:
> On Fri, May 10, 2019 at 12:35:13PM +0530, Aravinda Prasad wrote:
>>
>>
>> On Friday 10 May 2019 12:12 PM, David Gibson wrote:
>>> On Mon, Apr 22, 2019 at 12:33:26PM +0530, Aravinda Prasad wrote:
[...]
+/* Save gpr[3] in the guest e
On Friday 10 May 2019 08:03 PM, Greg Kurz wrote:
> On Fri, 10 May 2019 11:06:04 +0200
> Greg Kurz wrote:
>
>> On Mon, 22 Apr 2019 12:32:58 +0530
>> Aravinda Prasad wrote:
>>
>>> This patch adds support in QEMU to handle "ibm,nmi-register"
>>> and "ibm,nmi-interlock" RTAS calls.
>>>
>>> The ma
> > Guest reads the persistent memory range information from
> > Qemu over VIRTIO and registers it on nvdimm_bus. It also
> > creates a nd_region object with the persistent memory
> > range information so that existing 'nvdimm/pmem' driver
> > can reserve this into system memory map. This way
> >
On Friday 10 May 2019 02:36 PM, Greg Kurz wrote:
> On Mon, 22 Apr 2019 12:32:58 +0530
> Aravinda Prasad wrote:
>
>> This patch adds support in QEMU to handle "ibm,nmi-register"
>> and "ibm,nmi-interlock" RTAS calls.
>>
>> The machine check notification address is saved when the
>> OS issues "i
Sorry for the noise, is there any more comment for this patch?
Without this patch, ignore shared capabilities can not be used on arm64
B.R.
Catherine
On Tue, 16 Apr 2019 at 10:51, Peter Xu wrote:
> On Mon, Apr 08, 2019 at 04:42:13AM -0400, Catherine Ho wrote:
> > Commit 18269069c310 ("migration
On Fri, May 10, 2019 at 10:30:48AM -0700, Richard Henderson wrote:
> Generating a random number counts as I/O, as it cannot be
> replayed and produce the same results.
>
> Cc: David Gibson
> Suggested-by: Peter Maydell
> Signed-off-by: Richard Henderson
Acked-by: David Gibson
> ---
> target
On Fri, May 10, 2019 at 05:48:38PM +0800, Cornelia Huck wrote:
> On Fri, 10 May 2019 10:36:09 +0100
> "Dr. David Alan Gilbert" wrote:
>
> > * Cornelia Huck (coh...@redhat.com) wrote:
> > > On Thu, 9 May 2019 17:48:26 +0100
> > > "Dr. David Alan Gilbert" wrote:
> > >
> > > > * Cornelia Huck (c
On Fri, May 10, 2019 at 04:38:49PM +0200, Pierre Morel wrote:
> This should be copied from Linux kernel UAPI includes.
>
> Signed-off-by: Pierre Morel
pls add a note which linux version did you sync with.
> ---
> linux-headers/linux/vfio.h | 16 +---
> 1 file changed, 13 insertions
On Fri, May 10, 2019 at 03:42:00PM +0200, Laurent Vivier wrote:
> Add a new RNG backend using QEMU builtin getrandom function.
>
> This patch applies on top of
> "[PATCH v5 00/24] Add qemu_getrandom and ARMv8.5-RNG etc"
> Based-on: 20190510012458.22706-1-richard.hender...@linaro.org
>
> v3: I
On Thu, May 02, 2019 at 04:51:49PM +0200, Igor Mammedov wrote:
> so name would reflect what the function does
>
> Signed-off-by: Igor Mammedov
> Reviewed-by: Philippe Mathieu-Daudé
> Reviewed-by: Wei Yang
> ---
> v4:
> * make it as the first patch in series
> ---
FYI this trips up git am.
Do
On Tue, May 07, 2019 at 02:48:38PM +1000, David Gibson wrote:
> On Fri, Apr 26, 2019 at 04:40:17PM +1000, Alexey Kardashevskiy wrote:
> >
> >
> > On 24/04/2019 14:19, David Gibson wrote:
> > > Since c2077e2c "pci: Adjust PCI config limit based on bus topology",
> > > pci_adjust_config_limit() has
On Fri, May 10, 2019 at 09:21:58PM +0530, Pankaj Gupta wrote:
> This patch adds virtio-pmem driver for KVM guest.
>
> Guest reads the persistent memory range information from
> Qemu over VIRTIO and registers it on nvdimm_bus. It also
> creates a nd_region object with the persistent memory
> range
On Fri, May 10, 2019 at 07:33:03PM -0400, Pankaj Gupta wrote:
>
> > >
> > > Hi Michael & Dan,
> > >
> > > Please review/ack the patch series from LIBNVDIMM & VIRTIO side.
> > > We have ack on ext4, xfs patches(4, 5 & 6) patch 2. Still need
> > > your ack on nvdimm patches(1 & 3) & virtio patch
We should keep the error handling consistent. ENOMEDIUM is more meaningful than
ENOENT a when driver cannot be loaded.
---
block.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/block.c b/block.c
index 5c2c6aa..6685be7 100644
--- a/block.c
+++ b/block.c
@@ -770,7 +770,7
(The last email does not include signed-off-by line. Please ignoreit)
We should keep the error handling consistent. ENOMEDIUM is more meaningful than
ENOENT a when driver cannot be loaded.
Signed-off-by: Wensheng Tang
---
block.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
dif
On 11/05/2019 20.28, Programmingkid wrote:
>
>> On May 11, 2019, at 2:05 PM, Thomas Huth wrote:
>>
>> On 11/05/2019 19.21, Programmingkid wrote:
>>>
On Apr 20, 2019, at 6:40 AM, Thomas Huth wrote:
On 19/04/2019 15.44, G 3 wrote:
[...]
> Thank you for replying. Capstone comes w
Public bug reported:
With user mode emulation, messages from genu_log() are emitted
unconditionally to stderr. I didn't find a way to suppress them. It
would be nice to have options similar to the -D/-d options to be able to
filter and/or redirect the output.
My use case is chroot/container execu
Introduce another cpu property to control SVE vector lengths,
sve-vls-map, which allows the user to explicitly select the
set of vector lengths the guest can use. The map must conform
to QEMU's limits and architectural constraints, checked when
the property is set. Inconsistencies with sve-max-vq a
---
linux-headers/asm-arm64/kvm.h | 41 +
linux-headers/asm-arm64/sve_context.h | 53 +++
linux-headers/linux/kvm.h | 5 +++
3 files changed, 99 insertions(+)
create mode 100644 linux-headers/asm-arm64/sve_context.h
diff --git a/li
Move the getting/putting of the fpsimd registers out of
kvm_arch_get/put_registers() into their own helper functions
to prepare for alternatively getting/putting SVE registers.
No functional change.
Signed-off-by: Andrew Jones
---
target/arm/kvm64.c | 148 +++
These are the SVE equivalents to kvm_arch_get/put_fpsimd.
Signed-off-by: Andrew Jones
---
target/arm/kvm64.c | 127 +++--
1 file changed, 123 insertions(+), 4 deletions(-)
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index 61947f3716e1..86362f4cd7
Provide a QMP interface to query the supported SVE vector lengths.
A migratable guest will need to explicitly specify a valid set of
lengths on the command line and that set can be obtained from the
list returned with this QMP command.
This patch only introduces the QMP command with the TCG implem
While the TCG SVE implementation can implement all vector lengths
which are a quadword multiple, up to some maximum length, KVM can
only provide what the host supports, and not all multiples are
required to be supported by the architecture. With this patch
we extend the QMP query to ask KVM for the
Signed-off-by: Andrew Jones
---
scripts/update-linux-headers.sh | 3 +++
1 file changed, 3 insertions(+)
diff --git a/scripts/update-linux-headers.sh b/scripts/update-linux-headers.sh
index c3819d2b983d..e1fce54f8aa3 100755
--- a/scripts/update-linux-headers.sh
+++ b/scripts/update-linux-headers
Allow the host cpu type to enable SVE in guests with the sve-vls-map
cpu property.
Signed-off-by: Andrew Jones
---
target/arm/cpu.c | 1 +
target/arm/cpu.h | 2 ++
target/arm/cpu64.c | 12 +---
3 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/target/arm/cpu.c b/targe
The max cpu type can have its SVE vector lengths explicitly set
with the sve-vls-map property. This patch allows that property
to work when KVM is in use. The map must conform to additional
constraints for KVM which are checked at vcpu init.
Signed-off-by: Andrew Jones
---
target/arm/cpu64.c |
Enable SVE in the KVM guest when the 'max' cpu type is configured
and KVM supports it. KVM SVE requires use of the new finalize
vcpu ioctl, so we add that now too.
Signed-off-by: Andrew Jones
---
target/arm/cpu64.c | 1 +
target/arm/kvm.c | 5 +
target/arm/kvm64.c | 16
A couple return -EINVAL's forget their '-'s.
Signed-off-by: Andrew Jones
---
target/arm/kvm64.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index e3ba1492482f..ba232b27a6d3 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.
Signed-off-by: Andrew Jones
---
target/arm/kvm64.c | 7 +--
target/arm/kvm_arm.h | 20
2 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index 0c666e405357..11c6334a7c08 100644
--- a/target/arm/kvm64.c
+++ b/target/
Allow the cpu type 'max' sve-max-vq property to work with kvm
too. If the property is not specified then the maximum kvm
supports is used. If it is specified we check that kvm supports
that exact length or error out if it doesn't.
Signed-off-by: Andrew Jones
---
target/arm/cpu.h | 4 +++
targ
With the recent KVM guest SVE support pull request [1] KVM will be
ready for guests with SVE. This series provides the QEMU bits for
that enablement. The series starts with the bits needed for the KVM
SVE ioctls. Then it enables the arm 'max'cpu type, which with TCG
already supports SVE, to also su
Gentle ping on "[PATCH 2/2] vmdk: Add read-only support for seSparse snapshots”.
Yuchenlin reviewed "[PATCH 1/2] vmdk: Fix comment regarding max l1_size
coverage”.
Thanks, Sam
> On 24 Apr 2019, at 10:48, Sam Eiderman wrote:
>
> VMware introduced a new snapshot format in VMFS6 - seSparse (Space
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