On Tue, Mar 19, 2019 at 10:21:13AM -0700, Richard Henderson wrote:
> PowerPC Altivec does not support direct moves between vector registers
> and general registers. So when tcg_out_mov fails, we can use the
> backing memory for the temporary to perform the move.
>
> Signed-off-by: Richard Henders
BALATON Zoltan writes:
> On Tue, 19 Mar 2019, Paolo Bonzini wrote:
>> Do not create an ATI VGA if "-vga none" was passed on the command line.
>>
>> Cc: BALATON Zoltan
>
> Thanks, I did not know about this variable. Although the real hardware
> has the GPU soldered on the mainboard it makes sense
BALATON Zoltan writes:
> On Tue, 19 Mar 2019, Paolo Bonzini wrote:
>> Do not create an ATI VGA if "-vga none" was passed on the command line.
>>
>> Cc: BALATON Zoltan
>
> Thanks, I did not know about this variable. Although the real hardware
> has the GPU soldered on the mainboard it makes sense
On Tue, Mar 19, 2019 at 11:49:22AM -0400, Catherine Ho wrote:
> Commit 18269069c310 ("migration: Introduce ignore-shared capability")
> addes a ignore-shared capability to bypass the shared ramblock (e,g,
> membackend + numa node). It does good to live migration.
>
> This commit expected that QEM
Hello,
On behalf of the QEMU Team, I'd like to announce the availability of the
first release candidate for the QEMU 4.0 release. This release is meant
for testing purposes and should not be used in a production environment.
http://download.qemu-project.org/qemu-4.0.0-rc0.tar.xz
http://downl
Yes, While a guest tries to access it and detach remote cdrom at sametime.
-邮件原件-
发件人: John Snow [mailto:js...@redhat.com]
发送时间: 2019年3月20日 0:35
收件人: lizhengui
抄送: qemu-bl...@nongnu.org; Fangyi (C); qemu-devel@nongnu.org; wangjie (P);
pbonz...@redhat.com; stefa...@redhat.com; mre...@redh
On 20/03/2019 01:32, Fabiano Rosas wrote:
> Alexey Kardashevskiy writes:
>
>> Looks good to me, does not break what already works. However I cannot
>> debug SLOF real mode and I am not sure why.
>>
>> (gdb) set endian big
>>
>> The target is assumed to be big endian
>> (gdb) b *0x3f00
>>
>> Br
On Sat, Mar 16, 2019 at 03:23:09PM +0100, BALATON Zoltan wrote:
> On Sat, 16 Mar 2019, BALATON Zoltan wrote:
> > Version 4 try to fix an ASan warning about leaking bitbang_i2c.
>
> I still get ASan warning but it's about gpio_i2c_init in bitbang_i2c.c which
> I haven't changed nor using so I think
i'd rather the copyright notice on these files looks like i've put it
below and since i just simply snipped my name(i'll provide legal proof
that this is my name, if required), i don't expect this to be an issue.
IOMMU AUTHOR (1):
update copyright notice
hw/i386/amd_iommu.c | 1 -
hw/i386/amd_
Signed-off-by: IOMMU AUTHOR
---
hw/i386/amd_iommu.c | 1 -
hw/i386/amd_iommu.h | 1 -
2 files changed, 2 deletions(-)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index 6eabdf99..e4f3e9c0 100644
--- a/hw/i386/amd_iommu.c
+++ b/hw/i386/amd_iommu.c
@@ -2,7 +2,6 @@
* QEMU emulation of A
On 2019/3/19 23:49, Catherine Ho wrote:
Commit 18269069c310 ("migration: Introduce ignore-shared capability")
addes a ignore-shared capability to bypass the shared ramblock (e,g,
membackend + numa node). It does good to live migration.
This commit expected that QEMU doesn't write to guest RAM
On Tue, Mar 19, 2019 at 10:00:38AM +0100, Igor Mammedov wrote:
>On Tue, 19 Mar 2019 08:45:23 +0800
>Wei Yang wrote:
>
>> On Mon, Mar 18, 2019 at 01:39:12PM +0100, Igor Mammedov wrote:
>> >On Fri, 15 Mar 2019 08:44:32 +0800
>> >Wei Yang wrote:
>> >
>> >in subject: s/extract/generalize/
>> >
>> >
On Mon, 18 Mar 2019, Gerd Hoffmann wrote:
Does it work with the latest patch for you?
No (testing with radeonfb.ko).
I'm confused. You said here that it works with radeonfb with your patch:
http://lists.nongnu.org/archive/html/qemu-devel/2019-03/msg04745.html
and my patch should be the same b
The first patch removes a unnecessary function
and the second is just a code reorg of usb_mtp_write_data
to make it less confusing. Applies on top of
[PATCH v3] usb-mtp: fix return status of delete
Message-ID:
Bandan Das (2):
usb-mtp: remove usb_mtp_object_free_one
usb-mtp: refactor the flow
On Tue, 19 Mar 2019, Paolo Bonzini wrote:
Do not create an ATI VGA if "-vga none" was passed on the command line.
Cc: BALATON Zoltan
Thanks, I did not know about this variable. Although the real hardware has
the GPU soldered on the mainboard it makes sense to allow it to be
disabled in QEMU
There's no functional change but the flow is (hopefully)
more consistent for both file and folder object types.
Signed-off-by: Bandan Das
---
hw/usb/dev-mtp.c | 58 +---
1 file changed, 30 insertions(+), 28 deletions(-)
diff --git a/hw/usb/dev-mtp.c b
On Tue, 19 Mar 2019, Igor Mammedov wrote:
On Sun, 17 Mar 2019 01:22:57 +0100
Philippe Mathieu-Daudé wrote:
The PIIX4 chipset is a generic southbridge and can be used by
non-X86 hardware. Introduce the ACPI_PIIX4 Kconfig.
Hardware that requires ACPI but doesn't need the PIIX4 chipset
won't comp
This function is used in the delete path only and can
be replaced by a call to usb_mtp_object_free.
Signed-off-by: Bandan Das
---
hw/usb/dev-mtp.c | 14 ++
1 file changed, 2 insertions(+), 12 deletions(-)
diff --git a/hw/usb/dev-mtp.c b/hw/usb/dev-mtp.c
index 91b820baaf..4dc1317e2e
When using a non-UTF8 secret to create a volume using qemu-img, the
following error happens:
$ qemu-img create -f luks --object
secret,id=vol_1_encrypt0,file=vol_resize_pool.vol_1.secret.qzVQrI -o
key-secret=vol_1_encrypt0 /var/tmp/pool_target/vol_1 10240K
Formatting '/var/tmp/pool_target/vol_1
Daniel P. Berrangé writes:
> Watch IDs are allocated from incrementing a int counter against
> the QFileMonitor object. In very long life QEMU processes with
> a huge amount of USB MTP activity creating & deleting directories
> it is just about conceivable that the int counter can wrap
> around.
Aleksandar Markovic writes:
>>
>> From: Peter Maydell
>> Subject: Re: [PATCH v3] target/mips: Fix minor bug in FPU
>>
>> On Tue, 19 Mar 2019 at 19:21, Aleksandar Markovic
>> wrote:
>> >
>> > > From: Mateja Marjanovic
>> > > Subject: [PATCH v3] target/mips: Fix minor bug in FPU
>> > >
>> > >
On 19/03/2019 14:40, Paolo Bonzini wrote:
> Do not create a TCX if "-vga none" was passed on the command line.
> Remove some dead code along the way to avoid big reindentation.
>
> Signed-off-by: Paolo Bonzini
> ---
> hw/sparc/sun4m.c | 6 ++
> 1 file changed, 2 insertions(+), 4 deletions(-
Hi all,
I get the following warning when trying to build current git master on a 32-bit
host:
ui/curses.c: In function ‘get_ucs’:
ui/curses.c:456:49: warning: format ‘%x’ expects argument of type ‘unsigned
int’, but
argument 3 has type ‘wchar_t’ {aka ‘long int’} [-Wformat=]
fprintf(std
On 3/19/19 1:05 PM, Eduardo Habkost wrote:
> Currently, the Cascadelake-Server, Icelake-Client, and
> Icelake-Server are always generating the following warning:
>
> qemu-system-x86_64: warning: \
> host doesn't support requested feature: CPUID.07H:ECX [bit 4]
>
> This happens because OSPKE
>
> From: Peter Maydell
> Subject: Re: [PATCH v3] target/mips: Fix minor bug in FPU
>
> On Tue, 19 Mar 2019 at 19:21, Aleksandar Markovic
> wrote:
> >
> > > From: Mateja Marjanovic
> > > Subject: [PATCH v3] target/mips: Fix minor bug in FPU
> > >
> > > From: Mateja Marjanovic
> > >
> > > Wron
> From: Peter Maydell
> Sent: Monday, March 11, 2019 3:48 PM
> To: Aleksandar Markovic
> Cc: Alex Bennée; Mateja Marjanovic; qemu-devel@nongnu.org;
> aurel...@aurel32.net; Aleksandar Rikalo
> Subject: Re: [PATCH] target/mips: Fix minor bug in FPU
>
> On Mon, 11 Mar 2019 at 14:35, Aleksandar Mark
Currently, the Cascadelake-Server, Icelake-Client, and
Icelake-Server are always generating the following warning:
qemu-system-x86_64: warning: \
host doesn't support requested feature: CPUID.07H:ECX [bit 4]
This happens because OSPKE was never returned by
GET_SUPPORTED_CPUID or x86_cpu_get
On 19.03.2019 19:44, Andrey Shinkevich wrote:
>
>
> On 18/03/2019 17:42, Alberto Garcia wrote:
>> On Tue 26 Feb 2019 05:39:41 PM CET, Andrey Shinkevich wrote:
>>> On 26/02/2019 16:33, Alberto Garcia wrote:
On Mon 25 Feb 2019 05:39:14 PM CET, Vladimir Sementsov-Ogievskiy wrote:
>> --- a
On Sat, Mar 16, 2019 at 01:05:57PM +0100, BALATON Zoltan wrote:
> The bitbang i2c implementation is also useful for other device models
> such as DDC in display controllers. Move the header to include/hw/i2c/
> to allow it to be used from other device models and adjust users of
> this include. This
On Tue, 19 Mar 2019 at 19:21, Aleksandar Markovic
wrote:
>
> > From: Mateja Marjanovic
> > Subject: [PATCH v3] target/mips: Fix minor bug in FPU
> >
> > From: Mateja Marjanovic
> >
> > Wrong type of NaN was generated for IEEE 754-2008 by MADDF. and
> > MSUBF. instructions when the arguments were
> From: Mateja Marjanovic
> Subject: [PATCH v3] target/mips: Fix minor bug in FPU
>
> From: Mateja Marjanovic
>
> Wrong type of NaN was generated for IEEE 754-2008 by MADDF. and
> MSUBF. instructions when the arguments were (inf, zero, nan) or
> (zero, inf, nan).
> These instructions were teste
On Tue, 19 Mar 2019 at 18:24, Alistair Francis wrote:
>
> Signed-off-by: Alistair Francis
> ---
> target/riscv/cpu.c | 10 --
> target/riscv/cpu.h | 1 -
> 2 files changed, 11 deletions(-)
Won't this break linux-user? cpu_get_model() in linux-user/riscv/target_elf.h
specifies the "any"
On Tue, 19 Mar 2019 at 18:34, Markus Armbruster wrote:
Here are some command lines from my image zoo. Unfortunately
typically the images themselves are random accumulations
from people and I have no idea how to rebuild them (and
they are thus not redistributable, generally).
> = hw/arm/integ
Markus Armbruster writes:
> Dear board code maintainers,
>
> This is a (rather late) follow-up to the last QEMU summit. Minutes[*]:
>
> * Deprecating unmaintained features (devices, targets, backends) in QEMU
>
>QEMU has a mechanism to deprecate features but there remains a lot of
>old
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 52 ++
target/riscv/cpu.h | 8 +++
2 files changed, 56 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 31561c719f..b6408e0a83 100644
--- a/target/ris
Signed-off-by: Alistair Francis
---
hw/riscv/virt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index fc4c6b306e..5b25f028ad 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -400,7 +400,7 @@ static void riscv_virt_board_init(Machine
These can now be specified via the command line so we no longer need
these.
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 2 --
target/riscv/cpu.h | 2 --
2 files changed, 4 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 298413f6f6..1d507c5216 100644
--- a/ta
Add a generic spike machine (not tied to a version) and deprecate the
spike mahines that are tied to a specific version. As we can now specify
the CPU via the command line we no londer need specific versions of the
spike machines.
Signed-off-by: Alistair Francis
---
hw/riscv/spike.c | 106 ++
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 10 --
target/riscv/cpu.h | 1 -
2 files changed, 11 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b6408e0a83..298413f6f6 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -188,15 +188,6 @@ stat
If a user specifies a CPU that we don't understand then we want to fall
back to a CPU generated from the ISA string.
At the moment the generated CPU is assumed to be a privledge spec
version 1.10 CPU with an MMU. This can be changed in the future.
Signed-off-by: Alistair Francis
---
target/risc
This patch series adds a generic RISC-V CPU that can be generated at run
time based on the ISA string specified to QEMU via the -cpu argument. This
is supported on the virt and spike boards allowing users to specify the
RISC-V extensions as well as the ISA version.
As part of the conversion we hav
Patchew URL:
https://patchew.org/QEMU/20190319172126.7502-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190319172126.7502-1-richard.hender...@linaro.org
Type: series
Subject: [Qemu-devel] [PATCH f
On 3/19/19 10:05 AM, Aleksandar Markovic wrote:
> May I ask you to redo this segment of code as Richard
> describe (the exact invocations of TCG functions are in
> a Richard's comment to some of the previous versions of
> this patch). This means redo ILVEV.W handling. Then you
> can compare the per
The bug also affects shared-mime-info. update-mime-database uses readdir
and ends up generating an empty database without reporting any errors,
causing pixbuf and anything else that relies on the mime database not to
work properly.
Same things happens with update-ca-certificates. It calls c_rehash
This includes single-word loads and stores, lots of double-word
arithmetic, and a few extra logical operations.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.h | 3 +-
tcg/ppc/tcg-target.inc.c | 103 ---
2 files changed, 87 insertions(+), 19 de
This includes double-word loads and stores, double-word load and splat,
and double-word permute. All of which require multiple operations in
the base Altivec instruction set.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.h | 3 ++-
tcg/ppc/tcg-target.inc.c | 43 ++
There are a few missing operations yet, like expansion of
multiply and shifts. But this has move, load, store, and
basic arithmetic.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.h | 33 +-
tcg/ppc/tcg-target.opc.h | 3 +
tcg/ppc/tcg-target.inc.c | 721 +
For Altivec, this is done via vector shift by vector,
and loading the immediate into a register.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.h | 2 +-
tcg/ppc/tcg-target.inc.c | 58 ++--
2 files changed, 57 insertions(+), 3 deletions(-)
diff
Currently stubbed out in all backends that support vectors.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.inc.c | 6 ++
tcg/i386/tcg-target.inc.c| 7 +++
tcg/tcg.c| 19 ++-
3 files changed, 31 insertions(+), 1 deletion(-)
diff --gi
This includes vector load/store with immediate offset, some extra
move and splat insns, compare ne, and negate.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.h | 3 +-
tcg/ppc/tcg-target.inc.c | 103 ++-
2 files changed, 94 insertions(+), 12 de
For Altivec, this is always an expansion.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.h | 2 +-
tcg/ppc/tcg-target.opc.h | 8 +++
tcg/ppc/tcg-target.inc.c | 112 ++-
3 files changed, 120 insertions(+), 2 deletions(-)
diff --git a/tcg/ppc/t
This case is similar to INDEX_op_mov_* in that we need to do
different things depending on the current location of the source.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.inc.c | 9 ++--
tcg/i386/tcg-target.inc.c| 8 ++-
tcg/tcg.c| 102
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.inc.c | 38 ++--
1 file changed, 36 insertions(+), 2 deletions(-)
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index b34a1e5b06..d32e83ddf2 100644
--- a/tcg/aarch64/tcg-target.
This patch merely changes the interface, aborting on all failures,
of which there are currently none.
Reviewed-by: David Gibson
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.inc.c | 5 +++--
tcg/arm/tcg-target.inc.c | 7 +--
tcg/i386/tcg-target.inc.c| 5 +++--
tcg/m
Changes since v2:
* Several generic tcg patches to improve dup vs dupi vs dupm.
In particular, if a global temp (like guest r10) is not in
a host register, we should duplicate from memory instead of
loading to an integer register, spilling to stack, loading
to a vector register,
At the same time, improve tcg_out_dupi_vec wrt broadcast
from the constant pool.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.inc.c | 57 +--
1 file changed, 43 insertions(+), 14 deletions(-)
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-t
The i386 backend already has these functions, and the aarch64
backend could easily split out one. Nothing is done with these
functions yet, but this will aid register allocation of
INDEX_op_dup_vec in a later patch.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.inc.c | 12
Allow the backend to expand dup from memory directly, instead of
forcing the value into a temp first. This is especially important
if integer/vector register moves do not exist.
Note that officially tcg_out_dupm_vec is allowed to fail.
If it did, we could fix this up relatively easily:
VECE ==
The only fixed_reg is cpu_env, and it should not be modified
during any TB. Therefore code that tries to special-case moves
into a fixed_reg is dead. Remove it.
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 85 +--
1 file changed, 38 inser
PowerPC Altivec does not support direct moves between vector registers
and general registers. So when tcg_out_mov fails, we can use the
backing memory for the temporary to perform the move.
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 25 ++---
1 file changed, 22 inserti
This allows us to fall back to integers if the tcg backend
does not support comparisons in the given vece.
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index d408e4d7ef..13e2dc6
Signed-off-by: Richard Henderson
---
tcg/tcg-op-vec.c | 49
1 file changed, 33 insertions(+), 16 deletions(-)
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index 27f65600c3..cfb18682b1 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@ -22
On Tue, Mar 19, 2019 at 04:16:14PM +, Daniel P. Berrangé wrote:
> On Tue, Mar 19, 2019 at 10:35:33PM +0800, Tao Xu wrote:
> > On 3/19/2019 8:16 PM, Daniel P. Berrangé wrote:
> > > The Cascadelake-Server CPU was added last year in
> > >
> > >commit c7a88b52f62b30c04158eeb07f73e3f72221b6a8
>
On 19/03/19 08:21, Markus Armbruster wrote:
> Fixes: b93b63f574c "test makefile overhaul"
>
> Signed-off-by: Markus Armbruster
> Reviewed-by: Eric Blake
> ---
> Posted long ago as part of an RFC series that got stuck due to lack of
> time. Rebased.
>
> tests/Makefile.include | 2 +-
> 1 file
On Tue, 19 Mar 2019 at 17:08, Daniel P. Berrangé wrote:
>
> The glibc-2.29.9000-6.fc31.x86_64 package finally includes the gettid
> function as part of unistd.h when __USE_GNU is defined. This clashes
> with linux-user code which unconditionally defines this function
> itself.
> We need to probe
On Mon, Mar 18, 2019 at 8:41 PM Palmer Dabbelt wrote:
>
> On Mon, 18 Mar 2019 17:33:38 PDT (-0700), alistai...@gmail.com wrote:
> > On Fri, Mar 15, 2019 at 6:22 PM Alistair Francis
> > wrote:
> >>
> >> On Fri, Mar 15, 2019 at 6:19 PM Alistair Francis
> >> wrote:
> >> >
> >> > v3:
> >> > - Add
> >> From: Alex Bennée
> >> Subject: Re: [PATCH v3] target/mips: Fix minor bug in FPU
> >>
> >> Queued to fpu/next, thanks.
> >
> > Alex, does this mean for 4.0 or 4.1?
>
> It's a bug fix so it will go in 4.0 I think.
Right, Alex, I also think it should be included in 4.0. Please include
this pa
On Tue, 19 Mar 2019 at 15:46, Kevin Wolf wrote:
>
> The following changes since commit b98a66201dbc7cf3b962f4bb260f66100cc75578:
>
> Merge remote-tracking branch
> 'remotes/palmer/tags/riscv-for-master-4.0-rc0-2' into staging (2019-03-19
> 12:55:02 +)
>
> are available in the Git repositor
The glibc-2.29.9000-6.fc31.x86_64 package finally includes the gettid
function as part of unistd.h when __USE_GNU is defined. This clashes
with linux-user code which unconditionally defines this function
itself.
/home/berrange/src/virt/qemu/linux-user/syscall.c:253:16: error: static
declaration o
> From: Richard Henderson
> Subject: Re: [Qemu-devel] [PATCH 2/2] target/mips: Optimize ILVEV.
> MSA instructions
>
> On 3/19/19 4:28 AM, Mateja Marjanovic wrote:
> > +tcg_gen_andi_i64(t1, msa_wr_d[wt * 2], mask);
> > +tcg_gen_andi_i64(t0, msa_wr_d[ws * 2], mask);
> > +tcg_gen_shli_i
On 3/19/19 4:28 AM, Mateja Marjanovic wrote:
> +tcg_gen_andi_i64(t1, msa_wr_d[wt * 2], mask);
> +tcg_gen_shri_i64(t1, t1, 32);
> +tcg_gen_andi_i64(t0, msa_wr_d[ws * 2], mask);
> +tcg_gen_or_i64(msa_wr_d[wd * 2], t1, t0);
Deposit, again.
r~
On 3/19/19 6:55 AM, Aleksandar Markovic wrote:
>> From: Mateja Marjanovic
>> Subject: [PATCH 2/2] target/mips: Optimize ILVEV. MSA instructions
>>
>> ...
>>
>> +static inline void gen_ilvev_d(CPUMIPSState *env, uint32_t wd,
>> + uint32_t ws, uint32_t wt)
>> +{
>> +
Le mar. 19 mars 2019 16:03, Paolo Bonzini a écrit :
> On 16/03/19 21:08, Philippe Mathieu-Daudé wrote:
> > Hi,
> >
> > This series contains Kconfig fixes to be able to run binaries
> > built using: './configure --without-default-devices'.
>
>
> Hi, I applied 1/2/3/6/7/8/9/12/13/14, with select re
On 18/03/2019 17:42, Alberto Garcia wrote:
> On Tue 26 Feb 2019 05:39:41 PM CET, Andrey Shinkevich wrote:
>> On 26/02/2019 16:33, Alberto Garcia wrote:
>>> On Mon 25 Feb 2019 05:39:14 PM CET, Vladimir Sementsov-Ogievskiy wrote:
> --- a/block/stream.c
> +++ b/block/stream.c
> @@ -259,6
On 3/19/19 4:28 AM, Mateja Marjanovic wrote:
> +tcg_gen_andi_i64(t1, msa_wr_d[wt * 2], mask);
> +tcg_gen_andi_i64(t0, msa_wr_d[ws * 2], mask);
> +tcg_gen_shli_i64(t0, t0, 32);
> +tcg_gen_or_i64(msa_wr_d[wd * 2], t1, t0);
Deposit, again.
r~
v8:
* Split into two patches
* Commit messages reworked
* Factor out blk_check_size_and_read_all(), fix error paths [László]
* Use error_setg_errno() [László]
* Don't use blk_name() for errors [Kevin] (*sigh*)
* Since this amounts to a complete rewrite of the first patch, take
authorship, so my m
We reject undersized backends with a rather enigmatic "failed to read
the initial flash content" error. For instance:
$ qemu-system-ppc64 -S -display none -M sam460ex -drive
if=pflash,format=raw,file=eins.img
qemu-system-ppc64: Initialization of device cfi.pflash02 failed: failed to
rea
On 3/18/19 9:52 PM, lizhengui wrote:
> This problem can be reproduced by detaching and attaching remote cdrom
> repeatly.
>
While a guest tries to access it, or not? do you have a scriptable test?
--js
> -邮件原件-
> 发件人: John Snow [mailto:js...@redhat.com]
> 发送时间: 2019年3月19日 7:34
> 收件
From: Alex Bennée
We disabled code to limit device sizes to 8, 16, 32 or 64MiB more than
a decade ago in commit 95d1f3edd5e and c8b153d7949, v0.9.1. Bury.
Signed-off-by: Alex Bennée
Reviewed-by: Laszlo Ersek
[Extracted from a larger patch, extended to pflash_cfi02.c]
Signed-off-by: Markus Arm
Aleksandar Markovic writes:
>> From: Alex Bennée
>> Subject: Re: [PATCH v3] target/mips: Fix minor bug in FPU
>>
>> Queued to fpu/next, thanks.
>
> Alex, does this mean for 4.0 or 4.1?
It's a bug fix so it will go in 4.0 I think.
--
Alex Bennée
On Mon 18 Mar 2019 04:25:10 PM CET, Vladimir Sementsov-Ogievskiy
wrote:
>> So what we have now is:
>>
>> A <- B <- C <- D <- E <- F <- G <- H <- I
>>
>> and we can launch four parallel block-stream jobs:
>>
>> From C (base) to A
>> From E (base) to C
>> From G (base) to E
>>
>
> are available in the Git repository at:
>
> https://xenbits.xen.org/git-http/people/aperard/qemu-dm.git
> tags/pull-xen-20190319
>
> for you to fetch changes up to 4158e93f4aced247c8db94a0275fc027da7dc97e:
>
> xen-mapcache: use MAP_FIXED flag so the mmap addre
On 3/19/19 5:24 AM, Vladimir Sementsov-Ogievskiy wrote:
> Job (especially mirror) may call block_job_error_action several
> times before actual pause if it has several in-flight requests.
>
> block_job_error_action will call job_pause more than once in this case,
> which lead to following block
On Tue, Mar 19, 2019 at 10:35:33PM +0800, Tao Xu wrote:
> On 3/19/2019 8:16 PM, Daniel P. Berrangé wrote:
> > The Cascadelake-Server CPU was added last year in
> >
> >commit c7a88b52f62b30c04158eeb07f73e3f72221b6a8
> >Author: Tao Xu
> >Date: Wed Sep 19 11:11:22 2018 +0800
> >
> >
Watch IDs are allocated from incrementing a int counter against
the QFileMonitor object. In very long life QEMU processes with
a huge amount of USB MTP activity creating & deleting directories
it is just about conceivable that the int counter can wrap
around. This would result in incorrect behaviou
> From: Alex Bennée
> Subject: Re: [PATCH v3] target/mips: Fix minor bug in FPU
>
> Queued to fpu/next, thanks.
Alex, does this mean for 4.0 or 4.1?
Aleksandar
Mateja Marjanovic writes:
> From: Mateja Marjanovic
>
> Wrong type of NaN was generated for IEEE 754-2008 by MADDF. and
> MSUBF. instructions when the arguments were (inf, zero, nan) or
> (zero, inf, nan).
> These instructions were tested and the results match with the results
> of the machine
From: Mateja Marjanovic
Eliminate loops for better performance.
Signed-off-by: Mateja Marjanovic
---
target/mips/msa_helper.c | 43 ++-
1 file changed, 30 insertions(+), 13 deletions(-)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
in
Paolo Bonzini writes:
> On 19/03/19 11:18, Alex Bennée wrote:
>>
>> Richard Henderson writes:
>>
>>> On 3/18/19 12:46 PM, Peter Maydell wrote:
Hi; for the M-profile floating point work I'm going to need I think
three new TB flags (to control whether to generate the code to do
th
We were trying to check whether bdrv_open_blockdev_ref() returned
success, but accidentally checked the wrong variable. Spotted by
Coverity (CID 1399703).
Signed-off-by: Kevin Wolf
Reviewed-by: Eric Blake
Reviewed-by: Stefano Garzarella
---
block/qcow2.c | 2 +-
1 file changed, 1 insertion(+),
On 3/19/19 8:06 AM, Paolo Bonzini wrote:
>> Given how many guests use the cs_base I wonder if it's time we came up
>> with a better name for it: extra_tb_state, extra_state, moar_bits...
>
> Or make the flags 64-bits by moving cs_base into the upper 32-bits of
> flags... This way 32-bit hosts do
From: Sergio Lopez
While child_job_drained_begin() calls to job_pause(), the job doesn't
actually transition between states until it runs again and reaches a
pause point. This means bdrv_drained_begin() may return with some jobs
using the node still having 'busy == true'.
As a consequence, block
232 is marked as generic, but commit 12efe428c9e added code that assumes
qcow2. What the new test really needs is backing files and support for
updating the backing file link (.bdrv_change_backing_file).
Split the non-generic code into a new test case 247 and make it work
with qed, too.
Signed-of
From: Sam Eiderman
Commit 509d39aa22909c0ed1aabf896865f19c81fb38a1 added support for read
only VMDKs of version 3.
This commit fixes the probe function to correctly handle descriptors of
version 3.
This commit has two effects:
1. We no longer need to supply '-f vmdk' when pointing to descri
From: Vladimir Sementsov-Ogievskiy
There no @device parameter, only the @id one.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Eric Blake
Signed-off-by: Kevin Wolf
---
qapi/block-core.json | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/qapi/block-co
From: Alberto Garcia
Signed-off-by: Alberto Garcia
Signed-off-by: Kevin Wolf
---
block/copy-on-read.c | 2 +-
block/crypto.c | 2 +-
block/replication.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/block/copy-on-read.c b/block/copy-on-read.c
index 64dcc424b5..d
From: Max Reitz
There is no reason why the constraints we put on @replaces should be
limited to drive-mirror. Therefore, move the sanity checks from
qmp_drive_mirror() to blockdev_mirror_common() so they apply to
blockdev-mirror as well.
Signed-off-by: Max Reitz
Reviewed-by: Eric Blake
Review
From: Sergio Lopez
There are various actions in this test that must be executed
sequentially, as the result of it depends on the state triggered by the
previous one.
If the last argument of _send_qemu_cmd() is an empty string, it just
sends the QMP commands without waiting for an answer. While u
Commit 18269069c310 ("migration: Introduce ignore-shared capability")
addes a ignore-shared capability to bypass the shared ramblock (e,g,
membackend + numa node). It does good to live migration.
This commit expected that QEMU doesn't write to guest RAM until
VM starts, but it does on aarch64 qe
From: Vladimir Sementsov-Ogievskiy
Job (especially mirror) may call block_job_error_action several
times before actual pause if it has several in-flight requests.
block_job_error_action will call job_pause more than once in this case,
which lead to following block-job-resume qmp command can't ac
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