OK. RX decoder works fine.
Since it is necessary to read additional bytes in the function
of the operand, we need to have DisasContext passed as an argument.
> %b2_li_2 18:2 !function=li
"li" read more extra byte. It use cpu_env in DisasContext.
Signed-off-by: Yoshinori Sato
---
scripts/d
Patchew URL:
https://patchew.org/QEMU/20190302062138.10713-1-ys...@users.sourceforge.jp/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190302062138.10713-1-ys...@users.sourceforge.jp
Subject: [Qemu-devel] [PATCH RFC
Signed-off-by: Yoshinori Sato
---
target/rx/Makefile.objs | 11 +
target/rx/gdbstub.c | 113
target/rx/monitor.c | 38
3 files changed, 162 insertions(+)
create mode 100644 target/rx/Makefile.objs
create mode 100644
Hello.
This patch series is added Renesas RX target emulation.
My git repository is bellow.
git://git.pf.osdn.net/gitroot/y/ys/ysato/qemu.git
Since my understanding is not enough,
I want many comments to make this a good one.
Thanks.
Changes v2
Rewrite translate. using decodetree.py
Yoshinori
Signed-off-by: Yoshinori Sato
---
MAINTAINERS | 20
1 file changed, 20 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 5040d9dfb1..141c4994b9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -270,6 +270,14 @@ F: include/hw/riscv/
F: linux-user/host/riscv32/
F: linu
rx62n - RX62N cpu.
rxqemu - QEMU virtual target.
Signed-off-by: Yoshinori Sato
---
hw/rx/Makefile.objs | 1 +
hw/rx/rx62n.c | 227 ++
hw/rx/rxqemu.c| 100 ++
include/hw/rx/rx.h| 7 ++
include/hw/rx/rx6
Signed-off-by: Yoshinori Sato
---
arch_init.c| 2 ++
configure | 8
default-configs/rx-softmmu.mak | 7 +++
include/sysemu/arch_init.h | 1 +
4 files changed, 18 insertions(+)
create mode 100644 default-configs/rx-softmmu.mak
diff --git
Signed-off-by: Yoshinori Sato
---
target/rx/cpu-qom.h | 52
target/rx/cpu.c | 224
target/rx/cpu.h | 214 +
3 files changed, 490 insertions(+)
create mode 100644 target/rx/c
This part only supported RXv1 instructions.
Instruction manual.
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01us0032ej0120_rxsm.pdf
Signed-off-by: Yoshinori Sato
---
target/rx/insns.decode | 336
target/rx/translate.c | 2220 +++
renesas_tmr: 8bit timer modules.
renesas_cmt: 16bit compare match timer modules.
This part use many renesas's CPU.
Hardware manual.
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf?key=086621e01bd70347c18ea7f794aa9cc3
Signed-off-by: Yoshinori Sato
---
hw/
This implementation supported only ICUa.
Hardware manual.
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf?key=086621e01bd70347c18ea7f794aa9cc3
Signed-off-by: Yoshinori Sato
---
hw/intc/Makefile.objs| 1 +
hw/intc/rx_icu.c | 323
Signed-off-by: Yoshinori Sato
---
target/rx/helper.c| 252 +
target/rx/helper.h| 39
target/rx/op_helper.c | 602 ++
3 files changed, 893 insertions(+)
create mode 100644 target/rx/helper.c
create mode 100644 targ
Signed-off-by: Yoshinori Sato
---
include/disas/bfd.h |5 +
target/rx/disas.c | 1570 +++
2 files changed, 1575 insertions(+)
create mode 100644 target/rx/disas.c
diff --git a/include/disas/bfd.h b/include/disas/bfd.h
index 41b61c85f9..b2c34
This module supported only non FIFO type.
Hardware manual.
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf?key=086621e01bd70347c18ea7f794aa9cc3
Signed-off-by: Yoshinori Sato
---
hw/char/Makefile.objs | 2 +-
hw/char/renesas_sci.c | 288
I've got this issue too on windows 10 with QEMU emulator version 3.1.0
(Debian 1:3.1+dfsg-4). It seems to only occur when the device isn't used
in the windows host for a while by any application. If an application
opens the capture device, the delay slowly gets smaller until it's only
a 4th of a se
Proofread your comments, guys... oops
So it's a debian HOST and windows GUEST, not windows host. :-l
Sorry for the double post.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1492649
Title:
QEMU s
Signed-off-by: Samuel Thibault
---
slirp/tcp_subr.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/slirp/tcp_subr.c b/slirp/tcp_subr.c
index ef9d99c154..1d7e72dca7 100644
--- a/slirp/tcp_subr.c
+++ b/slirp/tcp_subr.c
@@ -660,10 +660,12 @@ tcp_emu(struct socket *so, struct
William Bowling, le ven. 01 mars 2019 21:45:56 +, a ecrit:
> When emulating ident in tcp_emu, if the strchr checks passed but the
> sscanf check failed, two uninitialized variables would be copied and
> sent in the reply.
>
> Signed-off-by: William Bowling
Applied to my tree, thanks!
> ---
Patchew URL:
https://patchew.org/QEMU/20190222024106.9167-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190222024106.9167-1-richard.hender...@linaro.org
Subject: [Qemu-devel] [PATCH v
When emulating ident in tcp_emu, if the strchr checks passed but the
sscanf check failed, two uninitialized variables would be copied and
sent in the reply.
Signed-off-by: William Bowling
---
slirp/tcp_subr.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/slirp/
On Thu, Feb 21, 2019 at 18:41:03 -0800, Richard Henderson wrote:
> Changes since v2:
> * Do not cache VECLEN, VECSTRIDE, VFPEN.
> These variables come from VFP_FPSCR and VFP_FPEXC, not from
> system control registers.
> * Move HANDLER and STACKCHECK to rebuild_hflags_a32,
> instead
Vic Lee, le ven. 01 mars 2019 14:48:09 +0800, a ecrit:
> Sometimes sorecvfrom() is called from slirp.c because revents == G_IO_IN,
> but there is 0 bytes available and recvfrom could be blocking indefinitely.
> This is likely due to 0-length udp payload. This also adds an error
> checking for ioctl
Peter Maydell, le ven. 01 mars 2019 09:49:26 +, a ecrit:
> On Fri, 1 Mar 2019 at 09:39, Greg Kurz wrote:
> >
> > Build fails with gcc 9:
> >
> > CC slirp/ndp_table.o
> > slirp/ndp_table.c: In function ‘ndp_table_add’:
> > slirp/ndp_table.c:31:23: error: taking address of packed member o
Quoting Greg Kurz (2019-03-01 13:32:37)
> The RTAS event hotplug code for machine types 2.8 and newer depends on
> the CAS negotiated ov5 in order to work properly. However, there's no
> CAS when running under qtest. There has been a tentative to trick the
> code by faking the OV5_HP_EVT bit, but i
From: Bastian Koppelmann
only one translate functions of rvc needs to handle special cases. For
the other rvc insns we can remove the extra layer of indirection.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn16.decode
From: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn_trans/trans_rvm.inc.c | 55 ++--
target/riscv/translate.c| 320 ++--
2 files changed, 1
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode | 28 ++
target/riscv/insn_trans/trans_rvd.inc.c | 360 ++
From: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn16.decode | 31
target/riscv/insn_trans/trans_rvc.inc.c | 101
target/riscv/t
From: Bastian Koppelmann
With decodetree we don't need to convert RISC-V opcodes into to MemOps
as the old gen_load() did.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn_trans/trans_rvi.inc.c | 3
From: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn_trans/trans_rvi.inc.c | 93 +
target/riscv/translate.c| 59 +---
2 files
From: Bastian Koppelmann
decodetree handles all instructions now so the fallback is not necessary
anymore.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/translate.c | 21 +
1 file
From: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn16.decode | 20 ++--
target/riscv/insn32.decode | 3 ++-
target/riscv/insn_trans/trans_rvc.inc.c | 24 ---
From: Bastian Koppelmann
it splices flwsp_ldsp, fswsp_sdsp, and jal_addiw and makes each of them
reuse the code generator used for the non compressed insns.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn16-32.decode
From: Bastian Koppelmann
this finally removes the old decoder functions that we carried along
with it.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Palmer Dabbelt
---
target/riscv/Makefile.objs | 1 +
target/riscv/insn16-32.decode |
From: Bastian Koppelmann
These all expand simply to R format instructions.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Palmer Dabbelt
---
target/riscv/Makefile.objs | 10 +++---
target/riscv/insn16-64.decode | 24 ++
targ
From: Bastian Koppelmann
trans_jalr() is the only caller, so move the code into trans_jalr().
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn_trans/trans_rvi.inc.c | 28
From: Bastian Koppelmann
with all 16 bit insns moved to decodetree no path is falling back to
gen_system(), so we can remove it.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/translate.c | 34 ---
From: Bastian Koppelmann
With decodetree we don't need to convert RISC-V opcodes into to MemOps
as the old gen_store() did.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn_trans/trans_rvi.inc.c |
From: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn_trans/trans_rvi.inc.c | 18 +-
target/riscv/insn_trans/trans_rvm.inc.c | 14 +++---
target/riscv/translate.c|
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode| 15 +++
.../riscv/insn_trans/trans_privileged.inc.c | 110 +
Patchew URL:
https://patchew.org/QEMU/1551466776-29123-1-git-send-email-jjhe...@linux.ibm.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1551466776-29123-1-git-send-email-jjhe...@linux.ibm.com
Subject: [Qemu-devel
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32-64.decode | 8 +
target/riscv/insn_trans/trans_rvd.inc.c | 82
target/riscv/
From: Bastian Koppelmann
manual decoding in gen_arith() is not necessary with decodetree. For now
the function is called trans_arith as the original gen_arith still
exists. The former will be renamed to gen_arith as soon as the old
gen_arith can be removed.
Reviewed-by: Richard Henderson
Signed
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32-64.decode | 6 +++
target/riscv/insn_trans/trans_rvf.inc.c | 60 +++
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode | 35 +++
target/riscv/insn_trans/trans_rvf.inc.c | 379 +
From: Bastian Koppelmann
gen_arith_imm() does a lot of decoding manually, which was hard to read
in case of the shift instructions and is not necessary anymore with
decodetree.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dab
From: Bastian Koppelmann
We now utilizes argument-sets of decodetree such that no manual
decoding is necessary.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn_trans/trans_rvi.inc.c | 46 +
From: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/Makefile.objs | 9 ++-
target/riscv/insn16.decode | 55 ++
target/riscv/insn_trans/tra
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32-64.decode | 7 ++
target/riscv/insn32.decode | 10 +++
target/riscv/
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32-64.decode | 13 +++
target/riscv/insn_trans/trans_rva.inc.c | 58 ++
targe
From: Bastian Koppelmann
this splits the 64-bit only instructions into its own decode file such
that we generate the decoder for these instructions only for the RISC-V
64 bit target.
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Pee
From: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn16.decode | 43 +++
target/riscv/insn_trans/trans_rvc.inc.c | 151
target/riscv/tr
From: Bastian Koppelmann
for now only LUI & AUIPC are decoded and translated. If decodetree fails, we
fall back to the old decoder.
Reviewed-by: Richard Henderson
Acked-by: Alistair Francis
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode | 17 +++
target/riscv/insn_trans/trans_rva.inc.c | 160 +
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvi.inc.c | 79 +++
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvi.inc.c | 19 +++
merged tag 'i2c-for-release-20190228'
Primary key fingerprint: FD0D 5CE6 7CE0 F59A 6688 2686 61F3 8C90 919B FF81
The following changes since commit 20b084c4b1401b7f8fbc385649d48c67b6f43d44:
Merge remote-tracking branch 'remotes/cminyard/tags/i2c-for-release-20190228'
into staging (2019-03-01 1
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode | 10 ++
target/riscv/insn_trans/trans_rvi.inc.c | 48
From: Bastian Koppelmann
we cannot remove the call to gen_arith() in decode_RV32_64G() since it
is used to translate multiply instructions.
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode | 19 ++
target/riscv/insn_trans/tran
Patchew URL:
https://patchew.org/QEMU/1551466776-29123-1-git-send-email-jjhe...@linux.ibm.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1551466776-29123-1-git-send-email-jjhe...@linux.ibm.com
Subject: [Qemu-devel
Patchew URL:
https://patchew.org/QEMU/1551466776-29123-1-git-send-email-jjhe...@linux.ibm.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1551466776-29123-1-git-send-email-jjhe...@linux.ibm.com
Subject: [Qemu-devel
Patchew URL:
https://patchew.org/QEMU/1551466776-29123-1-git-send-email-jjhe...@linux.ibm.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1551466776-29123-1-git-send-email-jjhe...@linux.ibm.com
Subject: [Qemu-devel
Patchew URL:
https://patchew.org/QEMU/1551466776-29123-1-git-send-email-jjhe...@linux.ibm.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1551466776-29123-1-git-send-email-jjhe...@linux.ibm.com
Subject: [Qemu-devel
Patchew URL:
https://patchew.org/QEMU/1551466776-29123-1-git-send-email-jjhe...@linux.ibm.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1551466776-29123-1-git-send-email-jjhe...@linux.ibm.com
Subject: [Qemu-devel
Patchew URL: https://patchew.org/QEMU/20190301115413.27153-1-da...@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190301115413.27153-1-da...@redhat.com
Subject: [Qemu-devel] [PATCH v2 00/32] s390x/tcg: Vec
Greg Kurz writes:
...
>>
>> I think there's an underlying problem with this code which we
>> should deal with differently. The 'dataset' local in this
>> file is (I think) pointing at on-the-wire information from
>> the USB device, but we're treating it as an array of
>> host-order uint16_t value
Found by inspection: Rn is the base register against which the
load began; I is the register within the mask being processed.
The exception return should of course be procesed from the loaded PC.
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 2 +-
1 file changed, 1 insertion(+),
On 3/1/19 5:47 AM, Eric Auger wrote:
> From: Shameer Kolothum
>
> We introduce an helper to create a memory node.
>
> Signed-off-by: Eric Auger
> Signed-off-by: Shameer Kolothum
> Reviewed-by: Igor Mammedov
>
> ---
> v7 -> v8:
> - Added Igor's R-b
>
> v6 -> v7:
> - msg error in the caller
>
On 3/1/19 2:03 AM, Alex Bennée wrote:
> I know Richard's is right because I asked him in the pub. I'm guessing
> Fredrik's based on the fact I vaguely remember an Atari demo. The
> others I attributed to academic institutions last time I posted so
> have moved them to individuals as requested.
>
>
On 3/1/19 2:03 PM, Eric Blake wrote:
> On 3/1/19 1:57 PM, John Snow wrote:
>
+if ((flags & BDRV_BITMAP_BUSY) && bdrv_dirty_bitmap_busy(bitmap)) {
+error_setg(errp, "Bitmap '%s' is currently in use by another"
+ " operation and cannot be used", bitmap->n
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 13 ++-
target/arm/cpu.c| 1 +
target/arm/cpu64.c | 2 ++
target/arm/helper.c | 55 +
4 files changed, 70 insertions(+), 1 deletion(-)
diff --git a/target/arm/cpu.h b/target/arm/
On 3/1/19 2:57 PM, Eric Blake wrote:
> On 3/1/19 1:48 PM, John Snow wrote:
>
>>> I understand forbidding inconsistent sources (because if the source is
>>> potentially missing bits, then the merge destination will also be
>>> missing bits and thus be inconsistent), but why forbid busy? If I've
The EL0+UMA check is unique to DAIF. While SPSel had avoided the
check by nature of already checking EL >= 1, the other post v8.0
extensions to MSR (imm) allow EL0 and do not require UMA. Avoid
the unconditional write to pc and use raise_exception_ra to unwind.
Signed-off-by: Richard Henderson
Tested-by: Laurent Desnogues
Signed-off-by: Richard Henderson
---
v2: Update ID_AA64ISAR0.TS.
---
target/arm/cpu.h | 5
target/arm/cpu64.c | 2 +-
target/arm/translate-a64.c | 58 ++
3 files changed, 64 insertions(+), 1 deletion(-)
di
Tested-by: Laurent Desnogues
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 5 ++
target/arm/helper.h| 5 ++
target/arm/cpu64.c | 1 +
target/arm/translate-a64.c | 71 ++--
target/arm/vfp_helper.c| 96 +
This decoding more closely matches the ARMv8.4 Table C4-6,
Encoding table for Data Processing - Register Group.
In particular, op2 == 0 is now more than just Add/sub (with carry).
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 98 ++
1 file
This will allow sharing code that adjusts rmode beyond
the existing users.
Tested-by: Laurent Desnogues
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 90 +-
1 file changed, 49 insertions(+), 41 deletions(-)
diff --git a/target/arm/transla
Minimize the number of places that will need updating when
the virtual host extensions are added.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 26 --
target/arm/helper.c | 8 ++--
2 files changed, 18 insertions(+), 16 deletions(-)
diff --git a/target/a
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 10 ++
linux-user/elfload.c | 1 +
target/arm/cpu.c | 1 +
target/arm/cpu64.c | 2 ++
target/arm/translate-a64.c | 14 ++
target/arm/translate.c | 22 ++
6 file
Tested-by: Laurent Desnogues
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 5 ++
linux-user/elfload.c | 1 +
target/arm/cpu64.c | 1 +
target/arm/translate-a64.c | 97 +-
4 files changed, 103 insertions(+), 1 deletion(-)
d
These 5 extensions are small, and all previous editions have
minor patch conflicts with master. Therefore, rebase them all
together for simplicity.
r~
Richard Henderson (10):
target/arm: Split out arm_sctlr
target/arm: Implement ARMv8.0-SB
target/arm: Implement ARMv8.0-PredInv
target/a
We do not need an out-of-line helper for manipulating bits in pstate.
While changing things, share the implementation of gen_ss_advance.
Signed-off-by: Richard Henderson
---
v3: Assert no manual change to CACHED_PSTATE_BITS,
merged in from a previously separate patch.
---
target/arm/helper.h
On 3/1/19 1:57 PM, John Snow wrote:
>>> +if ((flags & BDRV_BITMAP_BUSY) && bdrv_dirty_bitmap_busy(bitmap)) {
>>> +error_setg(errp, "Bitmap '%s' is currently in use by another"
>>> + " operation and cannot be used", bitmap->name);
>>
>> Split before space,
>>
>>> +
On 3/1/19 2:36 PM, Eric Blake wrote:
> On 3/1/19 1:15 PM, John Snow wrote:
>> Instead of checking against busy, inconsistent, or read only directly,
>> use a check function with permissions bits that let us streamline the
>> checks without reproducing them in many places.
>>
>> Included in this
On 3/1/19 1:48 PM, John Snow wrote:
>> I understand forbidding inconsistent sources (because if the source is
>> potentially missing bits, then the merge destination will also be
>> missing bits and thus be inconsistent), but why forbid busy? If I've
>> associated a bitmap with an NBD server (mak
On 2/28/19 9:41 AM, Thomas Huth wrote:
> Ok ... shall I resend the PULL request or could you maybe send a
> follow-up patch later?
The pr has been merged, so I'll do it later.
r~
On 3/1/19 1:15 PM, John Snow wrote:
> Set the inconsistent bit on load instead of rejecting such bitmaps.
> There is no way to un-set it; the only option is to delete it.
>
> Obvervations:
> - bitmap loading does not need to update the header for in_use bitmaps.
> - inconsistent bitmaps don't need
>From 3c1cba63dc5070ab559a126e206557f27fbaea59 Mon Sep 17 00:00:00 2001
From: Aarushi Mehta
Date: Sat, 2 Mar 2019 01:11:42 +0530
Subject: [PATCH v4] thunk: fix of malloc to g_new
Note that since thunking occurs throughout the lifetime of the QEMU
instance, there is no matching 'free' to correct.
On 3/1/19 2:44 PM, Eric Blake wrote:
> On 3/1/19 1:15 PM, John Snow wrote:
>> We didn't do any state checking on source bitmaps at all,
>> so this adds inconsistent and busy checks. readonly is
>> allowed, so you can still copy a readonly bitmap to a new
>> destination to use it for operations l
On 3/1/19 1:15 PM, John Snow wrote:
> We didn't do any state checking on source bitmaps at all,
> so this adds inconsistent and busy checks. readonly is
> allowed, so you can still copy a readonly bitmap to a new
> destination to use it for operations like drive-backup.
>
> Signed-off-by: John Sno
On 3/1/19 2:32 PM, Eric Blake wrote:
> On 3/1/19 1:15 PM, John Snow wrote:
>> Add an inconsistent bit to dirty-bitmaps that allows us to report a bitmap as
>> persistent but potentially inconsistent, i.e. if we find bitmaps on a qcow2
>> that have been marked as "in use".
>>
>> Signed-off-by: Jo
On 3/1/19 1:15 PM, John Snow wrote:
> drive and blockdev backup cannot use readonly bitmaps, because the
> sync=incremental mechanism actually edits the bitmaps on success.
>
> If you really want to do this operation, use a copied bitmap.
In fact, that's what I ended up doing in my libvirt patche
On 3/1/19 1:15 PM, John Snow wrote:
> Remove is an inherently RW operation, so this will fail anyway, but
> we can fail it very quickly instead of trying and failing, so do so.
>
> Signed-off-by: John Snow
> ---
> blockdev.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
Reviewed-by:
On 3/1/19 1:15 PM, John Snow wrote:
> Instead of checking against busy, inconsistent, or read only directly,
> use a check function with permissions bits that let us streamline the
> checks without reproducing them in many places.
>
> Included in this patch are permissions changes that simply add
The RTAS event hotplug code for machine types 2.8 and newer depends on
the CAS negotiated ov5 in order to work properly. However, there's no
CAS when running under qtest. There has been a tentative to trick the
code by faking the OV5_HP_EVT bit, but it turned out to break other
assumptions in the c
On 3/1/19 1:15 PM, John Snow wrote:
> Add an inconsistent bit to dirty-bitmaps that allows us to report a bitmap as
> persistent but potentially inconsistent, i.e. if we find bitmaps on a qcow2
> that have been marked as "in use".
>
> Signed-off-by: John Snow
> ---
> qapi/block-core.json
Allow QEMU to read in bitmaps that have the in-use bit set, for the
purposes of allowing users to delete those bitmaps.
This is chosen in preference to a hard error on load to minimize
impact for a non-critical error, but to force the user or management
utility to acknowledge that the bitmap is no
Commit b8165118f52c broke CPU hotplug tests for old machine types:
$ QTEST_QEMU_BINARY=ppc64-softmmu/qemu-system-ppc64 ./tests/cpu-plug-test
-m=slow
/ppc64/cpu-plug/pseries-3.1/device-add/2x3x1&maxcpus=6: OK
/ppc64/cpu-plug/pseries-2.12-sxxm/device-add/2x3x1&maxcpus=6: OK
/ppc64/cpu-plug/pseries-
From: Aleksandar Markovic
Add tests for MIPS64R6 bit swap instructions.
Signed-off-by: Aleksandar Markovic
---
.../isa/mips64r6/bit-swap/test_mips64r6_bitswap.c | 144 +
.../isa/mips64r6/bit-swap/test_mips64r6_dbitswap.c | 144 +
2 files changed, 288 in
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