Commit 376692b9dc6(cpus: protect work list with work_mutex)
initialize a work_mutex in cpu_common_initfn, however forget
to destroy it. This will cause resource leak when hotunplug cpu
or hotplug cpu fails.
Signed-off-by: Li Qiang
---
qom/cpu.c | 3 +++
1 file changed, 3 insertions(+)
diff --gi
On Sun, Dec 23, 2018 at 11:15:24AM +, Mark Cave-Ayland wrote:
> The VSX register array is a block of 64 128-bit registers where the first 32
> registers consist of the existing 64-bit FP registers extended to 128-bit
> using new VSR registers, and the last 32 registers are the VMX 128-bit
> reg
Depending on the interrupt mode of the machine, enable or disable the
XIVE MMIOs.
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/spapr_xive.h | 1 +
hw/intc/spapr_xive.c| 9 +
hw/ppc/spapr_irq.c | 9 +
3 files changed, 19 insertions(+)
diff --git a/include/h
The qemu_irq array is now allocated at the machine level using a sPAPR
IRQ set_irq handler depending on the chosen interrupt mode. The use of
this handler is slightly inefficient today but it will become necessary
when the 'dual' interrupt mode is introduced.
Signed-off-by: Cédric Le Goater
---
Future changes of the ICSState object will remove the qemu_irq array
from under the interrupt controller model. Prepare ground for the PSI
interrupt sources and introduce a new one directly under the PSI
device model.
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/pnv_psi.h | 1 +
hw/ppc/pnv
The 'dual' sPAPR IRQ backend supports both interrupt mode, XIVE
exploitation mode and the legacy compatibility mode (XICS). both modes
are not supported at the same time.
The machine starts with the legacy mode and a new interrupt mode can
then be negotiated by the CAS process. In this case, the n
Now that the 'intc' pointer is only used by the XICS interrupt mode,
let's make things clear and use a XICS type and name.
Signed-off-by: Cédric Le Goater
---
target/ppc/cpu.h| 3 ++-
hw/intc/xics_spapr.c| 10 +-
hw/ppc/pnv.c| 6 +++---
hw/ppc/pnv_core.c |
To support the 'dual' interrupt mode, XICS and XIVE, we plan to move
the qemu_irq array of each interrupt controller under the machine and
do the allocation under the sPAPR IRQ init method.
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/xics.h | 2 ++
include/hw/ppc/xive.h | 2 ++
hw/intc/xi
which will be used by the machine only when the XIVE interrupt mode is
in use.
Signed-off-by: Cédric Le Goater
---
target/ppc/cpu.h| 2 ++
hw/intc/xive.c | 6 +++---
hw/ppc/spapr_cpu_core.c | 7 ++-
hw/ppc/spapr_irq.c | 8
4 files changed, 15 insertions(+), 8 d
commit 15ed653fa49a ("ppc/xics: An ICS with offset 0 is assumed to be
uninitialized") introduced an extra check on the ICS offset which is
not strictly necessary.
Revert the change to be able to map the XICS IRQ number space on the
XIVE IRQ number space.
Signed-off-by: Cédric Le Goater
---
incl
The qirq routines of the XiveSource and the sPAPRXive model are only
used under the sPAPR IRQ backend. Simplify the overall call stack and
gather all the code under spapr_qirq_xive(). It will ease future
changes.
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/spapr_xive.h | 1 -
include/hw/
Hello,
This series adds a new sPAPR IRQ backend called 'dual' which supports
both interrupt mode, the XIVE native exploitation mode and the legacy
compatibility mode (XICS).
The machine operates with the legacy mode by default and lets CAS
negotiate a new interrupt mode. If a new mode is selected
Today, the interrupt presenter is linked to a CPU using the
cpu_intc_create() method of the sPAPR IRQ backend. The resulting
object is assigned to the PowerPCCPU 'intc' pointer whatever the
interrupt mode, XICS or XIVE.
To support the 'dual' interrupt mode, we will need to distinguish
between the
This option controls will mmap the memory backend file with MAP_SYNC flag,
which can ensure filesystem metadata consistent even after a system crash
or power failure, if MAP_SYNC flag is supported by the host kernel(Linux
kernel 4.15 and later) and the backend is a file supporting DAX (e.g.,
file o
As more flag parameters besides the existing 'shared' are going to be
added to qemu_ram_mmap(), let's switch 'shared' to a 'flags' parameter
in advance, so as to ease the further additions.
Signed-off-by: Haozhong Zhang
Signed-off-by: Zhang Yi
---
exec.c| 7 ---
include
When a file supporting DAX is used as vNVDIMM backend, mmap it with
MAP_SYNC flag in addition which can ensure file system metadata
synced in each guest writes to the backend file, without other QEMU
actions (e.g., periodic fsync() by QEMU).
Signed-off-by: Haozhong Zhang
Signed-off-by: Zhang Yi
When there are multiple memory backends in use, including the object type
name, ID and the property name in the error message can help users to
locate the error.
Signed-off-by: Haozhong Zhang
Signed-off-by: Zhang Yi
---
backends/hostmem-file.c | 6 --
backends/hostmem.c | 8 +---
2
object_get_canonical_path_component() returns a string which
must be freed using g_free().
Signed-off-by: Zhang Yi
Reviewed-by: Pankaj gupta
Reviewed-by: Igor Mammedov
---
numa.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/numa.c b/numa.c
index 50ec016..3875e1e 100644
--- a/numa.c
+++
Linux 4.15 introduces a new mmap flag MAP_SYNC, which can be used to
guarantee the write persistence to mmap'ed files supporting DAX (e.g.,
files on ext4/xfs file system mounted with '-o dax').
A description of MAP_SYNC and MAP_SHARED_VALIDATE can be found at
https://patchwork.kernel.org/patch
On Thu, Dec 13, 2018 at 10:00:53PM +0100, Juan Quintela wrote:
> Reviewed-by: Thomas Huth
> Reviewed-by: Laurent Vivier
> Signed-off-by: Juan Quintela
> ---
> hw/virtio/Makefile.objs| 1 +
> hw/virtio/virtio-net-pci.c | 96 ++
> hw/virtio/virtio-pci.c
On Wed, Jan 02, 2019 at 03:06:38AM +0100, BALATON Zoltan wrote:
> Debug logs were left enabled in ppc4xx_devs.c whereas in other files
> these are normally not enabled. Disable it here as well.
>
> Signed-off-by: BALATON Zoltan
Applied, thanks.
> ---
> hw/ppc/ppc4xx_devs.c | 3 +--
> 1 file ch
On Wed, Jan 02, 2019 at 03:06:38AM +0100, BALATON Zoltan wrote:
> The sm501 model belonged to SH before but that seems to be inactive
> now and latest changes were for sam460ex which is the more active user
> of this device at the moment so let's adopt sm501 for sam460ex.
>
> Also add device tree
On Wed, Jan 02, 2019 at 03:06:38AM +0100, BALATON Zoltan wrote:
> There's already a struct with the same name in ppc4xx_devs.c. They are
> not used outside their files so don't clash but they are also not
> identical so rename the ppc440 specific one to distinguish them.
>
> Signed-off-by: BALATON
On Wed, Jan 02, 2019 at 03:06:38AM +0100, BALATON Zoltan wrote:
> Get rid of code from MIPS Malta board used to create SPD EEPROM data
> (parts of which was not even needed for sam460ex) and use the generic
> spd_data_generate() function to simplify this.
>
> Signed-off-by: BALATON Zoltan
> ---
>
On Wed, Jan 02, 2019 at 03:06:38AM +0100, BALATON Zoltan wrote:
> There are several boards with SPD EEPROMs that are now using
> duplicated or slightly different hard coded data. Add a helper to
> generate SPD data for a memory module of given type and size that
> could be used by these boards (eit
On Wed, Jan 02, 2019 at 03:06:38AM +0100, BALATON Zoltan wrote:
> To avoid overflow if larger values are added later use ram_addr_t for
> the sdram_bank_sizes parameter to match ram_size to which it is
> compared.
So, technically I think these should be 'hwaddr' (which represents a
guest physical
On Wed, Jan 02, 2019 at 03:06:38AM +0100, BALATON Zoltan wrote:
> The sdram_set_bcr() function in ppc440_uc.c takes a pointer into an
> array then calculates its index from that. It's simpler and easier to
> just pass the index which simplifies both the function and its callers.
>
> Signed-off-by:
On Wed, Dec 19, 2018 at 05:35:41PM +0100, Laurent Vivier wrote:
> H_HOME_NODE_ASSOCIATIVITY H-Call returns the associativity domain
> designation associated with the identifier input parameter
>
> This fixes a crash when we try to hotplug a CPU in memory-less and
> CPU-less numa node. In this case
On Tue, Dec 25, 2018 at 10:04:43PM +0800, Fei Li wrote:
> Add a local_err to hold the error, and return the corresponding
> error code to replace the temporary &error_abort.
>
> Cc: Markus Armbruster
> Cc: David Gibson
> Signed-off-by: Fei Li
This looks like a good change, but it no longer app
On Fri, Dec 21, 2018 at 03:39:24PM -0200, Murilo Opsfelder Araujo wrote:
> On Fri, Dec 21, 2018 at 01:34:48AM +0100, Greg Kurz wrote:
> > From: Alexey Kardashevskiy
> >
> > SLOF receives a device tree and updates it with various properties
> > before switching to the guest kernel and QEMU is not a
On Fri, Dec 28, 2018 at 01:52:27PM +, Mark Cave-Ayland wrote:
> >From working on the TCG vector operations patchset, it is apparent that there
> are a large number of endian-based hacks in int_helper.c which can be removed
> by
> making use of the various Vsr* macros.
>
> Patch 1 is simple en
On Sun, Dec 23, 2018 at 11:15:16AM +, Mark Cave-Ayland wrote:
> This patchset is an attempt at trying to improve the VMX (Altivec) instruction
> performance by laying the groundwork for use of the new TCG vector operations.
>
> Patches 1 and 2 fix a sign-extension error discovered in EXTRACT_S
On Fri, Dec 28, 2018 at 01:52:28PM +, Mark Cave-Ayland wrote:
> This prepares us for eliminating the use of direct array access within the VMX
> instruction implementations.
>
> Signed-off-by: Mark Cave-Ayland
> Reviewed-by: Richard Henderson
Applied to ppc-for-4.0, thanks.
> ---
> target
There are several boards with SPD EEPROMs that are now using
duplicated or slightly different hard coded data. Add a helper to
generate SPD data for a memory module of given type and size that
could be used by these boards (either as is or with further changes if
needed) which should help cleaning
To avoid overflow if larger values are added later use ram_addr_t for
the sdram_bank_sizes parameter to match ram_size to which it is compared.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_bamboo.c | 2 +-
hw/ppc/ppc4xx_devs.c| 4 ++--
hw/ppc/sam460ex.c | 2 +-
include/hw/ppc/ppc4x
The sdram_set_bcr() function in ppc440_uc.c takes a pointer into an
array then calculates its index from that. It's simpler and easier to
just pass the index which simplifies both the function and its callers.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_uc.c | 36
Get rid of code from MIPS Malta board used to create SPD EEPROM data
(parts of which was not even needed for sam460ex) and use the generic
spd_data_generate() function to simplify this.
Signed-off-by: BALATON Zoltan
---
hw/ppc/sam460ex.c | 169 ++--
Debug logs were left enabled in ppc4xx_devs.c whereas in other files
these are normally not enabled. Disable it here as well.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc4xx_devs.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
i
Fix the encoding of larger memory modules in the SoC registers which
allows specifying more than 1GB memory for sam460ex. Well, only 2GB
due to SoC and firmware restrictions which was the only missing value
compared to what the real hardware supports. The SoC should support up
to 4GB but when setti
The sm501 model belonged to SH before but that seems to be inactive
now and latest changes were for sam460ex which is the more active user
of this device at the moment so let's adopt sm501 for sam460ex.
Also add device tree and firmware sources and binaries.
Signed-off-by: BALATON Zoltan
---
MA
There's already a struct with the same name in ppc4xx_devs.c. They are
not used outside their files so don't clash but they are also not
identical so rename the ppc440 specific one to distinguish them.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_uc.c | 16
1 file changed, 8
The last code patch in this series fixes memory size larger than 1GB
for sam460ex, other patches are just clean ups I've made along the way.
The first patch is intended to be generic and may be useful for other
boards which currently have their own SPD EEPROM data or don't yet
generate any SPD dat
On Wed, 19 Dec 2018 10:29:41 +0100
Markus Armbruster wrote:
> David Gibson writes:
>
> [...]
> [...]
> [...]
> [...]
> [...]
> [...]
> [...]
> [...]
>
> Double-checking: is it okay to report some failures of this function
> (one of two H_RESOURCE failures, to be precise
baiyao...@cmss.chinamobile.com
Bcc:
Subject: Re: [Qemu-devel] [PATCH] tcmu: Introduce qemu-tcmu utility
Reply-To: baiyao...@cmss.chinamobile.com
In-Reply-To: <20190102015321.GA26514@byw>
Add Xiubo.
On Wed, Jan 02, 2019 at 09:53:21AM +0800, Yaowei Bai wrote:
> Ping.
>
> BTW, it should be update
Ping.
BTW, it should be update docker image to install glib to fix this.
On Wed, Dec 26, 2018 at 12:19:48AM -0800, no-re...@patchew.org wrote:
> Patchew URL:
> https://patchew.org/QEMU/1545387387-9613-1-git-send-email-baiyao...@cmss.chinamobile.com/
>
>
>
> Hi,
>
> This series seems to have
> > On 25/12/18 09:23, Kang, Luwei wrote:
> > >> From: Qemu-devel
> > >> [mailto:qemu-devel-bounces+luwei.kang=intel@nongnu.org] On
> > >> Behalf Of Paolo Bonzini
> > >> Sent: Friday, December 21, 2018 8:44 PM
> > >> To: qemu-devel@nongnu.org
> > >> Cc: ehabk...@redhat.com; qemu-sta...@nongnu.o
> On Dec 20, 2018, at 19:20, Philippe Mathieu-Daudé wrote:
>
> Hi Fam,
>
> On 11/2/18 8:24 AM, Fam Zheng wrote:
>> On Fri, Nov 2, 2018 at 3:20 PM Philippe Mathieu-Daudé
>> wrote:
>>>
>>> Hi Fam,
>>>
>>> Thanks for picking this.
>>>
>>> On Fri, Nov 2, 2018 at 7:48 AM Fam Zheng wrote:
>>>
Hi Eduardo/Paolo,
Do you have any comments about these patches?
Thanks
Tao
On 12/27/18 10:43 AM, Tao Xu wrote:
These patches update the stepping and add some MSR based features
enumerated by ARCH_CAPABILITIES on Cascadelake-Server CPU model.
Tao Xu (2):
i386: Update stepping of Cascadelake
Hi Eduardo/Paolo,
Do you have any comments about these patches ?
Thanks
Tao
On 12/27/18 10:43 AM, Tao Xu wrote:
These patches update the stepping and add some MSR based features
enumerated by ARCH_CAPABILITIES on Cascadelake-Server CPU model.
Tao Xu (2):
i386: Update stepping of Cascadelak
> On Dec 30, 2018, at 08:09, Philippe Mathieu-Daudé wrote:
>
> Hi,
>
> I think patchew is having some trouble since at least 1 week:
> new series aren't added.
Thanks for the reminder, Phil. I fixed https on patches.org but forgot to
switch the importer back from http. Now it’s back to work
> On 25/12/18 09:23, Kang, Luwei wrote:
> >> From: Qemu-devel
> >> [mailto:qemu-devel-bounces+luwei.kang=intel@nongnu.org] On Behalf
> >> Of Paolo Bonzini
> >> Sent: Friday, December 21, 2018 8:44 PM
> >> To: qemu-devel@nongnu.org
> >> Cc: ehabk...@redhat.com; qemu-sta...@nongnu.org
> >> Subjec
Hi Aleksandar,
On 12/27/18 2:12 PM, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> New directory organization is as follows:
>
> tests
> tcg
> mips
> user
> isa
> r5900
> ase
> dsp
> system
> ase
> dsp
>
> New fil
Thanks Aleksandar!
> > From: Fredrik Noring
> > Subject: [PATCH v2 09/12] tests/tcg/mips: Test R5900 three-operand MADDU1
>
> Reviewed-by: Aleksandar Markovic
>
> This patch is selected for integration in the next MIPS pull request
> scheduled shortly.
>
> THANKS FOR ALL EFFORTS!
Is this a
> On Jan 1, 2019, at 7:27 AM, Zoltán Kővágó wrote:
>
> On 2019-01-01 05:24, Programmingkid wrote:
>>> On 2018-12-29 01:49, Programmingkid wrote:
> [snip]
I tried ac97 with a Windows 2000 guest in qemu-system-i386 - same demonic
sound.
With the above configuration but with
** Also affects: qemu
Importance: Undecided
Status: New
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1810105
Title:
Hint showing volume never disappears, blocking buttons to minimize,
On 2019-01-01 05:24, Programmingkid wrote:
>> On 2018-12-29 01:49, Programmingkid wrote:
[snip]
>>>
>>> I tried ac97 with a Windows 2000 guest in qemu-system-i386 - same demonic
>>> sound.
>>> With the above configuration but with an es1370 sound card I heard the same
>>> sound. I kept seeing "es
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