It's nice to see cloud vendors are also quite interested in VFIO
migration interfaces and functions. From what Yan said and Huawei's
requirements, there should be more devices which don't have private
memory, maybe GPU is almost the only one which has the private memory.
As VFIO is a generic u
On 2018-12-21 04:06, Alexey Kardashevskiy wrote:
> Hi
>
> I am trying https://travis-ci.org/aik/qemu/ and that thing fails every
> time I am not so sure why.
>
> One example:
> https://travis-ci.org/aik/qemu/jobs/470796318
>
> The errors are like this:
>
> GTESTER check-qtest-unicore32
> GT
From: Michael Roth
Hotplugging PHBs is a machine-level operation, but PHBs reside on the
main system bus, so we register spapr machine as the handler for the
main system bus.
We re-get the phandle of the interrupt controller systematically for
simplicity.
Signed-off-by: Michael Roth
Signed-off
This will be needed by PHB hotplug in order to access the phandle property.
Signed-off-by: Greg Kurz
---
hw/intc/spapr_xive.c|9 +++--
hw/intc/xics_spapr.c|9 -
hw/ppc/spapr_irq.c |3 +++
include/hw/ppc/spapr_irq.h |1 +
include/hw/ppc/spapr_
> scenario 1: did the tcg translation need to be done in this case now
> that the host and target arch is the same? or let the kvm emulation
> the system wit the original instructions with out the TCG
> translation
TCG is turned off when KVM is enabled. The code for TCG does not run at
all.
>
From: Robert Hoo
Processor tracing is not yet implemented for KVM and it will be an
opt in feature requiring a special module parameter.
Disable it, because it is wrong to enable it by default and
it is impossible that no one has ever used it.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Paolo Bonz
On 20/12/18 13:50, Robert Hoo wrote:
> On Thu, 2018-12-20 at 13:38 +0100, Paolo Bonzini wrote:
>> On 20/12/18 01:18, Robert Hoo wrote:
>>> I think the sooner, the better. Take the time window that Icelake
>>> CPU
>>> model has just shipped with QEMU 3.1.0 and is not publicly/widely
>>> used
>>> yet
From: Cédric Le Goater
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/ppc/spapr.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 65c6065602..19a07c5c9d 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -3931,7 +
From: Cédric Le Goater
The XIVE IRQ backend uses the same layout as the new XICS backend but
covers the full range of the IRQ number space. The IRQ numbers for the
CPU IPIs are allocated at the bottom of this space, below 4K, to
preserve compatibility with XICS which does not use that range.
Thi
From: Cédric Le Goater
This option is used to select the interrupt controller mode (XICS or
XIVE) with which the machine will operate. XICS being the default
mode for now.
When running a machine with the XIVE interrupt mode backend, the guest
OS is required to have support for the XIVE exploitat
From: Cédric Le Goater
The XIVE interface for the guest is described in the device tree under
the "interrupt-controller" node. A couple of new properties are
specific to XIVE :
- "reg"
contains the base address and size of the thread interrupt
managnement areas (TIMA), for the User level
From: Cédric Le Goater
Introduce a new sPAPR IRQ handler to handle resend after migration
when the machine is using a KVM XICS interrupt controller model.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
Signed-off-by: David Gibson
---
hw/ppc/spapr.c | 13 +
From: Cédric Le Goater
For the time being, the XIVE reset handler updates the OS CAM line of
the vCPU as it is done under a real hypervisor when a vCPU is
scheduled to run on a HW thread. This will let the XIVE presenter
engine find a match among the NVTs dispatched on the HW threads.
This handl
From: Alexey Kardashevskiy
When deciding about the huge DMA window, the typical Linux pseries guest
uses the maximum allowed RAM size as the upper limit. We did the same
on QEMU side to match that logic. Now we are going to support a GPU RAM
pass through which is not available at the guest boot t
From: Cédric Le Goater
The interrupt modes supported by the hypervisor are advertised to the
guest with new bits definitions of the option vector 5 of property
"ibm,arch-vec-5-platform-support. The byte 23 bits 0-1 of the OV5 are
defined as follow :
0b00 PAPR 2.7 and earlier (Legacy systems)
From: Cédric Le Goater
The XiveRouter models the second sub-engine of the XIVE architecture :
the Interrupt Virtualization Routing Engine (IVRE).
The IVRE handles event notifications of the IVSE and performs the
interrupt routing process. For this purpose, it uses a set of tables
stored in syste
From: Cédric Le Goater
After the event data was enqueued in the O/S Event Queue, the IVPE
raises the bit corresponding to the priority of the pending interrupt
in the register IBP (Interrupt Pending Buffer) to indicate there is an
event pending in one of the 8 priority queues. The Pending Interru
From: Cédric Le Goater
To complete the event routing, the IVRE sub-engine uses a second table
containing Event Notification Descriptor (END) structures.
An END specifies on which Event Queue (EQ) the event notification
data, defined in the associated EAS, should be posted when an
exception occur
From: Cédric Le Goater
The different XIVE virtualization structures (sources and event queues)
are configured with a set of Hypervisor calls :
- H_INT_GET_SOURCE_INFO
used to obtain the address of the MMIO page of the Event State
Buffer (ESB) entry associated with the source.
- H_INT_S
From: Cédric Le Goater
The IVPE scans the O/S CAM line of the XIVE thread interrupt contexts
to find a matching Notification Virtual Target (NVT) among the NVTs
dispatched on the HW processor threads.
On a real system, the thread interrupt contexts are updated by the
hypervisor when a Virtual Pr
From: Cédric Le Goater
The XiveNotifier offers a simple interface, between the XiveSource
object and the main interrupt controller of the machine. It will
forward event notifications to the XIVE Interrupt Virtualization
Routing Engine (IVRE).
Signed-off-by: Cédric Le Goater
[dwg: Adjust type na
From: Cédric Le Goater
Each interrupt mode has its own specific interrupt presenter object,
that we store under the CPU object, one for XICS and one for XIVE.
Extend the sPAPR IRQ backend with a new handler to support them both.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
Signed
From: Cédric Le Goater
Initialize the MSI bitmap from it as this will be necessary for the
sPAPR IRQ backend for XIVE.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
Signed-off-by: David Gibson
---
hw/ppc/spapr.c | 2 +-
hw/ppc/spapr_irq.c | 16 +++
From: Cédric Le Goater
The first sub-engine of the overall XIVE architecture is the Interrupt
Virtualization Source Engine (IVSE). An IVSE can be integrated into
another logic, like in a PCI PHB or in the main interrupt controller
to manage IPIs.
Each IVSE instance is associated with an Event St
From: Cédric Le Goater
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d676c73f88..0ab4676b06 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1011,6 +1011,14 @@ F: tests/libqo
From: Cédric Le Goater
The Event Notification Descriptor (END) XIVE structure also contains
two Event State Buffers providing further coalescing of interrupts,
one for the notification event (ESn) and one for the escalation events
(ESe). A MMIO page is assigned for each to control the EOI through
From: Greg Kurz
Because it is a recommended coding practice (see HACKING).
Signed-off-by: Greg Kurz
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: David Gibson
---
hw/ppc/sam460ex.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
From: Cédric Le Goater
The 'sent' status of the LSI interrupt source is modeled with the 'P'
bit of the ESB and the assertion status of the source is maintained
with an extra bit under the main XiveSource object. The type of the
source is stored in the same array for practical reasons.
Signed-of
From: Cédric Le Goater
sPAPRXive models the XIVE interrupt controller of the sPAPR machine.
It inherits from the XiveRouter and provisions storage for the routing
tables :
- Event Assignment Structure (EAS)
- Event Notification Descriptor (END)
The sPAPRXive model incorporates an internal X
From: Greg Kurz
Because it is a recommended coding practice (see HACKING).
Signed-off-by: Greg Kurz
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: David Gibson
---
hw/ppc/ppc405_uc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc40
From: Cédric Le Goater
The XIVE sPAPR IRQ backend will use it to define the number of ENDs of
the IC controller.
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/ppc/spapr.c | 8
include/hw/ppc/spapr.h | 1 +
2 files changed, 5 insertions(+), 4 deletions(-)
From: Cédric Le Goater
We will need to use xics_max_server_number() to create the sPAPRXive
object modeling the interrupt controller of the machine which is
created before the CPUs.
Signed-off-by: Cédric Le Goater
Reviewed-by: Greg Kurz
[dwg: Fix style nit]
Signed-off-by: David Gibson
---
hw
From: Cédric Le Goater
The last sub-engine of the XIVE architecture is the Interrupt
Virtualization Presentation Engine (IVPE). On HW, the IVRE and the
IVPE share elements, the Power Bus interface (CQ), the routing table
descriptors, and they can be combined in the same HW logic. We do the
same i
From: Greg Kurz
Because it is a recommended coding practice (see HACKING).
Signed-off-by: Greg Kurz
Signed-off-by: David Gibson
---
hw/ppc/ppc405_boards.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 1b0a0a8ba3..
From: Greg Kurz
The OpenPIC have 5 outputs per connected CPU. The machine init code hence
needs a bi-dimensional array (smp_cpu lines, 5 columns) to wire up the irqs
between the PIC and the CPUs.
The current code first allocates an array of smp_cpus pointers to qemu_irq
type, then it allocates a
From: Greg Kurz
The OpenPIC have 5 outputs per connected CPU. The machine init code hence
needs a bi-dimensional array (smp_cpu lines, 5 columns) to wire up the irqs
between the PIC and the CPUs.
The current code first allocates an array of smp_cpus pointers to qemu_irq
type, then it allocates a
From: Cédric Le Goater
Each POWER9 processor chip has a XIVE presenter that can generate four
different exceptions to its threads:
- hypervisor exception,
- O/S exception
- Event-Based Branch (EBB)
- msgsnd (doorbell).
Each exception has a state independent from the others called a Thre
From: Greg Kurz
Signed-off-by: Greg Kurz
Signed-off-by: David Gibson
Reviewed-by: Laurent Vivier
---
hw/ppc/spapr.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index b423db311e..051d080fe5 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -889,8 +889
From: Greg Kurz
Because it is a recommended coding practice (see HACKING).
Signed-off-by: Greg Kurz
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
Signed-off-by: David Gibson
---
hw/ppc/ppc440_bamboo.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --gi
From: Greg Kurz
Because it is a recommended coding practice (see HACKING).
Signed-off-by: Greg Kurz
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
Signed-off-by: David Gibson
---
hw/ppc/virtex_ml507.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw
From: Greg Kurz
Because it is a recommended coding practice (see HACKING).
Signed-off-by: Greg Kurz
Signed-off-by: David Gibson
---
hw/ppc/spapr_iommu.c | 2 +-
hw/ppc/spapr_vio.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/spapr_iommu.c b/hw/ppc/spapr_iomm
From: "Paul A. Clarke"
Changes requirement for "vsubsbs" instruction, which has been supported
since ISA 2.03. (Please see section 5.9.1.2 of ISA 2.03)
Reported-by: Paul A. Clarke
Signed-off-by: Paul A. Clarke
Signed-off-by: Leonardo Bras
Signed-off-by: David Gibson
---
target/ppc/translate
From: Suraj Jitindar Singh
Implement the addex instruction introduced in ISA V3.00 in qemu tcg.
The add extended using alternate carry bit (addex) instruction performs
the same operation as the add extended (adde) instruction, but using the
overflow (ov) field in the fixed point exception regist
From: Greg Kurz
Because it is a recommended coding practice (see HACKING).
Signed-off-by: Greg Kurz
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: David Gibson
---
target/ppc/translate_init.inc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/ppc/transla
From: Serhii Popovych
Laurent Vivier reported off by one with maximum number of NUMA nodes
provided by qemu-kvm being less by one than required according to
description of "ibm,max-associativity-domains" property in LoPAPR.
It appears that I incorrectly treated LoPAPR description of this
propert
The (only) obvious use for these macros is constructing and parsing guest
visible register fields. But the way they're constructed, they're only
valid when used on a *host* long, whose size shouldn't be visible to the
guest at all.
They also have no current users, so just get rid of them.
Signed
From: Cédric Le Goater
Change the PPC_BIT macro to use ULL instead of UL and the PPC_BIT32
and PPC_BIT8 not to use any suffix.
This fixes a compile breakage on windows.
Signed-off-by: Cédric Le Goater
Signed-off-by: David Gibson
---
target/ppc/cpu.h | 6 +++---
1 file changed, 3 insertions(+
The following changes since commit 95de6f4b92efea391a3cbb8651d774a4d3529861:
Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2018-12-20' into
staging (2018-12-20 18:54:47 +)
are available in the Git repository at:
git://github.com/dgibson/qemu.git tags/ppc-for-4.0-20181221
On 2018-12-20 at 09:06:41 -0500, Michael S. Tsirkin wrote:
> On Thu, Dec 20, 2018 at 01:37:40PM +0800, Yi Zhang wrote:
> > On 2018-12-19 at 22:42:07 -0500, Michael S. Tsirkin wrote:
> > > On Thu, Dec 20, 2018 at 11:03:12AM +0800, Yi Zhang wrote:
> > > > On 2018-12-19 at 10:59:10 -0500, Michael S. T
On Wed, Dec 19, 2018 at 08:15:36PM +0100, Cédric Le Goater wrote:
> [ ... ]
>
> >>> +static qemu_irq spapr_qirq_dual(sPAPRMachineState *spapr, int irq)
> >>> +{
> >>> +return spapr_irq_current(spapr)->qirq(spapr, irq);
> >>> +}
> >>
> >> This still makes me really nervous - I'd really prefer t
Hi
I am trying https://travis-ci.org/aik/qemu/ and that thing fails every
time I am not so sure why.
One example:
https://travis-ci.org/aik/qemu/jobs/470796318
The errors are like this:
GTESTER check-qtest-unicore32
GTESTER check-qtest-x86_64
Could not access KVM kernel module: No such file
hi folks:
i am very puzzled about the relationship between "target cpu instruction"
translated to host instructions through TCG module and the "kvm" acceleration"
mode.
think about three scenario of emulation:
scenario 1, 2 and 3 as follows:
1. target cpu: x86_64,
host cpu: x84_64,
ping
On 12/6/18 10:32, Li Zhijian wrote:
Long long ago, linux kernel has supported up to 4G initrd, but it's header
still hard code to allow loading initrd below 2G only.
cutting from arch/x86/head.S:
# (Header version 0x0203 or later) the highest safe address for the contents
# of an init
From: Michael Roth
Certain devices types, like memory/CPU, are now being handled using a
hotplug interface provided by a top-level MachineClass. Hotpluggable
host bridges are another such device where it makes sense to use a
machine-level hotplug handler. However, unlike those devices,
host-bridg
From: Michael Roth
PHB hotplug re-uses PHB device tree generation code and passes
it to a guest via RTAS. Doing this requires knowledge of where
exactly in the device tree the node describing the PHB begins.
Provide this via a new optional pointer that can be used to
store the PHB node's start o
From: Michael Roth
Extend the existing EPOW event format we use for PCI
devices to emit PHB plug/unplug events.
Signed-off-by: Michael Roth
Reviewed-by: David Gibson
Signed-off-by: Greg Kurz
---
hw/ppc/spapr_events.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/ppc/spapr_even
From: Michael Roth
Signed-off-by: Michael Roth
Reviewed-by: David Gibson
Signed-off-by: Greg Kurz
---
hw/ppc/spapr.c | 13 +
hw/ppc/spapr_drc.c | 17 +
include/hw/ppc/spapr_drc.h |8
3 files changed, 38 insertions(+)
diff --git
From: Michael Roth
This is needed to denote a boot-time PHB as being hot-pluggable.
Signed-off-by: Michael Roth
Reviewed-by: David Gibson
Signed-off-by: Greg Kurz
---
hw/ppc/spapr_pci.c |9 +
1 file changed, 9 insertions(+)
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
in
PHB hotplug will bring more users for it. Let's define it along with
the PHB defines from which it is derived for simplicity.
While here fix a misleading comment about manual placement, which was
abandoned with 30b3bc5aa9f4.
Signed-off-by: Greg Kurz
---
hw/ppc/spapr.c |2 --
in
From: Michael Roth
This adds cleanup counterparts to pci_register_root_bus(),
pci_root_bus_new(), and pci_bus_irqs().
These cleanup routines are needed in the case of hotpluggable
PCIHostBridge implementations. Currently we can rely on the
object_unparent()'ing of the PCIHostState recursively un
From: Nathan Fontenot
This add entries to the root OF node to advertise our PHBs as being
DR-capable in accordance with PAPR specification.
Signed-off-by: Nathan Fontenot
Signed-off-by: Michael Roth
Reviewed-by: David Gibson
Signed-off-by: Greg Kurz
---
hw/ppc/spapr.c |8
1 fil
The current realize code assumes the PHB is coldplugged, ie, QEMU will
terminate if an error is detected, and does not bother to free anything
it has already allocated.
In order to support PHB hotplug, let's first ensure spapr_phb_realize()
doesn't leak anything in case of error.
Signed-off-by: G
This function is only used when creating the default PHB. Let's rename
it and move it to the core machine code for clarity.
Signed-off-by: Greg Kurz
Reviewed-by: Alexey Kardashevskiy
Reviewed-by: David Gibson
---
hw/ppc/spapr.c | 13 -
hw/ppc/spapr_pci.c |
From: Michael Roth
The 'dr_phb_enabled' field of that class can be set as part of
machine-specific init code. It will be used to conditionally
enable creation of DRC objects and device-tree description to
facilitate hotplug of PHBs.
Since we can't migrate this state to older machine types,
defau
From: Michael Roth
To support PHB hotplug we need to clean up lingering references,
memory, child properties, etc. prior to the PHB object being
finalized. Generally this will be called as a result of calling
object_unparent() on the PHB object, which in turn would normally
be called as the resul
From: Alexey Kardashevskiy
SLOF receives a device tree and updates it with various properties
before switching to the guest kernel and QEMU is not aware of any changes
made by SLOF. Since there is no real RTAS (QEMU implements it), it makes
sense to pass the SLOF final device tree to QEMU to let
Previous work on PHB hotplug was last posted more than one year ago:
https://lists.gnu.org/archive/html/qemu-devel/2017-07/msg07906.html
Quite a few significant changes happened since then:
- fixed PHB indexes
- fixed IRQ numbers for LSIs
- SLOF capable of updating the FDT in QEMU
- XIVE
First s
Hi alex:
now my host machine did not have the "/dev/kvm" nodes and no chance to make
it exists.
so i want to know whether the "/dev/kvm" is mandatory for qemu to emulate the
whole system.
so i can make the emulation without the support of kvm mechanism.
thanks for your support.!
On Thu, Dec 20, 2018 at 12:15 PM Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
>
> At some point we should make this routine be non-optional for
> porting to a new host.
>
>
> r~
>
> ---
> linux-user/host/riscv64/hostdep.h
On 12/20/18 6:21 AM, Vladimir Sementsov-Ogievskiy wrote:
> 20.12.2018 5:29, John Snow wrote:
>> As laid out in the previous commit's message:
>>
>> ```
>> Several places in iotests deal with serializing objects into JSON
>> strings, but to add pretty-printing it seems desireable to localize
>> a
On 12/19/18 9:53 PM, Eric Blake wrote:
> On 12/19/18 8:29 PM, John Snow wrote:
>> As laid out in the previous commit's message:
>>
>> ```
>> Several places in iotests deal with serializing objects into JSON
>> strings, but to add pretty-printing it seems desireable to localize
>
> s/desireable/
On Fri, Dec 21, 2018 at 12:08 AM Eduardo Habkost wrote:
>
> On Thu, Dec 13, 2018 at 01:48:29AM +0400, Marc-André Lureau wrote:
> > Use static arrays instead.
> >
> > Suggested-by: Eduardo Habkost
> > Signed-off-by: Marc-André Lureau
>
> In case you need to respin the series: I suggest squashing
On Wed, Dec 19, 2018 at 11:40:37AM +0100, Igor Mammedov wrote:
> On Wed, 19 Dec 2018 10:57:17 +0800
> Yu Zhang wrote:
>
> > On Tue, Dec 18, 2018 at 03:55:36PM +0100, Igor Mammedov wrote:
> > > On Tue, 18 Dec 2018 17:27:23 +0800
> > > Yu Zhang wrote:
> > >
> > > > On Mon, Dec 17, 2018 at 02:17
On 12/20/18 12:40 PM, Peter Maydell wrote:
> On Thu, 20 Dec 2018 at 20:16, Richard Henderson
> wrote:
>>
>> Signed-off-by: Richard Henderson
>> ---
>>
>> At some point we should make this routine be non-optional for
>> porting to a new host.
>
> Yes, I agree -- how many hosts do we still have wh
On 12/19/18 9:48 PM, Eric Blake wrote:
> On 12/19/18 8:29 PM, John Snow wrote:
>> Especially outside of transactions, it is helpful to provide
>> all-or-nothing semantics for bitmap merges. This facilitates
>> the coalescing of multiple bitmaps into a single target for
>> the "checkpoint" interp
On Tue, Dec 18, 2018 at 05:27:23PM +0800, Yu Zhang wrote:
> On Mon, Dec 17, 2018 at 02:17:40PM +0100, Igor Mammedov wrote:
> > On Wed, 12 Dec 2018 21:05:38 +0800
> > Yu Zhang wrote:
> >
> > > Currently, vIOMMU is using the value of IOVA address width, instead of
> > > the host address width(HAW)
On 12/19/18 10:02 PM, Eric Blake wrote:
> On 12/19/18 8:29 PM, John Snow wrote:
>> New interface, new smoke test.
>>
>> Signed-off-by: John Snow
>> ---
>> tests/qemu-iotests/236 | 161 +
>> tests/qemu-iotests/236.out | 351 +
>> tests/
On 12/20/18 7:12 AM, Vladimir Sementsov-Ogievskiy wrote:
> 20.12.2018 5:29, John Snow wrote:
>> New interface, new smoke test.
>>
>> Signed-off-by: John Snow
>> ---
>
> [...]
>
>> +# A: 7 clusters
>> +# B: 4 clusters
>> +# C: 6 clusters
>> +log(query_bitmaps(vm), indent=2)
>>
On Thu, 20 Dec 2018 at 20:16, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
>
> At some point we should make this routine be non-optional for
> porting to a new host.
Yes, I agree -- how many hosts do we still have which are
missing support for it?
thanks
-- PMM
On Thu, 20 Dec 2018 at 09:47, Markus Armbruster wrote:
>
> The following changes since commit b72566a4ffaddbc0c0c1f6f5ee91b42ab13ff429:
>
> Merge remote-tracking branch
> 'remotes/vivier2/tags/trivial-patches-pull-request' into staging (2018-12-19
> 15:31:02 +)
>
> are available in the Git
Signed-off-by: Richard Henderson
---
At some point we should make this routine be non-optional for
porting to a new host.
r~
---
linux-user/host/riscv64/hostdep.h | 23 +++
linux-user/host/riscv64/safe-syscall.inc.S | 77 ++
2 files changed, 100 insertions(+)
On Thu, Dec 13, 2018 at 01:48:29AM +0400, Marc-André Lureau wrote:
> Use static arrays instead.
>
> Suggested-by: Eduardo Habkost
> Signed-off-by: Marc-André Lureau
In case you need to respin the series: I suggest squashing
patches 07-19 together.
--
Eduardo
Public bug reported:
Recently, I created a file using hdiutil from MacOS (using Zlib
compression):
$ hdiutil create -volname MyVolName -srcfolder /path/to/my/vol/ -ov
-format UDZO myvolname.dmg
But, when I try to convert this volume using qemu-img convert, this
command is freezing.
I'm using th
** Tags removed: qemu
** Tags added: arm
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https://bugs.launchpad.net/bugs/1737883
Title:
Cannot boot FreeBSD on versatilepb machine
Status in QEMU:
Incomplete
Bug description:
I
On Thu, 20 Dec 2018 09:20:05 PST (-0800), alistai...@gmail.com wrote:
On Wed, Dec 19, 2018 at 10:07 PM Richard Henderson
wrote:
On 12/19/18 11:16 AM, Alistair Francis wrote:
> This patch set adds RISC-V backend support to QEMU. This is based on
> Michael Clark's original work with extra work o
On Thu, Dec 20, 2018 at 10:45 AM Palmer Dabbelt wrote:
>
> On Thu, 20 Dec 2018 09:20:05 PST (-0800), alistai...@gmail.com wrote:
> > On Wed, Dec 19, 2018 at 10:07 PM Richard Henderson
> > wrote:
> >>
> >> On 12/19/18 11:16 AM, Alistair Francis wrote:
> >> > This patch set adds RISC-V backend supp
From: Peter Xu
Starting from QEMU 4.0, let's specify "split" as the default value for
kernel-irqchip.
So for QEMU>=4.0 we'll have: allowed=Y,required=N,split=Y
for QEMU<=3.1 we'll have: allowed=Y,required=N,split=N
(omitting all the "kernel_irqchip_" prefix)
Note that this will let the de
** Changed in: qemu
Status: New => Opinion
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https://bugs.launchpad.net/bugs/1781463
Title:
qemu don't start *.abs firmware files
Status in QEMU:
Opinion
Bug description:
H
'Hi, from this report your setup is unclear to me'.
Hi,
I am not using Linux kernel.
The t.bin image is a program built with .s and .c files using gcc-arm-none-eabi
for ARM
The sdimage is just a regular 1MB file, which is used by the -sd sdmage as a
virtual SDC card for
qemu-system-arm under Ubu
From: Peter Xu
When the user didn't specify "intremap" for the IOMMU device, we turn
it on by default if it is supported. This will turn IR on for the
default Q35 platform as long as the IOMMU device is specified on new
kernels.
Signed-off-by: Peter Xu
Acked-by: Paolo Bonzini
Reviewed-by: Mic
From: David Hildenbrand
These functions are essentially the same, we only have to use
object_get_typename() for reporting errors. So let's share the
implementation of hotplug handler callbacks.
Suggested-by: Igor Mammedov
Reviewed-by: Igor Mammedov
Signed-off-by: David Hildenbrand
Reviewed-by
On 20/12/18 18:41, Peter Maydell wrote:
>> This seemed to work on most of my test hosts but something
>> weird happened here: hyperlong repetitive command line and
>> looks like make got an "fwrite(): Resource temporarily unavailable"
>> halfway through writing it out??
>>
>> This was on my x86-64
From: David Hildenbrand
Introduce and use the "unplug" callback.
This is a preparation for multi-stage hotplug handlers, whereby the bus
hotplug handler is overwritten by the machine hotplug handler. This handler
will then pass control to the bus hotplug handler. So to get this running
cleanly,
From: David Hildenbrand
Perform the check in the pre_plug handler. In addition, we need the
capability only if the device is actually hotplugged (and not created
during machine initialization). This is a preparation for coldplugging
pci devices via that hotplug handler.
Reviewed-by: Igor Mammedo
On Thu, 20 Dec 2018 11:04:41 PST (-0800), alistai...@gmail.com wrote:
On Thu, Dec 20, 2018 at 10:45 AM Palmer Dabbelt wrote:
On Thu, 20 Dec 2018 09:20:05 PST (-0800), alistai...@gmail.com wrote:
> On Wed, Dec 19, 2018 at 10:07 PM Richard Henderson
> wrote:
>>
>> On 12/19/18 11:16 AM, Alistair
From: Thomas Huth
They've been deprecated for two releases and nobody complained that they
are still required anymore, so it's time to remove these now.
And while we're at it, mark the other remaining old 0.x machine types
as deprecated (since they can not properly be used for live-migration
anyw
From: Alex Williamson
A conventional PCI bus does not support config space accesses above
the standard 256 byte configuration space. PCIe-to-PCI bridges are
not permitted to forward transactions if the extended register address
field is non-zero and must handle it as an unsupported request (PCIe
From: David Hildenbrand
Introduce and use the "unplug" callback.
This is a preparation for multi-stage hotplug handlers, whereby the bus
hotplug handler is overwritten by the machine hotplug handler. This handler
will then pass control to the bus hotplug handler. So to get this running
cleanly,
From: Samuel Ortiz
Now that build_rsdp() supports building both legacy and current RSDP
tables, we can move it to a generic folder (hw/acpi) and have the i386
ACPI code reuse it in order to reduce code duplication.
Signed-off-by: Samuel Ortiz
Reviewed-by: Igor Mammedov
Reviewed-by: Michael S.
From: David Hildenbrand
Introduce and use the "unplug" callback.
This is a preparation for multi-stage hotplug handlers, whereby the bus
hotplug handler is overwritten by the machine hotplug handler. This handler
will then pass control to the bus hotplug handler. So to get this running
cleanly,
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