On 12/17/18 5:50 AM, David Gibson wrote:
> On Sat, Dec 15, 2018 at 07:42:22PM +0100, Cédric Le Goater wrote:
>> Fix the PPC_BIT definitions to use ULL instead in UL and replace
>> __builtin_ffssl() by the equivalent ctz routines.
>>
>> Signed-off-by: Cédric Le Goater
>> ---
>>
>> Compile tested w
On Mon, Dec 17, 2018 at 4:31 AM David Gibson
wrote:
>
> On Fri, Dec 14, 2018 at 06:49:55PM +0100, Cédric Le Goater wrote:
> > On 12/14/18 5:03 PM, Peter Maydell wrote:
> > > On Thu, 13 Dec 2018 at 04:01, David Gibson
> > > wrote:
> > >>
> > >> The following changes since commit
> > >> 4b3aab204
Report more *_invalid() tracepoints to error_report_once() so that we
can detect issues even without tracing enabled. Drop those tracepoints.
Signed-off-by: Peter Xu
---
hw/i386/intel_iommu.c | 58 ---
hw/i386/trace-events | 6 -
2 files changed, 43
The iotlb.iova can be zero if failure really happened. Dump the addr
instead.
Signed-off-by: Peter Xu
---
hw/i386/intel_iommu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index d97bcbc2f7..f21988f396 100644
--- a/hw/i386/int
Support DMA read/write draining should be easy for existing VT-d
emulation since the emulation itself does not have any request queue
there so we don't need to do anything to flush the un-commited queue.
What we need to do is to declare the support.
These capabilities are required to pass Windows
Patch 1-2: mostly for debugging purpose, either on continuous
converting tracepoints into error reports, or fix incorrect
debug messages.
Patch 3: enable dma read/write draining support for vt-d emulation.
The major reason is to pass Windows SVVP verification.
P
IR has been there for a long time and long time no bug reported.
Let's turn it on by default to match general hardwares. Providing
compatibility bit for QEMU<=3.1.
Signed-off-by: Peter Xu
---
hw/i386/x86-iommu.c | 2 +-
include/hw/i386/pc.h | 4
2 files changed, 5 insertions(+), 1 deletio
On 12/13/2018 03:26 PM, Markus Armbruster wrote:
There's a question for David Gibson inline. Please search for /ppc/.
Fei Li writes:
Make qemu_thread_create() return a Boolean to indicate if it succeeds
rather than failing with an error. And add an Error parameter to hold
the error messag
We're going to have 57bits aw-bits support sooner. It's possibly time
to remove the "x-" prefix.
Signed-off-by: Peter Xu
---
hw/i386/intel_iommu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 26cc731c7b..96ef31eb7e 10064
Marc-André Lureau writes:
> The following patches are going to introduce per-target #ifdef in the
> schemas.
>
> The introspection data is statically generated once, and must thus be
> built per-target to reflect target-specific configuration.
>
> Drop "do_test_visitor_in_qmp_introspect(&qmp_sche
Signed-off-by: Li Qiang
---
util/main-loop.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/util/main-loop.c b/util/main-loop.c
index affe0403c5..845a4b1f13 100644
--- a/util/main-loop.c
+++ b/util/main-loop.c
@@ -26,7 +26,6 @@
#include "qapi/error.h"
#include "qemu/cutils.h"
#include "qem
On Tue, Dec 11, 2018 at 11:38:19PM +0100, Cédric Le Goater wrote:
> This option is used to select the interrupt controller mode (XICS or
> XIVE) with which the machine will operate. XICS being the default
> mode for now.
>
> When running a machine with the XIVE interrupt mode backend, the guest
>
On Tue, Dec 11, 2018 at 11:38:23PM +0100, Cédric Le Goater wrote:
> Signed-off-by: Cédric Le Goater
Uh.. this will need something to keep the default at POWER8 for the
older machine types.
> ---
> hw/ppc/spapr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/ppc/sp
On Thu, Dec 13, 2018 at 01:52:14PM +0100, Cédric Le Goater wrote:
> On 12/11/18 11:38 PM, Cédric Le Goater wrote:
> > Currently, the interrupt presenter of the vCPU is set at realize
> > time. Setting it at reset will become necessary when the new machine
> > supporting both interrupt modes is intr
On Tue, Dec 11, 2018 at 11:38:22PM +0100, Cédric Le Goater wrote:
> The 'dual' sPAPR IRQ backend supports both interrupt mode, XIVE
> exploitation mode and the legacy compatibility mode (XICS). both modes
> are not supported at the same time.
>
> The machine starts with the legacy mode and a new i
On Tue, Dec 11, 2018 at 11:38:20PM +0100, Cédric Le Goater wrote:
> Currently, the interrupt presenter of the vCPU is set at realize
> time. Setting it at reset will become necessary when the new machine
> supporting both interrupt modes is introduced. In this machine, the
> interrupt mode is chose
On Tue, Dec 11, 2018 at 11:38:21PM +0100, Cédric Le Goater wrote:
> Depending on the interrupt mode of the machine, enable or disable the
> XIVE MMIOs.
>
> Signed-off-by: Cédric Le Goater
> ---
>
> Changes since v7:
>
> - renamed spapr_xive_enable_mmio() to spapr_xive_mmio_set_enabled()
>
>
On 2018-12-12 at 10:06:13 -0500, Michael S. Tsirkin wrote:
> On Wed, Dec 12, 2018 at 04:11:44PM +0800, Zhang Yi wrote:
> > Linux 4.15 introduces a new mmap flag MAP_SYNC, which can be used to
> > guarantee the write persistence to mmap'ed files supporting DAX (e.g.,
> > files on ext4/xfs file syste
On Tue, Dec 11, 2018 at 11:38:18PM +0100, Cédric Le Goater wrote:
> The interrupt modes supported by the hypervisor are advertised to the
> guest with new bits definitions of the option vector 5 of property
> "ibm,arch-vec-5-platform-support. The byte 23 bits 0-1 of the OV5 are
> defined as follow
On Tue, Dec 11, 2018 at 11:38:11PM +0100, Cédric Le Goater wrote:
> Hello,
>
> Here is the version 8 of the QEMU models adding support for the XIVE
> interrupt controller to the sPAPR machine, under TCG only. KVM support
> will be proposed in an other patchset, along with the KVM XIVE device
> pat
On Sat, Dec 15, 2018 at 07:42:22PM +0100, Cédric Le Goater wrote:
> Fix the PPC_BIT definitions to use ULL instead in UL and replace
> __builtin_ffssl() by the equivalent ctz routines.
>
> Signed-off-by: Cédric Le Goater
> ---
>
> Compile tested with --cross-prefix=x86_64-w64-mingw32-. When I h
There's no point in waiting 5 full minutes when there will be
no more output. Compute timeout based on elapsed wall clock
time instead of N * delays, as the delay is a minimum sleep time.
Cc: Thomas Huth
Cc: Laurent Vivier
Cc: Paolo Bonzini
Signed-off-by: Richard Henderson
---
tests/libqtest
patch.
r~
The following changes since commit 58b1f0f21edcab13f78a376b1d90267626be1275:
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging
(2018-12-16 12:49:06 +)
are available in the Git repository at:
https://github.com/rth7680/qemu.git tags/pu
Partially reverts ab20bdc1162. The 14-bit displacement that we
allowed to reach the constant pool is not always sufficient.
Retain the tb-relative addressing, as that is how most return
values from the tb are computed.
Signed-off-by: Richard Henderson
---
tcg/sparc/tcg-target.inc.c | 47 +++
On Fri, Dec 14, 2018 at 06:49:55PM +0100, Cédric Le Goater wrote:
> On 12/14/18 5:03 PM, Peter Maydell wrote:
> > On Thu, 13 Dec 2018 at 04:01, David Gibson
> > wrote:
> >>
> >> The following changes since commit
> >> 4b3aab204204ca742836219b97b538d90584f4f2:
> >>
> >> Merge remote-tracking br
Hi Michael,
CCed Jason as this is related to commit a0ccd2123ee2 "pci: remove hard-coded bar
size in msix_init_exclusive_bar()"
Please see my reply inline.
On 12/17/2018 10:24 AM, Michael S. Tsirkin wrote:
> On Mon, Dec 17, 2018 at 07:34:39AM +0800, Dongli Zhang wrote:
>> The bar_pba_size is mor
On Mon, Dec 17, 2018 at 09:10:06AM +0800, Li Qiang wrote:
> PingPaolo, could these patches go to your misc tree?
>
> Thanks,
> Li Qiang
Fine by me
Reviewed-by: Michael S. Tsirkin
> Li Qiang 于2018年11月29日周四下午12:53写道：
>
> According https://wiki.qemu.org/Contribute/BiteSizedTasks
>
On Mon, Dec 17, 2018 at 07:34:39AM +0800, Dongli Zhang wrote:
> The bar_pba_size is more than what the pba is expected to have, although
> this usually would not affect the bar_size used for dev->msix_exclusive_bar
> initialization.
>
> Signed-off-by: Dongli Zhang
If this does ever have an effe
On 14/12/2018 22:07, Philippe Mathieu-Daudé wrote:
> Hi Alexey,
>
> On 12/14/18 3:58 AM, Alexey Kardashevskiy wrote:
>> This adds an accelerator name to the "into mtree -f" to tell the user if
>> a particular memory section is registered with the accelerator;
>> the primary user for this is KVM
PingPaolo, could these patches go to your misc tree?
Thanks,
Li Qiang
Li Qiang 于2018年11月29日周四 下午12:53写道：
> According https://wiki.qemu.org/Contribute/BiteSizedTasks
> the 'DEFINE_PROP_PTR' should be replaced by QOM link property.
> The first patch replace constant strings with TYPE_ and
The bar_pba_size is more than what the pba is expected to have, although
this usually would not affect the bar_size used for dev->msix_exclusive_bar
initialization.
Signed-off-by: Dongli Zhang
---
hw/pci/msix.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/pci/msix.c b/h
I think this is a spice issue. I think anyone who has successfully
used these buttons wasn't using spice.
spice-protocol::spice/enums.h only gives SpiceMouseButton types of
LEFT, MIDDLE, RIGHT, UP, and DOWN.
spice-gtk::src/spide-widget.c::button_event() calls
button_gdk_to_spice() which also onl
Running "remote-viewer --spice-debug" does show events for pushing the
scroll wheel left and right:
(remote-viewer:14226): GSpice-DEBUG: 17:09:00.043: spice-widget.c:2007
0:0 button_event press: button 8, state 0x10
(remote-viewer:14226): GSpice-DEBUG: 17:09:00.414: spice-widget.c:2007
0:0 button_
I didn't make it very clear that my Arch Linux guest didn't had tablet
emulation. On it, evtest only shows "ImExPS/2 Generic Explorer
Mouse". On its monitor, "info mice" shows:
* Mouse #2: QEMU PS/2 Mouse
On the Windows 7 guest, you're right:
Mouse #2: QEMU PS/2 Mouse
* Mouse #3: QEMU HID Ta
The sun4u/sun4v machine currently always creates a VGA device, even if
the user started QEMU with "-nodefaults" or "-vga none". That's likely
not what the users expect in this case, so add a check whether the VGA
adapter has really been requested.
Signed-off-by: Thomas Huth
---
hw/sparc64/sun4u.
On Fri, 14 Dec 2018 at 13:54, Alex Bennée wrote:
>
> The following changes since commit d8d5fefd8657d4f7b380b3a1533340434b5b9def:
>
> Merge remote-tracking branch
> 'remotes/berrange/tags/qcrypto-next-pull-request' into staging (2018-12-13
> 18:45:18 +)
>
> are available in the Git reposit
On Fri, 14 Dec 2018 at 14:42, Peter Maydell wrote:
>
> This is a colletion of miscellaneous patches (mostly mine),
> which fix minor bugs or do some refactoring/cleanup.
> No user-visible changes in here.
>
> thanks
> -- PMM
>
> The following changes since commit 0f98c9945899c5dfacd5a410ff04178eda
On Fri, 14 Dec 2018 at 14:42, Peter Maydell wrote:
>
> This is a colletion of miscellaneous patches (mostly mine),
> which fix minor bugs or do some refactoring/cleanup.
> No user-visible changes in here.
>
> thanks
> -- PMM
>
> The following changes since commit 0f98c9945899c5dfacd5a410ff04178eda
Probably the PS/2 mouse is not used at all because the HID Tablet takes
precedence. By entering "info mice" on the monitor console you can see
which mouse is currently used. If you disable or uninstall the HID
Tablet, the PS/2 mouse should take over.
"IMEX" is short for Intelli Mouse Explorer.
Am
On Sun, 16 Dec 2018 at 20:11, Richard Henderson
wrote:
>
> On 12/16/18 4:43 AM, Peter Maydell wrote:
> > On Sun, 16 Dec 2018 at 07:03, Richard Henderson
> > wrote:
> > You have access to the gcc compile farm, right? The sparc
> > tests run on gcc202.fsffrance.org.
>
> Ah. I thought that machine
Hi Prasad,
Turned out that this patch cause a regression.
My test plan includes the following steps:
- Start two VMs.
- Run RC and UD traffic between the two.
- Run sanity local test on both which includes:
- RC traffic on 3 gids with various message size.
- UD traffic.
- R
On 12/16/18 4:43 AM, Peter Maydell wrote:
> On Sun, 16 Dec 2018 at 07:03, Richard Henderson
> wrote:
>>
>> On 12/15/18 1:18 PM, Peter Maydell wrote:
>>> This didn't pass 'make check' on sparc64 host.
>>> It looks like the handful of tests that exercise TCG
>>> in the process of doing what they do
Thanks!
I'd like to apply this but there's a conflict with other stuff queued.
Could you pls rebase on top of pci in
git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git
Alternatively wait until after the next pull request.
Thanks and sorry for all the churn!
On Thu, Dec 13, 2018 at 10:00:41PM +
On Fri, 14 Dec 2018 at 10:57, Kevin Wolf wrote:
>
> The following changes since commit d8d5fefd8657d4f7b380b3a1533340434b5b9def:
>
> Merge remote-tracking branch
> 'remotes/berrange/tags/qcrypto-next-pull-request' into staging (2018-12-13
> 18:45:18 +)
>
> are available in the Git reposito
Hello,
I apologize in advance if the question is stupid.
Let's suppose our hardware system contains a Vivante GPU. If we want to emulate
that system in QEMU, do we have to emulate that GPU (if yes, how to do it?), or
can/must we reuse some already developed equivalent component in QEMU? This is
It depends on TARGET_PPC || TARGET_ARM || TARGET_I386 || TARGET_S390X.
Signed-off-by: Marc-André Lureau
Reviewed-by: Eduardo Habkost
Acked-by: Cornelia Huck
---
qapi/misc.json | 58 --
qapi/target.json| 64 +++
Signed-off-by: Marc-André Lureau
Reviewed-by: Eduardo Habkost
Acked-by: Cornelia Huck
---
qapi/misc.json | 51 -
qapi/target.json | 52 ++
include/sysemu/arch_init.h | 3 --
monitor.c
Signed-off-by: Marc-André Lureau
Acked-by: Cornelia Huck
---
qapi/target.json | 6 ++
1 file changed, 6 insertions(+)
diff --git a/qapi/target.json b/qapi/target.json
index d751e1623a..dcfb6bc525 100644
--- a/qapi/target.json
+++ b/qapi/target.json
@@ -277,6 +277,9 @@
# an unknown
This command is no longer needed, the schema has compile-time
configuration conditions.
Signed-off-by: Marc-André Lureau
---
include/qapi/qmp/dispatch.h | 1 -
qapi/qmp-registry.c | 8
2 files changed, 9 deletions(-)
diff --git a/include/qapi/qmp/dispatch.h b/include/qapi/qmp/d
Signed-off-by: Marc-André Lureau
---
qapi/misc.json | 43 --
qapi/target.json | 45
monitor.c| 11 ---
target/arm/monitor.c | 2 +-
4 files changed, 46 insertions(+), 55 deletions(-
Move rtc-reset-reinjection and SEV in target.json and make them
conditional on TARGET_I386.
Signed-off-by: Marc-André Lureau
---
qapi/misc.json | 166 --
qapi/target.json | 175 -
target/i386/sev_i386.h |
Signed-off-by: Marc-André Lureau
Acked-by: Cornelia Huck
---
qapi/misc.json | 137 ---
qapi/target.json| 142
include/sysemu/arch_init.h | 7 --
hw/s390x/s390-skeys.c |
This will let the caller add several list of commands coming from
different schemas (the following patches split the schemas for common
and arch-specific parts).
Signed-off-by: Marc-André Lureau
---
scripts/qapi/commands.py | 2 --
monitor.c| 1 +
qga/main.c
A few targets don't emit RTC_CHANGE, we could restrict the event to
the tagets that do emit it.
Note: There is a lot more of events & commands that we could restrict
to capable targets, with the cost of some additional complexity, but
the benefit of added correctness and better introspection.
Not
The following patches are going to introduce per-target #ifdef in the
schemas.
The introspection data is statically generated once, and must thus be
built per-target to reflect target-specific configuration.
Drop "do_test_visitor_in_qmp_introspect(&qmp_schema_qlit)" since the
schema is no longer
Add a 'target' top-unit to be compiled seperately from the common qapi
modules. This will allow poisoned target #ifdef usage.
The generated commands must be registered seperately.
The events have a different enum, and must thus use a different
emitter/limiter.
The DUMMY event is there to force t
A module can declare belonging to a 'top-unit', with the corresponding
pragma value (the default 'top-unit' is None).
The generators have a chance to break the generated output by
units (top-units are visited first). Generated types, visitors,
events and commands are split by 'top-unit'. Generate
The function only calls various register_command() now, use a more
descriptive name.
Signed-off-by: Marc-André Lureau
---
scripts/qapi/commands.py | 4 ++--
monitor.c| 2 +-
qga/main.c | 2 +-
tests/test-qmp-cmds.c| 2 +-
docs/devel/qapi-code-gen
Hi,
The thrid and last part (of "[PATCH v2 00/54] qapi: add #if
pre-processor conditions to generated code") is about adding schema
conditions based on the target.
For now, the qapi code is compiled in common objects (common to all
targets). This makes it impossible to add #if TARGET_ARM for exam
On Fri, 14 Dec 2018 at 10:44, Gerd Hoffmann wrote:
>
> The following changes since commit 4f818e7b7f8ecb5c166d093b8859fec2ddeca2ef:
>
> Update version for v3.1.0-rc5 release (2018-12-06 17:07:12 +)
>
> are available in the git repository at:
>
> git://git.kraxel.org/qemu tags/usb-20181214-
On Sun, 16 Dec 2018 at 07:03, Richard Henderson
wrote:
>
> On 12/15/18 1:18 PM, Peter Maydell wrote:
> > This didn't pass 'make check' on sparc64 host.
> > It looks like the handful of tests that exercise TCG
> > in the process of doing what they do failed, and there
> > was a tcg assert in there
On Sun, 16 Dec 2018 at 06:20, Stefan Hajnoczi wrote:
>
> On Mon, Nov 26, 2018 at 05:43:59PM +, Peter Maydell wrote:
> > On Mon, 26 Nov 2018 at 00:24, Steffen Görtz wrote:
> > > What else is necessary to invalidate stale blocks?
> >
> > You need an AddressSpace that points to the MemoryRegion(
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