So we have a boot display when using a vgpu as primary display.
Gerd Hoffmann (2):
stubs: add ramfb
hw/vfio/display: add ramfb support
include/hw/vfio/vfio-common.h | 2 ++
hw/vfio/display.c | 12
hw/vfio/pci.c | 15 +++
stubs/ramfb.c
Needed to make sure code using ramfb (vfio) compiles properly even on
platforms without fw_cfg (and therefore no ramfb) support.
Signed-off-by: Gerd Hoffmann
---
stubs/ramfb.c | 13 +
stubs/Makefile.objs | 1 +
2 files changed, 14 insertions(+)
create mode 100644 stubs/ramfb.
So we have a boot display when using a vgpu as primary display.
Use vfio-pci-ramfb instead of vfio-pci to enable it.
Signed-off-by: Gerd Hoffmann
---
include/hw/vfio/vfio-common.h | 2 ++
hw/vfio/display.c | 12
hw/vfio/pci.c | 15 +++
3 fil
On 09/10/2018 08:12 AM, David Gibson wrote:
> On Mon, Jul 30, 2018 at 04:11:34PM +0200, Cédric Le Goater wrote:
>> The new layout using static IRQ number does not leave much space to
>> the dynamic MSI range, only 0x100 IRQ numbers. Increase the total
>> number of IRQS for newer machines and introd
On 2018-09-10 06:25, David Gibson wrote:
> On Fri, Sep 07, 2018 at 08:39:52AM -0500, Eric Blake wrote:
>> On 09/07/2018 02:31 AM, David Gibson wrote:
>>> From: Thomas Huth
>>>
>>> There is no known available OS for ppc around anymore that uses page
>>> sizes below 4k, so it does not make much sens
On Mon, Jul 30, 2018 at 04:11:34PM +0200, Cédric Le Goater wrote:
> The new layout using static IRQ number does not leave much space to
> the dynamic MSI range, only 0x100 IRQ numbers. Increase the total
> number of IRQS for newer machines and introduce a legacy XICS backend
> for pre-3.1 machines
On 09/08/2018 01:06 AM, Philippe Mathieu-Daudé wrote:
> Hi Cédric,
>
> On 8/31/18 7:38 AM, Cédric Le Goater wrote:
>> 0x should be returned for non implemented registers.
>>
>> Signed-off-by: Cédric Le Goater
>> ---
>> hw/ssi/aspeed_smc.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 d
> From: Paolo Bonzini [mailto:pbonz...@redhat.com]
> On 28/08/2018 09:23, Pavel Dovgalyuk wrote:
> > Hi, Paolo!
> >
> > Seems that this one breaks the record/replay.
>
> What are the symptoms?
Please look below.
> >> From: Paolo Bonzini [mailto:pbonz...@redhat.com]
> >> In the next patch, we wil
On Mon, Sep 03, 2018 at 09:25:43AM +0200, Roman Kapl wrote:
>
> On 08/31/2018 05:35 AM, David Gibson wrote:
> > On Tue, Aug 14, 2018 at 06:59:54PM +0200, Roman Kapl wrote:
> > > External PID is a mechanism present on BookE 2.06 that enables
> > > application to
> > > store/load data from differen
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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https://bugs.launchpad.net/bugs/1476183
Title:
can not cre
On Fri, Sep 07, 2018 at 08:39:52AM -0500, Eric Blake wrote:
> On 09/07/2018 02:31 AM, David Gibson wrote:
> > From: Thomas Huth
> >
> > There is no known available OS for ppc around anymore that uses page
> > sizes below 4k, so it does not make much sense that we keep wasting
> > our time on buil
On Sat, Sep 08, 2018 at 09:47:55AM +0100, Mark Cave-Ayland wrote:
> On 27/08/18 18:12, BALATON Zoltan wrote:
>
> > On Mon, 27 Aug 2018, Mark Cave-Ayland wrote:
> >> According to the PReP specification section 6.1.6 "System Interrupt
> >> Assignments", all PCI interrupts are routed via IRQ 15.
> >>
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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https://bugs.launchpad.net/bugs/1476800
Title:
Instant run
On Fri, Sep 07, 2018 at 03:19:54PM +0200, Thomas Huth wrote:
> The addition of the POWER9 CPUs divided the entries for the 970 CPUs,
> which is a little bit confusing when you look at the code. So let's
> re-group the 970 CPUs together again, and since these chips have been
> based on the POWER4 pr
On Sat, Sep 08, 2018 at 10:08:20AM +0100, Mark Cave-Ayland wrote:
> Whilst the PReP specification describes how all PCI IRQs are routed via IRQ
> 15 on the interrupt controller, the real 40p machine has routing quirk in
> that the LSI SCSI device is routed to IRQ 13.
>
> This is implemented using
On Sat, Sep 08, 2018 at 06:14:21PM +0200, Hervé Poussineau wrote:
> OpenBIOS gained 40p support in 5b20e4cacecb62fb2bdc6867c11d44cddd77c4ff
> Use it, instead of relying on an unmaintained and very limited firmware.
>
> Signed-off-by: Hervé Poussineau
Applied to ppc-for-3.1, thanks.
> ---
> Chan
On Sat, Sep 08, 2018 at 10:08:17AM +0100, Mark Cave-Ayland wrote:
11;rgb://> According to the PReP specification section 6.1.6
"System Interrupt
> Assignments", all PCI interrupts are routed via IRQ 15.
>
> In the case of the 40p machine this isn't quite true in that it has a routing
From: Philippe Mathieu-Daudé
When a container fails, it leaves a dangling tarball which name is
based on a timestamp. Further uses of make won't clean those files,
neither calling the 'docker-clean' target.
Use the .DELETE_ON_ERROR built-in target to let make remove those
temporary tarballs in c
From: Philippe Mathieu-Daudé
As recommended in
https://docs.docker.com/develop/develop-images/dockerfile_best-practices/#sort-multi-line-arguments
"This helps to avoid duplication of packages and make the
list much easier to update. This also makes PRs a lot easier
to read and review."
S
On Fri, 09/07 17:51, Kevin Wolf wrote:
> Am 09.08.2018 um 15:22 hat Fam Zheng geschrieben:
> > Furthermore, blocking aio_poll is only allowed on home thread
> > (in_aio_context_home_thread), because otherwise two blocking
> > aio_poll()'s can steal each other's ctx->notifier event and cause
> > han
From: Philippe Mathieu-Daudé
As recommended in
https://docs.docker.com/develop/develop-images/dockerfile_best-practices/#sort-multi-line-arguments
"This helps to avoid duplication of packages and make the
list much easier to update. This also makes PRs a lot easier
to read and review."
S
From: Philippe Mathieu-Daudé
As recommended in
https://docs.docker.com/develop/develop-images/dockerfile_best-practices/#sort-multi-line-arguments
"This helps to avoid duplication of packages and make the
list much easier to update."
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <2018
From: Philippe Mathieu-Daudé
As recommended in
https://docs.docker.com/develop/develop-images/dockerfile_best-practices/#sort-multi-line-arguments
"This helps to avoid duplication of packages and make the
list much easier to update. This also makes PRs a lot easier
to read and review."
S
The following changes since commit 19b599f7664b2ebfd0f405fb79c14dd241557452:
Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2018-08-27-v2'
into staging (2018-08-27 16:44:20 +0100)
are available in the Git repository at:
git://github.com/famz/qemu.git tags/docker-pull-request
On 2018年09月08日 04:48, Michael S. Tsirkin wrote:
On Fri, Aug 17, 2018 at 04:37:06PM +0800, Jason Wang wrote:
Sync linux headers to 5c60a7389d79 ("Merge tag 'for-linus-4.19-ofs1' of
git://git.kernel.org/pub/scm/linux/kernel/git/hubcap/linux").
Signed-off-by: Jason Wang
so there will be a new
Thanks Paolo,
Paolo Bonzini 于2018年9月10日周一 上午7:11写道：
> On 07/09/2018 08:32, Li Qiang wrote:
> > Hello all,
> >
> > I want to know why the i440FX in the following 'info qtree' information
> is
> > laid under the pci.0 bus. In the chip spec here:
> > -->https://wiki.qemu.org/images/b/bb/29054901.p
Hi Michael,
On 2018/9/8 5:30, Michael S. Tsirkin wrote:
> OK it is time to apply this.
Thanks.
> If I do I get latex errors (undefined and multiple-defined
> labels). Please post patches on top to fix this up,
> I will squash.
>
OK.
I'll keep working with the virtio-crypto spec and code.
>
On 28/08/2018 09:23, Pavel Dovgalyuk wrote:
> Hi, Paolo!
>
> Seems that this one breaks the record/replay.
What are the symptoms?
Paolo
>> From: Paolo Bonzini [mailto:pbonz...@redhat.com]
>> In the next patch, we will need to write cpu_ticks_offset from any
>> thread, even outside the BQL. Cur
On 01/09/2018 00:07, Emilio G. Cota wrote:
> On Mon, Aug 20, 2018 at 17:09:02 +0200, Paolo Bonzini wrote:
>> In the next patch, we will need to write cpu_ticks_offset from any
>> thread, even outside the BQL. Currently, it is protected by the BQL
>> just because cpu_enable_ticks and cpu_disable_ti
On 03/09/2018 19:18, Emilio G. Cota wrote:
> Using atomics here is a mistake since they're not guaranteed
> to compile.
But isn't it technically a C11 data race if you don't use atomics?
Could we make nocheck read/set degrade to just a volatile access when
used on a variable that is bigger than po
On 07/09/2018 08:32, Li Qiang wrote:
> Hello all,
>
> I want to know why the i440FX in the following 'info qtree' information is
> laid under the pci.0 bus. In the chip spec here:
> -->https://wiki.qemu.org/images/b/bb/29054901.pdf
> I don't see this device.
>
> Can anyone give me some hints?
On 24/08/2018 11:33, Peter Maydell wrote:
> ze);
> +
> + if (offset >= A_TIMERITCR) {
> + switch (offset) {
> + case A_TIMERITCR:
> + s->timeritcr = value & R_TIMERITCR_VALID_MASK;
> + cmsdk_apb_dualtimer_update(s);
> + case A_TIMERITOP:
> + s->timeritop = value & R_TIMERITOP_VALID_MASK;
> + cmsdk_
В Wed, 29 Aug 2018 21:30:56 +0300
Viktor Prutyanov пишет:
> We should map and use guest memory run by parts if it can't be mapped
> as a whole.
> After this patch, continuos guest physical memory blocks which are not
> continuos in host virtual address space will be processed correctly.
>
> Sign
> On Sep 9, 2018, at 1:34 PM, Stefan Weil wrote:
>
> Am 09.09.2018 um 17:32 schrieb John Arbuckle:
>> Currently the copyright date is set to 2017. Update the date to say
>> 2018.
>>
>> Signed-off-by: John Arbuckle
>> ---
>> include/qemu-common.h | 2 +-
>> 1 file changed, 1 insertion(+), 1 del
Am 09.09.2018 um 17:32 schrieb John Arbuckle:
> Currently the copyright date is set to 2017. Update the date to say
> 2018.
>
> Signed-off-by: John Arbuckle
> ---
> include/qemu-common.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/qemu-common.h b/include/qem
Currently the copyright date is set to 2017. Update the date to say
2018.
Signed-off-by: John Arbuckle
---
include/qemu-common.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/qemu-common.h b/include/qemu-common.h
index 85f4749aef..ed60ba251d 100644
--- a/include/qem
Well, thank you all for the discussions, we achieved some agreement,
and there are still things for further review.
The v3 patch has been sent out, we can move there and review/discuss
the updated patch now.
Thanks.
On 5 September 2018 at 23:00, Andrew Jones wrote:
> On Wed, Sep 05, 2018 at 10:0
For the Aarch64, there is one machine 'virt', it is primarily meant to
run on KVM and execute virtualization workloads, but we need an
environment as faithful as possible to physical hardware, for supporting
firmware and OS development for pysical Aarch64 machines.
This patch introduces new machin
Le 08/09/2018 à 20:22, Tony Garnock-Jones a écrit :
> Bring linux-user write(2) handling into line with linux for the case
> of a 0-byte write with a NULL buffer. Based on a patch originally
> written by Zhuowei Zhang.
>
> Addresses https://bugs.launchpad.net/qemu/+bug/1716292.
>
> From Zhuowei Z
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