On 2018-06-29 15:29, Luc Michel wrote:
> Add support for GICv2 virtualization extensions by mapping the necessary
> I/O regions and connecting the maintenance IRQ lines.
>
> Declare those additions in the device tree and in the ACPI tables.
>
> Signed-off-by: Luc Michel
> ---
> hw/arm/virt-acpi
On Wed, Jul 04, 2018 at 05:44:07PM -0300, Eduardo Habkost wrote:
> On Fri, Sep 01, 2017 at 12:53:31PM +0200, Gerd Hoffmann wrote:
> > Document how guest firmware is handled in qemu today.
> >
> > Reviewed-by: Laszlo Ersek
> > Signed-off-by: Gerd Hoffmann
>
> Is this document still valid? Shoul
Now that all machines which need cirrus explicitly select it qemu
doesn't need to consider it as default display any more. Drop it.
With this patch applied all ppc machine types will use "std" as default
display, no matter whenever cirrus-vga is compiled in or not.
Fixes: 29f9cef39e ppc: Include
Gerd Hoffmann (2):
vga: set default_display for all machines using cirrus.
vga: don't pick cirrus by default
hw/alpha/dp264.c | 1 +
hw/i386/pc_piix.c| 2 +-
hw/mips/mips_malta.c | 1 +
hw/mips/mips_r4k.c | 1 +
vl.c | 2 --
5 files changed, 4 insertions(+), 3 del
Explicitly set MachineClass->default_display to "cirrus" for all machine
types (alpha, mips, old i386 versions) which use cirrus today, so they
don't depend on cirrus being the default display device.
Signed-off-by: Gerd Hoffmann
---
hw/alpha/dp264.c | 1 +
hw/i386/pc_piix.c| 2 +-
hw/mi
> roms/config.vga-bochs-display:CONFIG_VGA_PCI=y
> roms/config.vga-cirrus:CONFIG_VGA_CIRRUS=y
> roms/config.vga-cirrus:CONFIG_VGA_PCI=y
> roms/config.vga-isavga:CONFIG_VGA_PCI=n
> roms/config.vga-qxl:CONFIG_VGA_PCI=y
> roms/config.vga-ramfb:CONFIG_VGA_PCI=n
> roms/config.vga-stdvga:CONFIG_VGA_PCI=y
> > -m->default_display = "std";
> > machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE);
>
> I wouldn't like to do this. Long term, it would be a good idea
> to have zero machines with default_display==NULL, so let's keep
> default_machine="std" on PC?
Fine with me, I'll send
On Thu, Jul 05, 2018 at 08:02:21AM +0200, Markus Armbruster wrote:
> Peter Xu writes:
>
> > When there is no parameter at all for a function prototype, return
> > "void" for the parameter list. This will happen after the next patch
> > where we removed the Error* for some of the emit functions.
Peter Xu writes:
> When there is no parameter at all for a function prototype, return
> "void" for the parameter list. This will happen after the next patch
> where we removed the Error* for some of the emit functions.
Error **, actually. Let's say
qapi: Fix build_params() for empty paramet
Hi,
qemu-system-ppc has an issue after building from the 3.1 branch. Mac
OS 9 hangs at the grey boot screen, OSX 10.3 hangs after verbose boot,
just before entering the graphical desktop.
Command line to reproduce:
qemu-system-ppc -L pc-bios -boot c -M mac99,via=pmu -m 512 -prom-env
'auto-boot?=
Hello Paolo,
On 07/04/2018 02:16 PM, Paolo Bonzini wrote:
> On 04/07/2018 11:55, Peter Xu wrote:
>>> commit b0e56e0b63f350691b52d3e75e89bb64143fbeff
>>> Author: Hu Tao
>>> Date: Wed Apr 2 15:13:27 2014 +0800
>>>
>>> unset RAMBlock idstr when unregister MemoryRegion
>>>
>>> S
On Wed, 20 Jun 2018 at 10:41, Michael S. Tsirkin wrote:
>
> On Wed, Jun 20, 2018 at 08:46:10AM +0800, Wanpeng Li wrote:
> > On Wed, 20 Jun 2018 at 08:07, Michael S. Tsirkin wrote:
> > >
> > > On Tue, Jun 19, 2018 at 05:07:46PM -0500, Eric Blake wrote:
> > > > On 06/19/2018 10:17 AM, Paolo Bonzini
> From: Emilio G. Cota [mailto:c...@braap.org]
> On Tue, Jul 03, 2018 at 08:38:52 +0300, Pavel Dovgalyuk wrote:
> > > From: Emilio G. Cota [mailto:c...@braap.org]
> > > On Mon, Jul 02, 2018 at 08:52:14 +0300, Pavel Dovgalyuk wrote:
> > > > The same failure can be reproduced with linux-0.2.img, whic
Peter Xu writes:
> When we reach monitor_qmp_setup_handlers_bh() we must be using the
> IOThread then, so no need to check against it any more. Instead, we
> assert.
>
> Signed-off-by: Peter Xu
> ---
> monitor.c | 13 -
> 1 file changed, 4 insertions(+), 9 deletions(-)
>
> diff --g
Philippe Mathieu-Daudé writes:
> Patch created mechanically by rerunning:
>
> $ spatch --sp-file scripts/coccinelle/round.cocci \
> --macro-file scripts/cocci-macro-file.h \
> --dir . --in-place
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> ui/vnc-enc-tight.c | 2
Philippe Mathieu-Daudé writes:
> Patch created mechanically by rerunning:
>
> $ spatch --sp-file scripts/coccinelle/typecast.cocci \
> --macro-file scripts/cocci-macro-file.h \
> --dir . --in-place
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/xen/xen_pt_config
Philippe Mathieu-Daudé writes:
> Patch created mechanically by rerunning:
>
> $ spatch --sp-file scripts/coccinelle/typecast.cocci \
> --macro-file scripts/cocci-macro-file.h \
> --dir . --in-place
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> tests/bios-tables-te
Philippe Mathieu-Daudé writes:
> Patch created mechanically by rerunning:
>
> $ spatch --sp-file scripts/coccinelle/round.cocci \
> --macro-file scripts/cocci-macro-file.h \
> --dir . --in-place
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/pci-host/piix.c | 2
Philippe Mathieu-Daudé writes:
> Patch created mechanically by rerunning:
>
> $ spatch --sp-file scripts/coccinelle/error_propagate_null.cocci \
> --macro-file scripts/cocci-macro-file.h \
> --dir . --in-place
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/s390x
Philippe Mathieu-Daudé writes:
> Patch created mechanically by rerunning:
>
> $ spatch --sp-file scripts/coccinelle/qobject.cocci \
> --macro-file scripts/cocci-macro-file.h \
> --dir . --in-place
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> qobject/block-qdict.c
On 07/04/2018 10:32 PM, Probir Roy wrote:
> I am writing a virtual device that would generate IRQ per CPU basis. I
Does 'per CPU basis' indicates irq per cpu, or irq per device queue?
AFAIK, the device may create multiple queues in the driver (in OS) and we would
have one irq (vector) per queu
Am 2018-07-04 23:04, schrieb Eduardo Habkost:
On Wed, Jul 04, 2018 at 05:52:06PM -0300, Eduardo Habkost wrote:
On Wed, Jul 04, 2018 at 10:21:19PM +0200, Sebastian Bauer wrote:
> Am 2018-07-04 20:53, schrieb Eduardo Habkost:
> > > mc->kvm_type = spapr_kvm_type;
> > > machine_class_allow
Test the postcopy recovery procedure by emulating a network failure
using migrate-pause command.
Signed-off-by: Peter Xu
---
tests/migration-test.c | 71 ++
1 file changed, 71 insertions(+)
diff --git a/tests/migration-test.c b/tests/migration-test.c
inde
Introduce helpers to query migration states and use it.
Signed-off-by: Peter Xu
---
tests/migration-test.c | 64 --
1 file changed, 43 insertions(+), 21 deletions(-)
diff --git a/tests/migration-test.c b/tests/migration-test.c
index af82a04789..1d85ccbef1
Separate the old postcopy UNIX socket test into three steps, provide a
helper for each step. With these helpers, we can do more compliated
tests like postcopy recovery, while keep the codes shared.
Signed-off-by: Peter Xu
---
tests/migration-test.c | 38 +++---
1
We dumped something when network failure happens. We should avoid those
messages to be dumped when running the tests:
$ ./tests/migration-test -p /x86_64/migration/postcopy/recovery
/x86_64/migration/postcopy/recovery: qemu-system-x86_64:
check_section_footer: Read section footer failed: -5
We were checking against -EIO, assuming that it will cover all IO
failures. But actually it is not. One example is that in
qemu_loadvm_section_start_full() we can have tons of places that will
return -EINVAL even if the error is caused by IO failures on the
network.
Let's loosen the recovery che
For example, we can pass in '"resume": true' to resume a migration.
Signed-off-by: Peter Xu
---
tests/migration-test.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/tests/migration-test.c b/tests/migration-test.c
index 2155869b96..af82a04789 100644
--- a/tests/
It's generalized from wait_for_migration_complete() to allow us to wait
for any migration status besides failure.
Signed-off-by: Peter Xu
---
tests/migration-test.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/tests/migration-test.c b/tests/migration-test.c
inde
The calculation on size of received bitmap is incorrect for postcopy
recovery. Here we wanted to let the size to cover all the valid bits in
the bitmap, we should use DIV_ROUND_UP() instead of a division.
For example, a RAMBlock with size=4K (which contains only one single 4K
page) will have nbit
Firstly, renaming the old matching_page_sizes variable to
matching_target_page_size, which suites more to what it did (it only
checks against target page size rather than multiple page sizes).
Meanwhile, simplify the check logic a bit, and enhance the comments.
Should have no functional change.
Si
Based-on: <20180627132246.5576-1-pet...@redhat.com>
Based on the series to unbreak postcopy:
Subject: [PATCH v3 0/4] migation: unbreak postcopy recovery
Message-Id: <20180627132246.5576-1-pet...@redhat.com>
This series introduce a new postcopy recovery test. The new test
actually helped me t
Currently, Qemu ACPI builder doesn't consider the non-memory NUMA nodes, eg:
-m 4G,slots=4,maxmem=8G \
-numa node,nodeid=0 \
-numa node,nodeid=1,mem=2G \
-numa node,nodeid=2,mem=2G \
-numa node,nodeid=3\
Guest Linux will report
[0.00] ACPI: SRAT: Node 0 PXM 0 [mem 0x-
On Wed, Jul 04, 2018 at 02:04:12PM +0200, Paolo Bonzini wrote:
> The vector cannot be negative. Coverity now reports this because it sees an
> array access before the check, in ioapic_stat_update_irq.
>
> Signed-off-by: Paolo Bonzini
Reviewed-by: Peter Xu
Thanks!
--
Peter Xu
On Wed, Jul 04, 2018 at 09:42:16AM -0400, Programmingkid wrote:
>
> > On Jul 3, 2018, at 11:31 PM, David Gibson
> > wrote:
> >
> > On Tue, Jul 03, 2018 at 08:17:25AM -0700, Richard Henderson wrote:
> >> Beginning with John Arbuckle's fdiv test case, clean up some
> >> of the fp helpers. As wit
On Wed, Jul 04, 2018 at 08:38:55PM +0200, Laurent Vivier wrote:
1;5202;0c> When I try to build a ppc64 target on a ppc64 host (gcc 8.1.1), I
have:
>
> .../target/ppc/int_helper.c: In function 'helper_vinsertb':
> .../target/ppc/int_helper.c:1954:32: error: array subscript
> 18446744073709551608
On Wed, Jul 04, 2018 at 06:40:35PM +0200, BALATON Zoltan wrote:
> On Wed, 4 Jul 2018, Philippe Mathieu-Daudé wrote:
> > Missed in 3c409c1927e, hopefully reported by Coverity.
>
> Apparently Coverity did report it and Paolo already notified me about that.
> I was about to send a patch but you were
On Wed, Jul 04, 2018 at 06:44:02PM -0300, Philippe Mathieu-Daudé wrote:
> On 07/04/2018 05:47 PM, Eduardo Habkost wrote:
> > On Wed, Jul 04, 2018 at 04:56:44PM -0300, Philippe Mathieu-Daudé wrote:
> >> On 06/28/2018 07:45 PM, Philippe Mathieu-Daudé wrote:
> >>> On 06/28/2018 03:36 PM, Alex Bennée w
On 07/04/2018 11:38 AM, Laurent Vivier wrote:
> When I try to build a ppc64 target on a ppc64 host (gcc 8.1.1), I have:
>
> .../target/ppc/int_helper.c: In function 'helper_vinsertb':
> .../target/ppc/int_helper.c:1954:32: error: array subscript
> 18446744073709551608 is above array bounds of 'ui
Hi,
This series failed docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
Type: series
Message-id: 20180704175006.519184-1-vsement...@virtuozzo.com
Subject: [Qemu-devel] [PATCH v2 0/4] fix
On 07/04/2018 04:51 PM, Will Deacon wrote:
Hi Suzuki,
On Fri, Jun 29, 2018 at 12:15:35PM +0100, Suzuki K Poulose wrote:
Allow specifying the physical address size for a new VM via
the kvm_type argument for KVM_CREATE_VM ioctl. This allows
us to finalise the stage2 page table format as early as
On 07/04/2018 05:47 PM, Eduardo Habkost wrote:
> On Wed, Jul 04, 2018 at 04:56:44PM -0300, Philippe Mathieu-Daudé wrote:
>> On 06/28/2018 07:45 PM, Philippe Mathieu-Daudé wrote:
>>> On 06/28/2018 03:36 PM, Alex Bennée wrote:
Philippe Mathieu-Daudé writes:
> On 06/28/2018 01:23 PM, Alex Be
On 3 July 2018 at 17:34, Alistair Francis wrote:
> The following changes since commit f988c7e191141e92de2059d04a5f9a9bb01f399c:
>
> Merge remote-tracking branch 'remotes/shorne/tags/pull-or-20180703' into
> staging (2018-07-03 16:04:41 +0100)
>
> are available in the Git repository at:
>
> g.
On Wed, Jul 04, 2018 at 05:52:06PM -0300, Eduardo Habkost wrote:
> On Wed, Jul 04, 2018 at 10:21:19PM +0200, Sebastian Bauer wrote:
> > Am 2018-07-04 20:53, schrieb Eduardo Habkost:
> > > > mc->kvm_type = spapr_kvm_type;
> > > > machine_class_allow_dynamic_sysbus_dev(mc,
> > > > TYPE_SPAP
On Wed, Jul 04, 2018 at 10:21:19PM +0200, Sebastian Bauer wrote:
> Am 2018-07-04 20:53, schrieb Eduardo Habkost:
> > > mc->kvm_type = spapr_kvm_type;
> > > machine_class_allow_dynamic_sysbus_dev(mc,
> > > TYPE_SPAPR_PCI_HOST_BRIDGE);
> > > mc->pci_allow_0_address = true;
> > > diff -
On 07/03/2018 04:51 PM, Stafford Horne wrote:
> Richard, how do you usually remove these before your pr? I suppose you have
> some kind of script?
No, I just edit the things by hand.
r~
On Wed, Jul 04, 2018 at 04:56:44PM -0300, Philippe Mathieu-Daudé wrote:
> On 06/28/2018 07:45 PM, Philippe Mathieu-Daudé wrote:
> > On 06/28/2018 03:36 PM, Alex Bennée wrote:
> >> Philippe Mathieu-Daudé writes:
> >>> On 06/28/2018 01:23 PM, Alex Bennée wrote:
[...]
> > +def test(self):
> >
On Fri, Sep 01, 2017 at 12:53:31PM +0200, Gerd Hoffmann wrote:
> Document how guest firmware is handled in qemu today.
>
> Reviewed-by: Laszlo Ersek
> Signed-off-by: Gerd Hoffmann
Is this document still valid? Should we apply this for QEMU 3.0?
> ---
> docs/firmware.txt | 49
MSR handling is the only place where CONTROL.nPRIV is modified.
Signed-off-by: Julia Suvorova
---
target/arm/helper.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 5ee229eb35..83cca554ad 100644
--- a/target/arm/helper.c
Hi Aleksandar,
On 07/04/2018 04:30 PM, Aleksandar Markovic wrote:
> From: Yongbok Kim
>
> BadVAddr should not be updated if (env->hflags & MIPS_HFLAG_DM) is
> set.
>
> Signed-off-by: Yongbok Kim
> Signed-off-by: Aleksandar Markovic
> Reviewed-by: Philippe Mathieu-Daudé
Watch out in
http://l
Hi Aleksandar,
On 07/04/2018 04:30 PM, Aleksandar Markovic wrote:
> From: Stefan Markovic
>
> Add CP0 BadInstrX register. This register will be used in nanoMIPS.
>
> Signed-off-by: Stefan Markovic
> Signed-off-by: Yongbok Kim
> Signed-off-by: Aleksandar Markovic
> Reviewed-by: Aleksandar Mar
Am 2018-07-04 20:53, schrieb Eduardo Habkost:
mc->kvm_type = spapr_kvm_type;
machine_class_allow_dynamic_sysbus_dev(mc,
TYPE_SPAPR_PCI_HOST_BRIDGE);
mc->pci_allow_0_address = true;
diff --git a/vl.c b/vl.c
index 16b913f9d5..e60bf2d6cd 100644
--- a/vl.c
+++ b/vl.c
@@ -4475,10 +447
Hi Aleksandar,
On 07/04/2018 04:30 PM, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Update CP0 registers Config0, Config1, and Config5 bit definitions.
>
> Some of these bits will be utilized by upcoming nanoMIPS changes.
>
> Signed-off-by: Aleksandar Markovic
> ---
> target/mi
Hi Aleksandar,
On 07/04/2018 04:30 PM, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> If checkpatch.pl is applied (using switch "-f") on file
> target/mips/msa_helper.c, it will hang.
>
> This is a workaround by correcting the source file. The workaround is
> found by partial deleti
Hi Aleksandar,
It's a bit funny you sent this email from yet another company, RT-RK =)
The mips.com is dead, long live the MIPS!
On 07/04/2018 04:30 PM, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Update email addresses of Aleksandar Markovic and Paul Burton in the
> MAINTAINERS
Julia Suvorova (2):
nvic: Handle ARMv6-M SCS reserved registers
tests: Add ARMv6-M reserved register test
hw/intc/armv7m_nvic.c | 69 +--
tests/Makefile.include| 2 +
tests/tcg/arm/test-reserved-reg.c | 60 +++
3 fil
Handle SCS reserved registers listed in ARMv6-M ARM D3.6.1.
All reserved registers are RAZ/WI.
Signed-off-by: Julia Suvorova
---
hw/intc/armv7m_nvic.c | 69 +++
1 file changed, 57 insertions(+), 12 deletions(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc
Check that reserved SCS registers return 0 at read,
and writes are ignored.
Based-on: <20180627143815.1829-1-j...@jms.id.au>
Based-on: <20180630091343.14391-1-stefa...@redhat.com>
Signed-off-by: Julia Suvorova
---
Test will work if Joel's patches will use ARMv6-M.
tests/Makefile.include
Hi Alex, Cleber.
On 06/28/2018 07:45 PM, Philippe Mathieu-Daudé wrote:
> On 06/28/2018 03:36 PM, Alex Bennée wrote:
>> Philippe Mathieu-Daudé writes:
>>> On 06/28/2018 01:23 PM, Alex Bennée wrote:
Philippe Mathieu-Daudé writes:
> Similar to the BootLinuxConsoleX86_64 test:
> bo
Cc'ing qemu-stable since the patch below is now in master:
2a8ceef ("target/ppc: set is_jmp on ppc_tr_breakpoint_check", 2018-07-03)
Please pick up the patch for QEMU 2.12.1 -- it fixes a regression
introduced in 2.12.0.
Thanks,
Emilio
On Mon, Jul 02, 2018 at 18:02:07 -0400, E
On Wed, Jul 04, 2018 at 09:21:06PM +0800, Jingqi Liu wrote:
> The MSR (33H) controls support for #AC exception
> for split locked accesses. When bit 29 of the MSR (33H)
> is set, the processor causes an #AC exception to
> be issued instead of suppressing LOCK on bus
> (during split lock access).
>
On Tue, Jul 03, 2018 at 08:38:52 +0300, Pavel Dovgalyuk wrote:
> > From: Emilio G. Cota [mailto:c...@braap.org]
> > On Mon, Jul 02, 2018 at 08:52:14 +0300, Pavel Dovgalyuk wrote:
> > > The same failure can be reproduced with linux-0.2.img, which was
> > > downloaded from QEMU site.
> > > I can't fi
From: Yongbok Kim
MFHC0 and MTHC0 used to handle EntryLo0 and EntryLo1 registers only,
and placing ELPA flag checks befor switch statement were technically
correct. However, after adding handling more registers, these checks
should be moved to act only in cases of handling EntryLo0 and
EntryLo1.
From: Yongbok Kim
BadVAddr should not be updated if (env->hflags & MIPS_HFLAG_DM) is
set.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Reviewed-by: Philippe Mathieu-Daudé
---
target/mips/helper.c| 4 +++-
target/mips/op_helper.c | 12 +---
2 files changed, 12 in
From: Yongbok Kim
WatchHi is extended by the field MemoryMapID with the GINVT instruction.
The field is accessible by MTHC0/MFHC0 in 32-bit architectures and DMTC0/
DMFC0 in 64-bit architectures.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
---
target/mips/cpu.h | 2 +-
From: Stefan Markovic
Add CP0 BadInstrX register. This register will be used in nanoMIPS.
Signed-off-by: Stefan Markovic
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Reviewed-by: Aleksandar Markovic
---
target/mips/cpu.h | 1 +
target/mips/machine.c | 5 +++--
tar
From: Aleksandar Markovic
Remove "range style" case statements to make code analysis easier.
This is needed also for some upcoming nanoMIPS-related refactorings.
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 257 +++-
1 file chang
From: Aleksandar Markovic
Update CP0 registers Config0, Config1, and Config5 bit definitions.
Some of these bits will be utilized by upcoming nanoMIPS changes.
Signed-off-by: Aleksandar Markovic
---
target/mips/cpu.h | 41 -
1 file changed, 28 insertion
From: Aleksandar Markovic
Update email addresses of Aleksandar Markovic and Paul Burton in the
MAINTAINERS file. Also, add corresponding items in the .mailmap file.
Signed-off-by: Aleksandar Markovic
---
.mailmap| 7 +--
MAINTAINERS | 9 +
2 files changed, 10 insertions(+), 6 d
From: Aleksandar Markovic
If checkpatch.pl is applied (using switch "-f") on file
target/mips/msa_helper.c, it will hang.
This is a workaround by correcting the source file. The workaround is
found by partial deleting and undeleting of the code in msa_helper.c
in binary search fashion.
The bug
From: Aleksandar Markovic
v2->v3:
- replaced invalid @imgtec.com and @mips.com in "From:",,
"Signed-off-by:", "Reviewed-by:" lines with the most current
email addresses for a particular person
- fixed build errors that appeared because of errors during integration
v1->v2:
- fixed
On Wed, Jul 04, 2018 at 01:28:59PM +0200, Gerd Hoffmann wrote:
> This reverts the stdvga vs. cirrus selection logic. Current state is
> that "cirrus" is the default and MachineClass->default_display is set to
> "std" by some machine types to override that.
>
> The patch makes "std" the default.
When I try to build a ppc64 target on a ppc64 host (gcc 8.1.1), I have:
.../target/ppc/int_helper.c: In function 'helper_vinsertb':
.../target/ppc/int_helper.c:1954:32: error: array subscript
18446744073709551608 is above array bounds of 'uint8_t[16]' {aka 'unsigned
char[16]'} [-Werror=array-bou
Hi,
This series failed build test on s390x host. Please find the details below.
Type: series
Message-id: 20180704175006.519184-1-vsement...@virtuozzo.com
Subject: [Qemu-devel] [PATCH v2 0/4] fix image fleecing
=== TEST SCRIPT BEGIN ===
#!/bin/bash
# Testing script will be invoked under the git c
Am 2018-07-04 13:28, schrieb Gerd Hoffmann:
This reverts the stdvga vs. cirrus selection logic. Current state is
that "cirrus" is the default and MachineClass->default_display is set
to
"std" by some machine types to override that.
The patch makes "std" the default. Setting default_display t
On 3 July 2018 at 15:59, Kevin Wolf wrote:
> The following changes since commit a395717cbd26e7593d3c3fe81faca121ec6d13e8:
>
> Merge remote-tracking branch 'remotes/cody/tags/block-pull-request' into
> staging (2018-07-03 11:49:51 +0100)
>
> are available in the git repository at:
>
> git://re
From: Aleksandar Markovic
Remove "range style" case statements to make code analysis easier.
This is needed also for some upcoming nanoMIPS-related refactorings.
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 257 +++-
1 file chang
From: Aleksandar Markovic
v1->v2:
- fixed recipient's email addresses
Maintenance issues, fixes, and improvements collected during recent
development. Some of them are related to the upcoming nanoMIPS changes.
Note: These patches are, of course, supposed to be applied AFTER soft
freeze.
Ale
From: Yongbok Kim
WatchHi is extended by the field MemoryMapID with the GINVT instruction.
The field is accessible by MTHC0/MFHC0 in 32-bit architectures and DMTC0/
DMFC0 in 64-bit architectures.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
---
target/mips/cpu.h | 2 +-
From: Yongbok Kim
BadVAddr should not be updated if (env->hflags & MIPS_HFLAG_DM) is
set.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Reviewed-by: Philippe Mathieu-Daudé
---
target/mips/helper.c| 4 +++-
target/mips/op_helper.c | 12 +---
2 files changed, 12 in
From: Aleksandar Markovic
Update CP0 registers Config0, Config1, and Config5 bit definitions.
Some of these bits will be utilized by upcoming nanoMIPS changes.
Signed-off-by: Aleksandar Markovic
---
target/mips/cpu.h | 41 -
1 file changed, 28 insertion
From: Aleksandar Markovic
If checkpatch.pl is applied (using switch "-f") on file
target/mips/msa_helper.c, it will hang.
This is a workaround by correcting the source file. The workaround is
found by partial deleting and undeleting of the code in msa_helper.c
in binary search fashion.
The bug
From: Stefan Markovic
Add CP0 BadInstrX register. This register will be used in nanoMIPS.
Signed-off-by: Stefan Markovic
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
---
target/mips/cpu.h | 1 +
target/mips/machine.c | 5 +++--
target/mips/translate.c | 20
From: Yongbok Kim
MFHC0 and MTHC0 used to handle EntryLo0 and EntryLo1 registers only,
and placing ELPA flag checks befor switch statement were technically
correct. However, after adding handling more registers, these checks
should be moved to act only in cases of handling EntryLo0 and
EntryLo1.
The current paths for modules are CONFIG_QEMU_MODDIR and paths relative
to the executable. Qemu and its modules can be installed and executed in
paths that are different from these search paths. This change allows
a search path to be specified by environment variable.
An example usage for this is
From: Aleksandar Markovic
Update email addresses of Aleksandar Markovic and Paul Burton in the
MAINTAINERS file. Also, add corresponding items in the .mailmap file.
Signed-off-by: Aleksandar Markovic
---
.mailmap| 7 +--
MAINTAINERS | 9 +
2 files changed, 10 insertions(+), 6 d
From: Aleksandar Markovic
Remove "range style" case statements to make code analysis easier.
This is needed also for some upcoming nanoMIPS-related refactorings.
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 257 +++-
1 file chang
From: Yongbok Kim
MFHC0 and MTHC0 used to handle EntryLo0 and EntryLo1 registers only,
and placing ELPA flag checks befor switch statement were technically
correct. However, after adding handling more registers, these checks
should be moved to act only in cases of handling EntryLo0 and
EntryLo1.
From: Aleksandar Markovic
If checkpatch.pl is applied (using switch "-f") on file
target/mips/msa_helper.c, it will hang.
This is a workaround by correcting the source file. The workaround is
found by partial deleting and undeleting of the code in msa_helper.c
in binary search fashion.
The bug
From: Aleksandar Markovic
Update email addresses of Aleksandar Markovic and Paul Burton in the
MAINTAINERS file. Also, add corresponding items in the .mailmap file.
Signed-off-by: Aleksandar Markovic
---
.mailmap| 7 +--
MAINTAINERS | 9 +
2 files changed, 10 insertions(+), 6 d
From: Aleksandar Markovic
Update CP0 registers Config0, Config1, and Config5 bit definitions.
Some of these bits will be utilized by upcoming nanoMIPS changes.
Signed-off-by: Aleksandar Markovic
---
target/mips/cpu.h | 41 -
1 file changed, 28 insertion
From: Stefan Markovic
Add CP0 BadInstrX register. This register will be used in nanoMIPS.
Signed-off-by: Stefan Markovic
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
---
target/mips/cpu.h | 1 +
target/mips/machine.c | 5 +++--
target/mips/translate.c | 20
From: Aleksandar Markovic
Maintenance issues, fixes, and improvements collected during recent
development. Some of them are related to the upcoming nanoMIPS changes.
Note: These patches are, of course, supposed to be applied AFTER soft
freeze.
Aleksandar Markovic (4):
target/mips: Update main
From: Yongbok Kim
BadVAddr should not be updated if (env->hflags & MIPS_HFLAG_DM) is
set.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Reviewed-by: Philippe Mathieu-Daudé
---
target/mips/helper.c| 4 +++-
target/mips/op_helper.c | 12 +---
2 files changed, 12 in
From: Yongbok Kim
WatchHi is extended by the field MemoryMapID with the GINVT instruction.
The field is accessible by MTHC0/MFHC0 in 32-bit architectures and DMTC0/
DMFC0 in 64-bit architectures.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
---
target/mips/cpu.h | 2 +-
On Wed, Jul 04, 2018 at 09:22:39PM +0800, Dou Liyang wrote:
> Commit 7a3099fc9c5c("numa: postpone options post-processing till
> machine_run_board_init()")
> broke the commit 7b8be49d36fc("NUMA: Enable adding NUMA node implicitly").
>
> The machine_run_board_init() doesn't do NUMA setup if nb_num
On Wed, Jul 04, 2018 at 03:38:32PM +0200, Paolo Bonzini wrote:
> On 04/07/2018 15:12, Jingqi Liu wrote:
> > Add the option split-lock-ac to control whether the #AC
> > exception is generated for split locked accesses, which
> > is introduced for the machine, there is an example to enable it:
> > -m
Hi all.
This fixes image fleecing scheme for 3.0, details are in 04 patch.
v2:
01,02: new patches
03: - improve comment
- fix assert in bdrv_aligned_pwritev
- add asserts to not use the flag on read requests
- support copy_range
04: - expand "detected cases" range
- s/fleecing/
Serialized writes should be used in copy-on-write of backup(sync=none)
for image fleecing scheme.
We need to change an assert in bdrv_aligned_pwritev, added in
28de2dcd88de. The assert may fail now, because call to
wait_serialising_requests here may become first call to it for this
request with se
Fleecing scheme works as follows: we want a kind of temporary snapshot
of active drive A. We create temporary image B, with B->backing = A.
Then we start backup(sync=none) from A to B. From this point, B reads
as point-in-time snapshot of A (A continues to be active drive,
accepting guest IO).
Thi
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