There was a nasty flip in identifying which register group an access is
targeting. The issue caused spuriously raised priorities of the guest
when handing CPUs over in the Jailhouse hypervisor.
Signed-off-by: Jan Kiszka
---
hw/intc/arm_gicv3_cpuif.c | 12 ++--
1 file changed, 6 insertion
Babu,
If num_sharing_l3_cache() uses MAX_NODES_EPYC, then that function It’s EPYC
specific.
An alternative would be to use a data member (e.g., max_nodes_per_socket)) that
get initialized (via another helper function) to MAX_NODES_EPYC.
Basically, ideally the functions that return CPUID inform
v2.4 is not maintained anymore, so closing this as WONTFIX.
** Changed in: qemu
Status: New => Won't Fix
--
You received this bug notification because you are a member of qemu-
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https://bugs.launchpad.net/bugs/1772166
Title:
qemu 2.4.1: dereferenci
> Maybe we should add a parameter to the pxb-pci device specifying the PCI
domain
> instead of adding it on the fly. It will help ensuring the PCI domain
will not change over
> time due to code changes.In this case "bus sharing" should be off. For
the moment
> the pxb devices get the bus range from
> An interesting point is if we want to limit the MMFCG size for PXBs, as
we may not be
> interested to use all the buses in a specific domain.
OK, perhaps providing an option for the user to specify the desired bus
numbers?
> For each bus we require some address space that remains unused.
Does
On 19.05.2018 13:36, Peter Maydell wrote:
> On 19 May 2018 at 07:10, Thomas Huth wrote:
>> On 18.05.2018 20:31, Peter Maydell wrote:
>>> Another flaky test for the collection:
>>>
>>> TEST: tests/boot-serial-test... (pid=25144)
>>> /sparc64/boot-serial/sun4u:
> have no objection here, we'll see later how the modification helps.
The purpose is to place the q35 host at the start of queue. In the original
QLIST,
when a new pxb host is added, q35 host will be bumped to the end end list.
By replacing it with QTAILQ, we can always get q35 host bridges firs
Hi Marcel,
Thanks a lot for your feedback.
> I don't think we should try to place the MMCFGs before 4G even if there
> is enough room. Is better to place them always after 4G.
>
> "above_4g_mem" PCI hole it is reserved for PCI devices hotplug. We cannot
use if for
> MMCFGs. What I think we can do
On 05/14/2018 12:38 PM, Peter Maydell wrote:
> On 9 May 2018 at 07:01, Philippe Mathieu-Daudé wrote:
>> [based on a patch from Alistair Francis
>> from qemu/xilinx tag xilinx-v2015.2]
>> Signed-off-by: Edgar E. Iglesias
>> [PMD: rebased, changed magic by definitions, use stw_be_p, add tracing,
On Tue, May 22, 2018 at 11:56:27AM +0800, Peter Xu wrote:
> v2:
> - for patch 1: replace tabs, add trivial comment [Markus]
> (I didn't add much comment otherwise I'll need to duplicate what's
>there in error_report())
> - add patch 2
>
> Patch 1 introduce the helpers.
>
> Patch 2 use it to
Hi Peter,
On 03/12/2018 10:16 AM, Peter Maydell wrote:
> On 12 March 2018 at 13:03, Philippe Mathieu-Daudé wrote:
>> On 03/09/2018 06:03 PM, Peter Maydell wrote:
>>> I think the spec says that if the guest makes an invalid selection
>>> for one function in the group then we must ignore all the se
Replace existing trace_vtd_err() with error_report_once() then stderr
will capture something if any of the error happens, meanwhile we don't
suffer from any DDOS. Then remove the trace point.
Signed-off-by: Peter Xu
---
hw/i386/intel_iommu.c | 34 +-
hw/i386/trac
v2:
- for patch 1: replace tabs, add trivial comment [Markus]
(I didn't add much comment otherwise I'll need to duplicate what's
there in error_report())
- add patch 2
Patch 1 introduce the helpers.
Patch 2 use it to replace VT-d trace_vtd_err().
Please review. Thanks.
Peter Xu (2):
qem
I stole the printk_once() macro.
I always wanted to be able to print some error directly if there is a
buffer to dump, however we can't use error_report() where the code path
can be triggered by DDOS attack. To avoid that, we can introduce a
print-once-like function for it. Meanwhile, we also in
On Thu, Apr 12, 2018 at 02:11:08PM +0800, Peter Xu wrote:
> In the future the monitor iothread may be accessing the cur_mon as
> well (via monitor_qmp_dispatch_one()). Before we introduce a real
> Out-Of-Band command, let's convert the cur_mon variable to be a
> per-thread variable to make sure th
On Wed, Apr 25, 2018 at 10:54:55AM +0800, Peter Xu wrote:
> v6:
> - rename __QEMU_THREAD_COMMON_H__ to QEMU_THREAD_COMMON_H
> - collect r-bs for Emilio
Ping.
It's fine if we don't really want this, but in case if this falls
through the cracks...
Regards,
--
Peter Xu
On Mon, May 21, 2018 at 09:13:06AM -0500, Eric Blake wrote:
> On 05/21/2018 03:42 AM, Peter Xu wrote:
> > We turned Out-Of-Band feature of monitors off for 2.12 release. Now we
> > try to turn that on again.
>
> "try to turn" sounds weak, like you aren't sure of this patch. If you
> aren't sure,
On Mon, May 21, 2018 at 03:03:49PM +0100, Peter Maydell wrote:
> If an IOMMU supports mappings that care about the memory
> transaction attributes, then it no longer has a unique
> address -> output mapping, but more than one. We can
> represent these using an IOMMU index, analogous to TCG's
> mmu
Add information for cpuid 0x801D leaf. Populate cache topology information
for different cache types(Data Cache, Instruction Cache, L2 and L3) supported
by 0x801D leaf. Please refer Processor Programming Reference (PPR) for AMD
Family 17h Model for more details.
Signed-off-by: Babu Moger
This series enables the TOPOEXT feature for AMD CPUs. This is required to
support hyperthreading on kvm guests.
This addresses the issues reported in these bugs:
https://bugzilla.redhat.com/show_bug.cgi?id=1481253
https://bugs.launchpad.net/qemu/+bug/1703506
v10:
Based the patches on Eduardo's
Remove generic non-intel check while validating hyperthreading support.
Certain AMD CPUs can support hyperthreading now.
CPU family with TOPOEXT feature can support hyperthreading now.
Signed-off-by: Babu Moger
Tested-by: Geoffrey McRae
Reviewed-by: Eduardo Habkost
---
target/i386/cpu.c | 15
Enable TOPOEXT feature on EPYC CPU. This is required to support
hyperthreading on VM guests. Also extend xlevel to 0x801E.
Disable TOPOEXT feature for legacy machines and also disable
TOPOEXT feature if the config cannot be supported.
Signed-off-by: Babu Moger
---
include/hw/i386/pc.h | 4
From: Eduardo Habkost
Always initialize CPUCaches structs with cache information, even
if legacy_cache=true. Use different CPUCaches struct for
CPUID[2], CPUID[4], and the AMD CPUID leaves.
This will simplify a lot the logic inside cpu_x86_cpuid().
Signed-off-by: Eduardo Habkost
Signed-off-by
Add support for cpuid leaf CPUID_8000_001E. Build the config that closely
match the underlying hardware. Please refer Processor Programming Reference
(PPR) for AMD Family 17h Model for more details.
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 85
On 05/21/2018 07:03 AM, Peter Maydell wrote:
> As part of plumbing MemTxAttrs down to the IOMMU translate method,
> add MemTxAttrs as an argument to tb_invalidate_phys_addr().
> Its callers either have an attrs value to hand, or don't care
> and can use MEMTXATTRS_UNSPECIFIED.
>
> Signed-off-by: P
This applies to both user-mode and !user-mode emulation.
Instead of relying on a global lock, protect the list of incoming
jumps with tb->jmp_lock. This lock also protects tb->cflags,
so update all tb->cflags readers outside tb->jmp_lock to use
atomic reads via tb_cflags().
In order to find the d
This is only compiled under CONFIG_DEBUG_TCG to avoid
bloating the binary.
In user-mode, assert_page_locked is equivalent to assert_mmap_lock.
Note: There are some tb_lock assertions left that will be
removed by later patches.
Suggested-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
accel/
This paves the way for enabling scalable parallel generation of TCG code.
Instead of tracking TBs with a single binary search tree (BST), use a
BST for each TCG region, protecting it with a lock. This is as scalable
as it gets, since each TCG thread operates on a separate region.
The core of this
Groundwork for supporting parallel TCG generation.
Instead of using a global lock (tb_lock) to protect changes
to pages, use fine-grained, per-page locks in !user-mode.
User-mode stays with mmap_lock.
Sometimes changes need to happen atomically on more than one
page (e.g. when a TB that spans acr
tb_lock was needed when the function did retranslation. However,
since fca8a500d519 ("tcg: Save insn data and use it in
cpu_restore_state_from_tb") we don't do retranslation.
Get rid of the comment.
Reviewed-by: Richard Henderson
Signed-off-by: Emilio G. Cota
---
accel/tcg/translate-all.c | 1
The meaning of "existing" is now changed to "matches in hash and
ht->cmp result". This is saner than just checking the pointer value.
Suggested-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Emilio G. Cota
---
include/qemu/qht.h| 7 +--
accel/tcg/translate-al
Use the recently-gained QHT feature of returning the matching TB if it
already exists. This allows us to get rid of the lookup we perform
right after acquiring tb_lock.
Suggested-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Emilio G. Cota
---
docs/devel/multi-thread-tcg.
So that we pass a same-page range to tb_invalidate_phys_page_range,
instead of always passing an end address that could be on a different
page.
As discussed with Peter Maydell on the list [1], tb_invalidate_phys_page_range
doesn't actually do much with 'end', which explains why we have never
hit a
This commit does several things, but to avoid churn I merged them all
into the same commit. To wit:
- Use uintptr_t instead of TranslationBlock * for the list of TBs in a page.
Just like we did in (c37e6d7e "tcg: Use uintptr_t type for
jmp_list_{next|first} fields of TB"), the rationale is the
The acquisition of tb_lock was added when the async tlb_flush
was introduced in e3b9ca810 ("cputlb: introduce tlb_flush_* async work.")
tb_lock was there to allow us to do memset() on the tb_jmp_cache's.
However, since f3ced3c5928 ("tcg: consistently access cpu->tb_jmp_cache
atomically") all acces
Use mmap_lock in user-mode to protect TCG state and the page
descriptors.
In !user-mode, each vCPU has its own TCG state, so no locks
needed. Per-page locks are used to protect the page descriptors.
Per-TB locks are used in both modes to protect TB jumps.
Some notes:
- tb_lock is removed from no
This greatly simplifies next commit's diff.
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
accel/tcg/translate-all.c | 77 ---
1 file changed, 39 insertions(+), 38 deletions(-)
diff --git a/accel/tcg/transl
qht_lookup now uses the default cmp function. qht_lookup_custom is defined
to retain the old behaviour, that is a cmp function is explicitly provided.
qht_insert will gain use of the default cmp in the next patch.
Note that we move qht_lookup_custom's @func to be the last argument,
which makes th
Thereby making it per-TCGContext. Once we remove tb_lock, this will
avoid an atomic increment every time a TB is invalidated.
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
include/exec/tb-context.h | 1 -
tcg/tcg.h | 3 +++
accel/tc
Groundwork for supporting parallel TCG generation.
We never remove entries from the radix tree, so we can use cmpxchg
to implement lockless insertions.
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
docs/devel/multi-thread-tcg.txt | 4 ++--
accel/tc
The appended adds assertions to make sure we do not longjmp with page
locks held. Note that user-mode has nothing to check, since page_locks
are !user-mode only.
Signed-off-by: Emilio G. Cota
---
include/exec/exec-all.h | 8
accel/tcg/cpu-exec.c | 1 +
accel/tcg/translate-all.c |
Groundwork for supporting parallel TCG generation.
Move the hole to the end of the struct, so that a u32
field can be added there without bloating the struct.
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
accel/tcg/translate-all.c | 2 +-
1 file cha
v2: https://lists.nongnu.org/archive/html/qemu-devel/2018-04/msg00656.html
Changes since v2:
- rebase onto master, fixing conflicts
- add R-b's
- add a missing page_lock to page_collection_lock
- add a couple of missing assert_page_locked assertions
- add page_lock_pair, as suggested by Alex
On 05/21/2018 07:33 PM, Alistair Francis wrote:
> On Sun, May 20, 2018 at 8:16 PM, Fam Zheng wrote:
>> On Fri, 05/18 11:34, Alistair Francis wrote:
>>> Avocado is not trivial to setup on non-Fedora systems. To simplfying
>>> future testing add a docker test image that runs Avocado tests.
>>>
>>> S
On 05/21/2018 07:37 PM, Alistair Francis wrote:
> On Mon, May 21, 2018 at 10:26 AM, Philippe Mathieu-Daudé
> wrote:
>> Hi Alistair, Fam,
>>
>> On 05/21/2018 12:16 AM, Fam Zheng wrote:
>>> On Fri, 05/18 11:34, Alistair Francis wrote:
Avocado is not trivial to setup on non-Fedora systems. To si
Hi I'm a privacy distro maintainer investigating the implications of the
newly published nethammer attack [0] on KVM guests particularly the
virtio-net drivers. The summary of the paper is that rowhammer can be
remotely triggered by feeding susceptible* network driver crafted
traffic. This attack
On Mon, May 21, 2018 at 10:26 AM, Philippe Mathieu-Daudé
wrote:
> Hi Alistair, Fam,
>
> On 05/21/2018 12:16 AM, Fam Zheng wrote:
>> On Fri, 05/18 11:34, Alistair Francis wrote:
>>> Avocado is not trivial to setup on non-Fedora systems. To simplfying
>>> future testing add a docker test image that
On Sun, May 20, 2018 at 8:16 PM, Fam Zheng wrote:
> On Fri, 05/18 11:34, Alistair Francis wrote:
>> Avocado is not trivial to setup on non-Fedora systems. To simplfying
>> future testing add a docker test image that runs Avocado tests.
>>
>> Signed-off-by: Alistair Francis
>> ---
>> v2:
>> - Add
From: Daniel P. Berrangé
New microcode introduces the "Speculative Store Bypass Disable"
CPUID feature bit. This needs to be exposed to guest OS to allow
them to protect against CVE-2018-3639.
Signed-off-by: Daniel P. Berrangé
Reviewed-by: Konrad Rzeszutek Wilk
Signed-off-by: Konrad Rzeszutek
From: Konrad Rzeszutek Wilk
AMD Zen expose the Intel equivalant to Speculative Store Bypass Disable
via the 0x8008_EBX[25] CPUID feature bit.
This needs to be exposed to guest OS to allow them to protect
against CVE-2018-3639.
Signed-off-by: Konrad Rzeszutek Wilk
Reviewed-by: Daniel P. Ber
From: Konrad Rzeszutek Wilk
"Some AMD processors only support a non-architectural means of enabling
speculative store bypass disable (SSBD). To allow a simplified view of
this to a guest, an architectural definition has been created through a new
CPUID bit, 0x8008_EBX[25], and a new MSR, 0xc
This provides the QEMU part of the mitigations for the speculative
store buffer bypass vulnerabilities on the x86 platform[1], and is
the companion of the kernel patches merged in:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=3b78ce4a34b761c7fe13520de822984019ff
On Mon, May 21, 2018 at 10:54:21PM +0100, Daniel P. Berrangé wrote:
> This provides the QEMU part of the mitigations for the speculative
> store buffer bypass vulnerabilities on the x86 platform[1], and is
> the companion of the kernel patches merged in:
>
>
> https://git.kernel.org/pub/scm/lin
This provides the QEMU part of the mitigations for the speculative
store buffer bypass vulnerabilities on the x86 platform[1], and is
the companion of the kernel patches merged in:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=3b78ce4a34b761c7fe13520de822984019ff
New microcode introduces the "Speculative Store Bypass Disable"
CPUID feature bit. This needs to be exposed to guest OS to allow
them to protect against CVE-2018-3639.
Signed-off-by: Daniel P. Berrangé
Reviewed-by: Konrad Rzeszutek Wilk
Signed-off-by: Konrad Rzeszutek Wilk
---
target/i386/cpu.
From: Konrad Rzeszutek Wilk
"Some AMD processors only support a non-architectural means of enabling
speculative store bypass disable (SSBD). To allow a simplified view of
this to a guest, an architectural definition has been created through a new
CPUID bit, 0x8008_EBX[25], and a new MSR, 0xc
From: Konrad Rzeszutek Wilk
AMD Zen expose the Intel equivalant to Speculative Store Bypass Disable
via the 0x8008_EBX[25] CPUID feature bit.
This needs to be exposed to guest OS to allow them to protect
against CVE-2018-3639.
Signed-off-by: Konrad Rzeszutek Wilk
Reviewed-by: Daniel P. Ber
On Mon, May 21, 2018 at 09:18:17PM +0100, Daniel P. Berrangé wrote:
> On Fri, May 18, 2018 at 02:41:33PM -0300, Eduardo Habkost wrote:
> > On Fri, May 18, 2018 at 06:09:56PM +0100, Daniel P. Berrangé wrote:
> > > On Fri, May 18, 2018 at 06:30:38PM +0300, Michael S. Tsirkin wrote:
> > > > Hi!
> > >
On Mon, May 21, 2018 at 04:46:36PM -0300, Daniel Henrique Barboza wrote:
>
>
> On 05/21/2018 03:14 PM, Eduardo Habkost wrote:
> > > Issue#2: the flag isn't a property of the target. Due to -no-acpi, it's
> > > not even a property of the machine type. If it was, query-machines
> > > would be the
On Fri, May 18, 2018 at 02:41:33PM -0300, Eduardo Habkost wrote:
> On Fri, May 18, 2018 at 06:09:56PM +0100, Daniel P. Berrangé wrote:
> > On Fri, May 18, 2018 at 06:30:38PM +0300, Michael S. Tsirkin wrote:
> > > Hi!
> > > Right now, QEMU supports multiple machine types within
> > > a given archite
On 05/21/2018 10:27 AM, Peter Maydell wrote:
> The FRECPX instructions should (like most other floating point operations)
> honour the FPCR.FZ bit which specifies whether input denormals should
> be flushed to zero (or FZ16 for the half-precision version).
> We forgot to implement this, which doesn
On 05/21/2018 03:14 PM, Eduardo Habkost wrote:
Issue#2: the flag isn't a property of the target. Due to -no-acpi, it's
not even a property of the machine type. If it was, query-machines
would be the natural owner of the flag.
Perhaps query-machines is still the proper owner. The value of
wa
From: Paul Durrant
Now that the (native or emulated) xen_be_copy_grant_refs() helper is
always available, the xen_disk code can be significantly simplified by
removing direct use of grant map and unmap operations.
Signed-off-by: Paul Durrant
Acked-by: Anthony Perard
Signed-off-by: Stefano Stab
From: Paul Durrant
Certain functions in xen_disk are called with a pointer to xendev
(struct XenDevice *). They then use container_of() to acces the surrounding
blkdev (struct XenBlkDev) but then in various places use &blkdev->xendev
when use of the original xendev pointer is shorter to express a
On 05/21/2018 07:03 AM, Peter Maydell wrote:
> Add more detail to the documentation for memory_region_init_iommu()
> and other IOMMU-related functions and data structures.
>
> Signed-off-by: Peter Maydell
> ---
> v2->v3 changes:
> * minor wording tweaks per Eric's review
> * moved the bit about
From: Paul Durrant
Now that helpers are present in xen_backend, this patch removes open-coded
calls to libxengnttab from the xen_disk code.
This patch also fixes one whitspace error in the assignment of the
XenDevOps initialise method.
Signed-off-by: Paul Durrant
Acked-by: Anthony Perard
Sign
From: Anthony PERARD
Signed-off-by: Anthony PERARD
Reviewed-by: Markus Armbruster
Signed-off-by: Stefano Stabellini
---
configure | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configure b/configure
index 59f91ab..a8498ab 100755
--- a/configure
+++ b/configure
@@ -1588,7
From: Paul Durrant
Now that helpers are available in xen_backend, use them throughout all
Xen PV backends.
Signed-off-by: Paul Durrant
Acked-by: Anthony Perard
Signed-off-by: Stefano Stabellini
---
hw/9pfs/xen-9p-backend.c | 32 +++-
hw/char/xen_console.c| 9
From: Paul Durrant
xen_handle
and some define additional handle types of the form:
xen__handle
Examples of these are xenforeignmemory_handle and
xenforeignmemory_resource_handle.
Both of these types will be misparsed by checkpatch if they appear as the
first token in a line since, as types de
From: Paul Durrant
Since xen_disk now always copies data to and from a guest there is no need
to maintain a vector entry corresponding to every page of a request.
This means there is less per-request state to maintain so the ioreq
structure can shrink significantly.
Signed-off-by: Paul Durrant
From: Paul Durrant
Currently the xen_disk source has to carry #ifdef exclusions to compile
against Xen older then 4.8. This is a bit messy so this patch lifts the
definition of struct xengnttab_grant_copy_segment and adds it into the
pre-4.8 compat area in xen_common.h, which allows xen_disk to b
From: Paul Durrant
There is no longer any use of this flag outside of the xen_backend code.
Signed-off-by: Paul Durrant
Acked-by: Anthony Perard
Signed-off-by: Stefano Stabellini
---
hw/xen/xen_backend.c | 2 +-
include/hw/xen/xen_backend.h | 1 -
2 files changed, 1 insertion(+), 2 d
From: Paul Durrant
The code is sufficiently substantial that it improves code readability
to put it in a new function called by xen_hvm_init() rather than having
it inline.
Signed-off-by: Paul Durrant
Reviewed-by: Anthony Perard
Signed-off-by: Stefano Stabellini
---
hw/i386/xen/xen-hvm.c | 7
From: Igor Druzhinin
Commit 99605175c (xen-pt: Fix PCI devices re-attach failed) introduced
a subtle bug. As soon as the guest switches off Bus Mastering on the
device it immediately causes all the BARs be unmapped due to the DMA
address space of the device being changed. This is undesired behavi
From: Paul Durrant
Not all Xen environments support the xengnttab_grant_copy() operation.
E.g. where the OS is FreeBSD or Xen is older than 4.8.0.
This patch introduces an emulation of that operation using
xengnttab_map_domain_grant_refs() and memcpy() for those environments.
Signed-off-by: Pau
From: Igor Druzhinin
This should help to avoid problems with accessing the device after
migration/resume without PV drivers by migrating its PCI configuration
space state. Without an explicitly defined state record it resets
every time a VM migrates which confuses the OS and makes every
access to
From: Paul Durrant
This patch adds grant table helper functions to the xen_backend code to
localize error reporting and use of xen_domid.
The patch also defers the call to xengnttab_open() until just before the
initialise method in XenDevOps is invoked. This method is responsible for
mapping the
From: Ross Lagerwall
The full size of the BAR is stored in the lower PCIIORegion.size. The
upper PCIIORegion.size is 0. Calculate the size of the upper half
correctly from the lower half otherwise the size read by the guest will
be incorrect.
Signed-off-by: Ross Lagerwall
Acked-by: Anthony PER
ttp/people/sstabellini/qemu-dm.git
tags/xen-20180521-tag
for you to fetch changes up to f03df99f09ee0ca27ea2298a1b77438e7999044d:
xen_disk: be consistent with use of xendev and blkdev->xendev (2018-05-18
11:13:01 -0700)
X
On Mon, May 21, 2018 at 07:44:40PM +0100, Daniel P. Berrangé wrote:
> On Mon, May 21, 2018 at 03:29:28PM -0300, Eduardo Habkost wrote:
> > On Sat, May 19, 2018 at 08:05:06AM +0200, Markus Armbruster wrote:
> > > Eduardo Habkost writes:
> > >
> > > [...]
> > > > About being more expressive than ju
On Mon, May 21, 2018 at 03:29:28PM -0300, Eduardo Habkost wrote:
> On Sat, May 19, 2018 at 08:05:06AM +0200, Markus Armbruster wrote:
> > Eduardo Habkost writes:
> >
> > [...]
> > > About being more expressive than just a single list of key,value
> > > pairs, I don't see any evidence of that bein
On Sat, May 19, 2018 at 08:05:06AM +0200, Markus Armbruster wrote:
> Eduardo Habkost writes:
>
> [...]
> > About being more expressive than just a single list of key,value
> > pairs, I don't see any evidence of that being necessary for the
> > problems we're trying to address.
>
> Short history
On 05/21/2018 12:32 PM, Philippe Mathieu-Daudé wrote:
tests/test-block-backend
+test-block-backend
test-blockjob
test-blockjob-txn
test-bufferiszero
What about using gitignore negated pattern in tests/?
Or, what we've threatened to do in the past: rename all unit tests to
On Fri, May 18, 2018 at 10:48:31AM +0200, Markus Armbruster wrote:
> Cc'ing a few more people.
>
> Daniel Henrique Barboza writes:
>
> > When issuing the qmp/hmp 'system_wakeup' command, what happens in a
> > nutshell is:
> >
> > - qmp_system_wakeup_request set runstate to RUNNING, sets a wakeup
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180519092956.15134-1-laur...@vivier.eu
Subject: [Qemu-devel] [PATCH v3 0/8] linux-user: move socket.h definitions to
CPU directories
=== TEST SCRIPT BEGIN ===
#!/bin/bash
On 05/21/2018 01:41 PM, Eric Blake wrote:
> On 05/21/2018 11:32 AM, Ross Zwisler wrote:
>> After a "make check" we end up with the following:
>>
>> $ git status
>> On branch master
>> Your branch is up-to-date with 'origin/master'.
>>
>> Untracked files:
>> (use "git add ..." to include in what
The FRECPX instructions should (like most other floating point operations)
honour the FPCR.FZ bit which specifies whether input denormals should
be flushed to zero (or FZ16 for the half-precision version).
We forgot to implement this, which doesn't affect the results (since
the calculation doesn't
Hi Alistair, Fam,
On 05/21/2018 12:16 AM, Fam Zheng wrote:
> On Fri, 05/18 11:34, Alistair Francis wrote:
>> Avocado is not trivial to setup on non-Fedora systems. To simplfying
>> future testing add a docker test image that runs Avocado tests.
Can you add an entry in the "make docker" help menu?
On 05/21/2018 11:32 AM, Ross Zwisler wrote:
After a "make check" we end up with the following:
$ git status
On branch master
Your branch is up-to-date with 'origin/master'.
Untracked files:
(use "git add ..." to include in what will be committed)
tests/test-block-backend
nothing ad
Hello,
It's been about a week since the last email to my patches, in case anyone would
like to review but missed them.
Patches are the following on patchwork:
http://patchwork.ozlabs.org/patch/912281/
http://patchwork.ozlabs.org/patch/912282/
And the following on patchew:
http://patchew.org/QEMU
Add a machine command line option to allow the user to control the Platform
Capabilities Structure in the virtualized NFIT. This Platform Capabilities
Structure was added in ACPI 6.2 Errata A.
Signed-off-by: Ross Zwisler
---
docs/nvdimm.txt | 27 +++
hw/acpi/nvdi
After a "make check" we end up with the following:
$ git status
On branch master
Your branch is up-to-date with 'origin/master'.
Untracked files:
(use "git add ..." to include in what will be committed)
tests/test-block-backend
nothing added to commit but untracked files present (use
Signed-off-by: Ross Zwisler
Fixes: commit da6789c27c2e ("nvdimm: add a macro for property "label-size"")
Reviewed-by: Stefan Hajnoczi
Reviewed-by: Igor Mammedov
Cc: Haozhong Zhang
Cc: Michael S. Tsirkin
Cc: Stefan Hajnoczi
---
hw/mem/nvdimm.c | 2 +-
include/hw/mem/nvdimm.h | 2 +-
2
Add testing for the newly added NFIT Platform Capabilities Structure.
Signed-off-by: Ross Zwisler
Suggested-by: Igor Mammedov
---
tests/acpi-test-data/pc/NFIT.dimmpxm | Bin 224 -> 240 bytes
tests/acpi-test-data/q35/NFIT.dimmpxm | Bin 224 -> 240 bytes
tests/bios-tables-test.c |
Changes since v3:
* Updated the text in docs/nvdimm.txt to make it clear that the value
being passed in on the command line in an integer made up of various
bit fields. (Rob Elliott)
* Updated the "Highest Valid Capability" byte to be dynamic based on
the highest valid bit in the user'
This is a second attempt at sending this patch:
http://lists.nongnu.org/archive/html/qemu-devel/2018-05/msg04697.html
Signed-off-by: Pavel Balaev
---
io/channel-socket.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/io/channel-socket.c b/io/channel-socke
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180521140402.23318-1-peter.mayd...@linaro.org
Subject: [Qemu-devel] [PATCH 00/27] iommu: support txattrs, support TCG
execution, implement TZ MPC
=== TEST SCRIPT BEGIN ===
On Fri, May 18, 2018 at 04:37:10PM +, Elliott, Robert (Persistent Memory)
wrote:
>
>
> ...
> > Would it help to show them in hex?
> >
> > As of ACPI 6.2 Errata A, the following values are valid for the bottom
> > two bits:
> >
> > 0x2 - Memory Controller Flush to NVDIMM Durability on
Writing to these registers may raise an interrupt request. Actually,
this prevents the milkymist board from starting.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Michael Walle
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
---
target/lm32/op_helper.c | 4
1 file changed, 4 inser
The following changes since commit 81e9cbd0ca1131012b058df6804b1f626a6b730c:
lm32: take BQL before writing IP/IM register (2018-05-21 13:37:12 +0200)
are available in the git repository at:
git://github.com/mwalle/qemu.git tags/lm32-queue/20180521
for you to fetch changes up to
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