Fam Zheng writes:
> This is a mechanical patch that does search-and-replace and adding
> necessary "#include" for pulling in the QAPI enum definition. The string
> lookup could use the QAPI helper, and is left for the next patch.
>
> Signed-off-by: Fam Zheng
> ---
> slirp/misc.c | 23
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180514065700.22202-1-...@kaod.org
Subject: [Qemu-devel] [PATCH v4] migration: discard non-migratable RAMBlocks
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(
This patch adds Intel Hexadecimal Object File format support to
the loader. The file format specification is available here:
http://www.piclist.com/techref/fileext/hex/intel.htm
The file format is mainly intended for embedded systems
and microcontrollers, such as Micro:bit Arduino, ARM, STM32, et
'test.hex' file is a bare metal ARM software stored in Hexadecimal
Object Format. When it's loaded by QEMU, it will print "Hello world!\n"
on console.
`pre_store` array in 'hexloader-test.c' file, stores the binary format
of 'test.hex' file, which is used to verify correctness.
Reviewed-by: Stefa
These series of patchs implement Intel Hexadecimal File loader and
add QTest testcase to verify the correctness of Loader.
v1:
-- Basic version.
v2:
-- Replace `do{}while(cond);` block with `for(;;)` block.
v3:
-- Add two new files information in MAINTAINERS.
v4:
-- Correct the 'test.hex' p
On Fri, May 04, 2018 at 11:08:01AM +0800, Peter Xu wrote:
> v2:
> - fix patchew code style warnings
> - interval tree: postpone malloc when inserting; simplify node remove
> a bit where proper [Jason]
> - fix up comment and commit message for iommu lock patch [Kevin]
> - protect context cache too
On Tue, May 15, 2018 10:36 PM, Igor Mammedov wrote:
> On Wed, 9 May 2018 16:34:29 +0800
> Liu Jingqi wrote:
>
> > HMAT is defined in ACPI 6.2: 5.2.27 Heterogeneous Memory Attribute Table
> (HMAT).
> > The specification references below link:
> > http://www.uefi.org/sites/default/files/resource
Great! Thanks for your suggestion!
Best,
SU Hang
"Steffen Görtz" wrote:
> On 10.05.2018 09:18, Su Hang wrote:
>
> Hi,
> this will be my first comment on devel as part of my GSoC participation
> this year.
>
> > +
> > +QTestState *s = qtest_startf(
> > +"-M versatilepb -m 128M -nogra
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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https://bugs.launchpad.net/bugs/1435101
Title:
Windows, QE
On Wed, May 16, 2018 at 09:38:31AM +0800, Fam Zheng wrote:
> On Tue, 05/15 20:00, Jie Wang wrote:
> > When we call addIOThread, the epollfd created in aio_context_setup,
> > but not close it in the process of delIOThread, so the epollfd will leak.
> >
> > Signed-off-by: Jie Wang
> > ---
> > ioth
On Tue, May 15, 2018 at 05:56:34PM +0200, Markus Armbruster wrote:
[...]
> I see.
>
> Add a contract comment (suggest to start with the one next to
> error_report()), expand the tabs, replace the reserved identifiers
> (caught by patchew; you can use foo_ instead of __foo), throw in at
> least o
On Tue, May 15, 2018 at 10:29:39AM -0500, Eric Blake wrote:
> On 05/15/2018 04:13 AM, Peter Xu wrote:
> > I stole the printk_once() macro.
> >
> > I always wanted to be able to print some error directly if there is a
> > buffer to dump, however we can't use error_report() really quite often
> > wh
On 16/5/18 12:30 am, Eric Blake wrote:
> On 05/14/2018 02:00 AM, Alexey Kardashevskiy wrote:
>> On 13/3/18 6:44 pm, Samuel Thibault wrote:
>>> Alexey Kardashevskiy, on mar. 13 mars 2018 15:49:44 +1100, wrote:
Signed-off-by: Alexey Kardashevskiy
>>>
>>> Applied to my tree, thanks!
>>
>>
>> And
On Fri, 05/04 15:42, Fam Zheng wrote:
> v6: Rename QAPI enum: TCPS -> UsernetTcpState. [Daniel]
Ping?
Fam
On Wed, May 16, 2018 at 04:41:48AM +0300, Michael S. Tsirkin wrote:
> On Thu, Apr 12, 2018 at 11:12:26PM +0800, Tiwei Bie wrote:
> > The original subject is: Extend vhost-user to support VFIO based
> > accelerators
> >
> > Update notes
> >
> >
> > Now, this patch set just focuses on
On Thu, Apr 12, 2018 at 11:12:26PM +0800, Tiwei Bie wrote:
> The original subject is: Extend vhost-user to support VFIO based accelerators
>
> Update notes
>
>
> Now, this patch set just focuses on adding the support for
> registering memory region based host notifiers. With this
> s
On Tue, 05/15 20:00, Jie Wang wrote:
> When we call addIOThread, the epollfd created in aio_context_setup,
> but not close it in the process of delIOThread, so the epollfd will leak.
>
> Signed-off-by: Jie Wang
> ---
> iothread.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/iothread
在 2018/5/15 下午11:25, Eric Blake 写道:
On 05/15/2018 06:33 AM, Yi Min Zhao wrote:
If CONFIG_SECCOMP is undefined, the option 'elevateprivileges' remains
compiled. This would make libvirt set the corresponding capability and
then trigger the guest startup fails. So this patch excludes the code
s
From: "Dr. David Alan Gilbert"
During a TLS connect we see:
migration_channel_connect calls
migration_tls_channel_connect
(calls after TLS setup)
migration_channel_connect
My previous error handling fix made migration_channel_connect
call migrate_fd_connect in all cases; unfortunately th
From: Lidong Chen
rdma_delete_block function deletes RDMALocalBlock base on index field,
but not update the index field. So when next time invoke rdma_delete_block,
it will not work correctly.
If start and cancel migration repeatedly, some RDMALocalBlock not invoke
ibv_dereg_mr to decrease kerne
From: Peter Xu
The first allow-oob=true command. It's used on destination side when
the postcopy migration is paused and ready for a recovery. After
execution, a new migration channel will be established for postcopy to
continue.
Reviewed-by: Dr. David Alan Gilbert
Signed-off-by: Peter Xu
Me
@Khaled El Mously: It's more a feature request.
** No longer affects: qemu
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https://bugs.launchpad.net/bugs/1771238
Title:
Not able to passthrough > 32 PCIe devices to a KVM Guest
St
From: Peter Xu
Introducing new return path message MIG_RP_MSG_RECV_BITMAP to send
received bitmap of ramblock back to source.
This is the reply message of MIG_CMD_RECV_BITMAP, it contains not only
the header (including the ramblock name), and it was appended with the
whole ramblock received bitm
From: Peter Xu
Introducing this new command to be sent when the source VM is ready to
resume the paused migration. What the destination does here is
basically release the fault thread to continue service page faults.
Reviewed-by: Dr. David Alan Gilbert
Signed-off-by: Peter Xu
Message-Id: <201
Hi Paolo,
The main reason for different signatures is to allow guest workloads to be
aware of the differences between the two platforms (eg VirtIO vs VMBus).
Thanks,
Alessandro
> On 15 May 2018, at 16:44, Paolo Bonzini wrote:
>
>> On 15/05/2018 13:37, petrutlucia...@gmail.com wrote:
>> From:
From: "Dr. David Alan Gilbert"
Update the migration docs:
Among other changes:
* Added a general list of advice for device authors
* Reordered the section on conditional state (subsections etc)
into the order we prefer.
* Add a note about firmware
Signed-off-by: Dr. David Alan Gilbert
From: "Dr. David Alan Gilbert"
Blank lines and comments as suggested by Eric.
Signed-off-by: Dr. David Alan Gilbert
Reviewed-by: Juan Quintela
Reviewed-by: Eric Blake
Message-Id: <20180427111502.9822-1-dgilb...@redhat.com>
Signed-off-by: Juan Quintela
---
qapi/migration.json | 9 +
From: Peter Xu
Add a new vm command MIG_CMD_RECV_BITMAP to request received bitmap for
one ramblock.
Reviewed-by: Dr. David Alan Gilbert
Signed-off-by: Peter Xu
Message-Id: <20180502104740.12123-12-pet...@redhat.com>
Signed-off-by: Juan Quintela
---
migration/savevm.c | 61 ++
From: Peter Xu
Let's introduce a lock for that QEMUFile since we are going to operate
on it in multiple threads.
Reviewed-by: Dr. David Alan Gilbert
Signed-off-by: Peter Xu
Message-Id: <20180502104740.12123-23-pet...@redhat.com>
Signed-off-by: Juan Quintela
---
migration/channel.c | 3 ++-
From: Peter Xu
Introducing new migration state "postcopy-recover". If a migration
procedure is paused and the connection is rebuilt afterward
successfully, we'll switch the source VM state from "postcopy-paused" to
the new state "postcopy-recover", then we'll do the resume logic in the
migration
From: Peter Xu
Wrapper for QMP command "migrate-pause".
Reviewed-by: Dr. David Alan Gilbert
Signed-off-by: Peter Xu
Message-Id: <20180502104740.12123-25-pet...@redhat.com>
Signed-off-by: Juan Quintela
---
hmp-commands.hx | 14 ++
hmp.c | 9 +
hmp.h |
From: Peter Xu
Sister command to migrate-recover in QMP.
Reviewed-by: Dr. David Alan Gilbert
Signed-off-by: Peter Xu
Message-Id: <20180502104740.12123-22-pet...@redhat.com>
Signed-off-by: Juan Quintela
---
hmp-commands.hx | 13 +
hmp.c | 10 ++
hmp.h |
From: Peter Xu
It pauses an ongoing migration. Currently it only supports postcopy.
Note that this command will work on either side of the migration.
Basically when we trigger this on one side, it'll interrupt the other
side as well since the other side will get notified on the disconnect
event.
From: Peter Xu
It will be used when we want to resume one paused migration.
Reviewed-by: Dr. David Alan Gilbert
Signed-off-by: Peter Xu
Message-Id: <20180502104740.12123-8-pet...@redhat.com>
Signed-off-by: Juan Quintela
---
s/2.12/2.13/
---
hmp-commands.hx | 7 ---
hmp.c
From: Peter Xu
Though we may not need it, now we init both the src/dst migration
objects in migration_object_init() so that even incoming migration
object would be thread safe (it was not).
Reviewed-by: Dr. David Alan Gilbert
Signed-off-by: Peter Xu
Message-Id: <20180502104740.12123-20-pet...@
From: Peter Xu
Finish the last step to do the final handshake for the recovery.
First source sends one MIG_CMD_RESUME to dst, telling that source is
ready to resume.
Then, dest replies with MIG_RP_MSG_RESUME_ACK to source, telling that
dest is ready to resume (after switch to postcopy-active st
From: Peter Xu
Allows the fault thread to stop handling page faults temporarily. When
network failure happened (and if we expect a recovery afterwards), we
should not allow the fault thread to continue sending things to source,
instead, it should halt for a while until the connection is rebuilt.
We need them before we start migration.
Signed-off-by: Juan Quintela
Reviewed-by: Daniel P. Berrangé
---
migration/migration.c | 6 +-
migration/ram.c | 11 +++
migration/ram.h | 1 +
3 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/migration/migration.c
From: Peter Xu
This is hook function to be called when a postcopy migration wants to
resume from a failure. For each module, it should provide its own
recovery logic before we switch to the postcopy-active state.
Reviewed-by: Dr. David Alan Gilbert
Signed-off-by: Peter Xu
Message-Id: <20180502
From: Peter Xu
On the destination side, we cannot wake up all the threads when we got
reconnected. The first thing to do is to wake up the main load thread,
so that we can continue to receive valid messages from source again and
reply when needed.
At this point, we switch the destination VM stat
From: Peter Xu
After we updated the dirty bitmaps of ramblocks, we also need to update
the critical fields in RAMState to make sure it is ready for a resume.
Reviewed-by: Dr. David Alan Gilbert
Signed-off-by: Peter Xu
Message-Id: <20180502104740.12123-18-pet...@redhat.com>
Signed-off-by: Juan
From: Peter Xu
Now when network down for postcopy, the source side will not fail the
migration. Instead we convert the status into this new paused state, and
we will try to wait for a rescue in the future.
If a recovery is detected, migration_thread() will reset its local
variables to prepare fo
From: Peter Xu
Creating new message to reply for MIG_CMD_POSTCOPY_RESUME. One uint32_t
is used as payload to let the source know whether destination is ready
to continue the migration.
Reviewed-by: Dr. David Alan Gilbert
Signed-off-by: Peter Xu
Message-Id: <20180502104740.12123-15-pet...@redha
From: Peter Xu
This patch implements the first part of core RAM resume logic for
postcopy. ram_resume_prepare() is provided for the work.
When the migration is interrupted by network failure, the dirty bitmap
on the source side will be meaningless, because even the dirty bit is
cleared, it is st
From: Peter Xu
This patch detects the "resume" flag of migration command, rebuild the
channels only if the flag is set.
Reviewed-by: Dr. David Alan Gilbert
Signed-off-by: Peter Xu
Message-Id: <20180502104740.12123-9-pet...@redhat.com>
Signed-off-by: Juan Quintela
---
migration/migration.c |
From: Peter Xu
Introducing a new state "postcopy-paused", which can be used when the
postcopy migration is paused. It is targeted for postcopy network
failure recovery.
Reviewed-by: Dr. David Alan Gilbert
Reviewed-by: Juan Quintela
Signed-off-by: Peter Xu
Message-Id: <20180502104740.12123-3-p
From: Peter Xu
Let the thread pause for network issues.
Reviewed-by: Dr. David Alan Gilbert
Signed-off-by: Peter Xu
Message-Id: <20180502104740.12123-6-pet...@redhat.com>
Signed-off-by: Juan Quintela
---
migration/migration.c | 35 +--
migration/migration.h
Signed-off-by: Juan Quintela
---
migration/ram.c | 26 --
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/migration/ram.c b/migration/ram.c
index da0b567003..4d8be30676 100644
--- a/migration/ram.c
+++ b/migration/ram.c
@@ -448,10 +448,22 @@ struct {
in
From: Peter Xu
When there is IO error on the incoming channel (e.g., network down),
instead of bailing out immediately, we allow the dst vm to switch to the
new POSTCOPY_PAUSE state. Currently it is still simple - it waits the
new semaphore, until someone poke it for another attempt.
One note is
We need to make sure that we have started all the multifd threads.
Signed-off-by: Juan Quintela
Reviewed-by: Daniel P. Berrangé
---
migration/migration.c | 4 ++--
migration/migration.h | 1 +
migration/ram.c | 3 +++
migration/socket.c| 4
4 files changed, 10 insertions(+), 2 de
From: Peter Xu
The old incoming migration is running in main thread and default
gcontext. With the new qio_channel_add_watch_full() we can now let it
run in the thread's own gcontext (if there is one).
Currently this patch does nothing alone. But when any of the incoming
migration is run in an
Once there, we don't need the struct names anywhere, just the
typedefs. And now also document all fields.
Signed-off-by: Juan Quintela
Reviewed-by: Dr. David Alan Gilbert
---
migration/ram.c | 46 +++---
1 file changed, 31 insertions(+), 15 deletions(-)
No need to write it to a file. Just need a proper firmware O:-)
Signed-off-by: Juan Quintela
Reviewed-by: Laurent Vivier
Reviewed-by: Thomas Huth
---
tests/migration-test.c | 41 +
1 file changed, 5 insertions(+), 36 deletions(-)
diff --git a/tests/mig
Signed-off-by: Juan Quintela
Reviewed-by: Daniel P. Berrangé
---
migration/socket.c | 28 +++-
migration/socket.h | 7 +++
2 files changed, 34 insertions(+), 1 deletion(-)
diff --git a/migration/socket.c b/migration/socket.c
index 122d8ccfbe..e09fd1aae5 100644
--- a
Signed-off-by: Juan Quintela
Reviewed-by: Daniel P. Berrangé
--
Be network agnostic.
Add error checking for all values.
---
migration/ram.c | 104 +---
1 file changed, 99 insertions(+), 5 deletions(-)
diff --git a/migration/ram.c b/migration/ram.c
i
Once there, make count field to always be accessed with atomic
operations. To make blocking operations, we need to know that the
thread is running, so create a bool to indicate that.
Signed-off-by: Juan Quintela
Reviewed-by: Daniel P. Berrangé
--
Once here, s/terminate_multifd_*-threads/mult
5 17:02:00 +0100)
are available in the Git repository at:
git://github.com/juanquintela/qemu.git tags/migration/20180515
for you to fetch changes up to 8b7bf2badac25c0a52aff1b181ad75fdb304dd0c:
Migration+TLS: Fix crash due to double cleanup (2018-05-15 22:1
In both sides. We still don't transmit anything through them.
Signed-off-by: Juan Quintela
Reviewed-by: Daniel P. Berrangé
---
migration/ram.c | 52 +++--
1 file changed, 42 insertions(+), 10 deletions(-)
diff --git a/migration/ram.c b/migration/ram
Signed-off-by: Juan Quintela
Reviewed-by: Dr. David Alan Gilbert
Reviewed-by: Peter Xu
---
tests/migration-test.c | 44 --
1 file changed, 42 insertions(+), 2 deletions(-)
diff --git a/tests/migration-test.c b/tests/migration-test.c
index b99661b773..2b9
Signed-off-by: Juan Quintela
Reviewed-by: Daniel P. Berrangé
---
migration/migration.c | 3 ++-
migration/ram.c | 6 ++
migration/ram.h | 2 ++
3 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/migration/migration.c b/migration/migration.c
index 35f2781b03..4a7959c11
From: Xiao Guangrong
Fix the bug introduced by da3f56cb2e767016 (migration: remove
ram_save_compressed_page()), It should be 'return' rather than
'res'
Sorry for this stupid mistake :(
Signed-off-by: Xiao Guangrong
Message-Id: <20180428081045.8878-1-xiaoguangr...@tencent.com>
Signed-off-by: Ju
On Thu, May 10, 2018 at 03:28:48PM +0200, Igor Mammedov wrote:
> On Fri, 27 Apr 2018 15:53:14 -0600
> Ross Zwisler wrote:
>
> > Add a device command line option to allow the user to control the Platform
> > Capabilities Structure in the virtualized NFIT.
> >
> > Signed-off-by: Ross Zwisler
> >
@David Coronel: It's not clear to me - is this a regression?
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https://bugs.launchpad.net/bugs/1771238
Title:
Not able to passthrough > 32 PCIe devices to a KVM Guest
Status in QEMU:
For each operand, pass a single enumeration instead of a pair of booleans.
The commit also merges multiple different ifdef-selected implementations
of pickNaN into a single function whose body is ifdef-selected.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
fpu/softfloat-speci
This is now handled properly by the generic softfloat code.
Cc: Alexander Graf
Reviewed-by: David Hildenbrand
Signed-off-by: Richard Henderson
---
target/s390x/fpu_helper.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/s390x/fpu_helper.c b/target/s390x
We will need these helpers within softfloat-specialize.h, so move
the definitions above the include. After specialization, they will
not always be used so mark them to avoid the Werror.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
From: Alex Bennée
This allows us to delete a lot of additional boilerplate
code which is no longer needed.
Reviewed-by: Peter Maydell
Signed-off-by: Alex Bennée
Signed-off-by: Richard Henderson
---
v2
- pass FloatFmt to float_to_float instead of sizes
- split AHP handling to another patc
This is now handled properly by the generic softfloat code.
Cc: Aurelien Jarno
Cc: Yongbok Kim
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/mips/msa_helper.c | 4
target/mips/op_helper.c | 2 --
2 files changed, 6 deletions(-)
diff --git a/target/mips/msa_help
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper-a64.c | 6 +++---
target/arm/helper.c | 12 ++--
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/arm/helper-a64.c b/target/arm/he
Reviewed-by: Peter Maydell
Reviewed-by: Laurent Vivier
Signed-off-by: Richard Henderson
---
target/m68k/softfloat.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/m68k/softfloat.c b/target/m68k/softfloat.c
index d093997219..b45a5e8690 100644
--- a/target/m68k/softf
From: Alex Bennée
For float16 ARM supports an alternative half-precision format which
sacrifices the ability to represent NaN/Inf in return for a higher
dynamic range. The new FloatFmt flag, arm_althp, is then used to
modify the behaviour of canonicalize and round_canonical with respect
to repre
Only MIPS requires snan_bit_is_one to be variable. While we are
specializing softfloat behaviour, allow other targets to eliminate
this runtime check.
Cc: Aurelien Jarno
Cc: Yongbok Kim
Cc: David Gibson
Cc: Alexander Graf
Cc: Guan Xuetao
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Revi
Isolate the target-specific choice to 3 functions instead of 6.
The code in floatx80_default_nan tried to be over-general. There are
only two targets that support this format: x86 and m68k. Thus there
is no point in inventing a mechanism for snan_bit_is_one.
Move routines that no longer have if
This is now handled properly by the generic softfloat code.
Reviewed-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/hppa/op_helper.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c
index a3af62daf7..
These functions are now unused.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
fpu/softfloat-specialize.h | 63 --
include/fpu/softfloat.h| 5 ---
2 files changed, 68 deletions(-)
diff -
The new function assumes that the input is an SNaN and
does not double-check.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
fpu/softfloat-specialize.h | 174 +
include/fpu/softfloat.h|
Reduce the number of ifdefs. Correct the result for OpenRISC
and TriCore (although TriCore fixed in target-specific code).
Signed-off-by: Richard Henderson
---
fpu/softfloat-specialize.h | 21 ++---
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/fpu/softfloat-spe
This is now handled properly by the generic softfloat code.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper-a64.c | 1 -
target/arm/helper.c | 12 ++--
2 files changed, 2 insertions(+), 11 deletions
We have already checked the arguments for SNaN;
we don't need to do it again.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
fpu/softfloat-specialize.h | 44 +-
1 file changed, 34 insertions(+
Shift the NaN fraction to a canonical position, much like we
do for the fraction of normal numbers. This will facilitate
manipulation of NaNs within the shared code paths.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
fpu/soft
Isolate the target-specific choice to 2 functions instead of 6.
The code in float16_default_nan was only correct for ARM, MIPS, and X86.
Though float16 support is rare among our targets.
The code in float128_default_nan was arguably wrong for Sparc. While
QEMU supports the Sparc 128-bit insns, n
This is now handled properly by the generic softfloat code.
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Reviewed-by: Michael Clark
Signed-off-by: Richard Henderson
---
target/riscv/fpu_helper.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/targe
From: Alex Bennée
Instead of passing env and leaving it up to the helper to get the
right fpstatus we pass it explicitly. There was already a get_fpstatus
helper for neon for the 32 bit code. We also add an get_ahp_flag() for
passing the state of the alternative FP16 format flag. This leaves
scop
We want to be able to specialize on the canonical representation.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
fpu/softfloat.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/fpu/soft
For each operand, pass a single enumeration instead of a pair of booleans.
The commit also merges multiple different ifdef-selected implementations
of pickNaNMulAdd into a single function whose body is ifdef-selected.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
fpu/softfloat
With a canonical representation of NaNs, we can return the
default nan directly rather than delay the expansion until
the final format is known.
Note one case where we uselessly assigned to a.sign, which was
overwritten/ignored later when expanding float_class_dnan.
Tested-by: Alex Bennée
Review
From: Petr Tesarik
The significand is passed to normalizeRoundAndPackFloat128() as high
first, low second. The current code passes the integer first, so the
result is incorrectly shifted left by 64 bits.
This bug affects the emulation of s390x instruction CXLGBR (convert
from logical 64-bit bina
From: Alex Bennée
The ARM ARM specifies FZ16 is suppressed for conversions. Rather than
pushing this logic into the softfloat code we can simply save the FZ
state and temporarily disable it for the softfloat call.
Reviewed-by: Peter Maydell
Signed-off-by: Alex Bennée
Signed-off-by: Richard Hen
With a canonical representation of NaNs, we can silence an SNaN
immediately rather than delay until the final format is known.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
fpu/softfloat-specialize.h | 23 ++
Move the ifdef inside the relevant functions instead of
duplicating the function declarations.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
fpu/softfloat-specialize.h | 100 +++--
1 file changed
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
fpu/softfloat-specialize.h | 15 +++
fpu/softfloat.c| 12 ++--
2 files changed, 17 insertions(+), 10 deletions(-)
diff --git a/fpu/softfloat-speciali
This is my SNaN patch set, Alex's float-float refactor, and a couple
of other random outstanding fpu patches. This has been reordered so
as to be bisectable, since the float-float refactor requires the snan
work to avoid breakage.
The edition of pm215/target-arm.next upon which this was built has
On Wed, May 09, 2018 at 02:15:14PM -0700, Richard Henderson wrote:
> On 05/08/2018 10:31 AM, Edgar E. Iglesias wrote:
> > +if (to) {
> > +gen_helper_mmu_write(cpu_env, tcg_const_i32(extended),
> > + tcg_const_i32(sr), cpu_R[dc->ra]);
> > +
From: Babu Moger
The property legacy-cache will be used to control the cache information.
If user passes "-cpu legacy-cache" then older information will
be displayed even if the hardware supports new information. Otherwise
use the statically loaded cache definitions if available.
Renamed the pre
From: Jingqi Liu
The CLDEMOTE instruction hints to hardware that the cache line that
contains the linear address should be moved("demoted") from
the cache(s) closest to the processor core to a level more distant
from the processor core. This may accelerate subsequent accesses
to the line by other
Instead of having a collection of macros that need to be used in
complex expressions to build CPUID data, define a CPUCacheInfo
struct that can hold information about a given cache. Helper
functions will take a CPUCacheInfo struct as input to encode
CPUID leaves for a cache.
This will help us ens
From: Boqun Feng
A new cpu model called "KnightsMill" is added to model Knights Mill
processors. Compared to "Skylake-Server" cpu model, the following
features are added:
avx512_4vnniw avx512_4fmaps avx512pf avx512er avx512_vpopcntdq
and the following features are removed:
pci
From: Babu Moger
Initialize pre-determined cache information for EPYC processors.
Signed-off-by: Babu Moger
Tested-by: Geoffrey McRae
Message-Id: <20180510204148.11687-5-babu.mo...@amd.com>
Signed-off-by: Eduardo Habkost
---
target/i386/cpu.c | 52
From: Babu Moger
Add pc-q35-2.13 and pc-i440fx-2.13 machine types
Signed-off-by: Babu Moger
Message-Id: <20180514164156.27034-2-babu.mo...@amd.com>
Reviewed-by: Eduardo Habkost
Signed-off-by: Eduardo Habkost
---
include/hw/i386/pc.h | 3 +++
hw/i386/pc_piix.c| 15 ---
hw/i38
From: Babu Moger
Add cache information in X86CPUDefinition and CPUX86State.
Signed-off-by: Babu Moger
Tested-by: Geoffrey McRae
Reviewed-by: Eduardo Habkost
Message-Id: <20180510204148.11687-3-babu.mo...@amd.com>
Signed-off-by: Eduardo Habkost
---
target/i386/cpu.h | 7 +++
target/i386/
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