On Thu, May 03, 2018 at 10:40:17PM -0700, Richard Henderson wrote:
> While the openrisc decode isn't particularly complicated,
> the result, I think, is still cleaner.
Hi Richard,
I agree this does look clean, thanks for doing this.
I reviewed all and everything seems good, do you plan to send t
On Thu, May 03, 2018 at 10:40:30PM -0700, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
Acked-by: Stafford Horne
> ---
> target/openrisc/translate.c | 15 ++-
> 1 file changed, 6 insertions(+), 9 deletions(-)
>
> diff --git a/target/openrisc/translate.c b/target/open
On Thu, May 03, 2018 at 10:40:29PM -0700, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
Acked-by: Stafford Horne
> ---
> target/openrisc/translate.c | 359
> +++
> target/openrisc/insns.decode | 21 +++
> 2 files changed, 149 insertions(
On Thu, May 03, 2018 at 10:40:27PM -0700, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
Acked-by: Stafford Horne
> ---
> target/openrisc/translate.c | 120
> +--
> target/openrisc/insns.decode | 15 ++
> 2 files changed, 73 insertion
On Thu, May 03, 2018 at 10:40:28PM -0700, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
Acked-by: Stafford Horne
> ---
> target/openrisc/translate.c | 116
> +--
> target/openrisc/insns.decode | 12 +
> 2 files changed, 70 insertions
On Thu, May 03, 2018 at 10:40:26PM -0700, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
Acked-by: Stafford Horne
> ---
> target/openrisc/translate.c | 41 +
> target/openrisc/insns.decode | 3 +++
> 2 files changed, 16 insertions(+), 28 d
On Thu, May 03, 2018 at 10:40:25PM -0700, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
Acked-by: Stafford Horne
> ---
> target/openrisc/translate.c | 62
> +++-
> target/openrisc/insns.decode | 6 +
> 2 files changed, 32 insertions(
On Thu, May 03, 2018 at 10:40:24PM -0700, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
Acked-by: Stafford Horne
> ---
> target/openrisc/translate.c | 55
> ++--
> target/openrisc/insns.decode | 5
> 2 files changed, 27 insertions(+
On Thu, May 03, 2018 at 10:40:23PM -0700, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
Acked-by: Stafford Horne
> ---
> target/openrisc/translate.c | 322
> +++
> target/openrisc/insns.decode | 76 +++---
> 2 files changed, 229 inse
On 05/04/2018 10:26 PM, Eduardo Habkost wrote:
On Mon, Apr 23, 2018 at 06:51:17PM +0200, David Hildenbrand wrote:
[...]
+/* always allocate the device memory information */
+machine->device_memory = g_malloc(sizeof(*machine->device_memory));
[...]
-/* initialize hotplug memory ad
On Thu, May 03, 2018 at 10:40:22PM -0700, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
Acked-by: Stafford Horne
> ---
> target/openrisc/translate.c | 279
> +++
> target/openrisc/insns.decode | 35 +-
> 2 files changed, 151 insertio
On Thu, May 03, 2018 at 10:40:21PM -0700, Richard Henderson wrote:
Acked-by: Stafford Horne
> Signed-off-by: Richard Henderson
> ---
> target/openrisc/translate.c | 275
> +--
> target/openrisc/insns.decode | 24
> 2 files changed, 160 insertions
On Thu, May 03, 2018 at 10:40:20PM -0700, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
Acked-by: Stafford Horne
> ---
> target/openrisc/translate.c | 149
> +--
> target/openrisc/insns.decode | 12
> 2 files changed, 83 insertions(
On Thu, May 03, 2018 at 10:40:19PM -0700, Richard Henderson wrote:
> Begin with the 0x08 major opcode, the system instructions.
>
> Signed-off-by: Richard Henderson
Acked-by: Stafford Horne
> ---
> target/openrisc/translate.c | 79
> +--
> target/open
On Thu, May 03, 2018 at 10:40:18PM -0700, Richard Henderson wrote:
> From: Richard Henderson
>
> The architecture manual is unclear about this, but the or1ksim
> does writeback before the exception. This requires splitting
> the helpers in half, with the exception raised by the second.
I dont r
On Fri, May 04, 2018 at 03:11:57PM +0200, Cédric Le Goater wrote:
> On 05/04/2018 06:51 AM, David Gibson wrote:
> > On Thu, May 03, 2018 at 06:06:14PM +0200, Cédric Le Goater wrote:
> >> On 05/03/2018 07:35 AM, David Gibson wrote:
> >>> On Thu, Apr 26, 2018 at 11:27:21AM +0200, Cédric Le Goater wro
On Fri, May 04, 2018 at 04:25:16PM +0200, Cédric Le Goater wrote:
> On 04/27/2018 04:43 AM, David Gibson wrote:
> I did some work on that topic a while ago :
>
> https://patchwork.ozlabs.org/cover/836782/
>
> But we stopped exploring the idea. May be it was not the good ap
On Fri, May 04, 2018 at 03:29:02PM +0200, Cédric Le Goater wrote:
> On 05/04/2018 07:19 AM, David Gibson wrote:
> > On Thu, May 03, 2018 at 04:37:29PM +0200, Cédric Le Goater wrote:
> >> On 05/03/2018 08:25 AM, David Gibson wrote:
> >>> On Thu, May 03, 2018 at 08:07:54AM +0200, Cédric Le Goater wro
On Fri, May 04, 2018 at 03:05:08PM +0200, Cédric Le Goater wrote:
> On 05/04/2018 05:33 AM, David Gibson wrote:
> > On Thu, May 03, 2018 at 06:50:09PM +0200, Cédric Le Goater wrote:
> >> On 05/03/2018 07:22 AM, David Gibson wrote:
> >>> On Thu, Apr 26, 2018 at 12:43:29PM +0200, Cédric Le Goater wro
On Fri, May 04, 2018 at 07:18:13AM -0500, Michael Roth wrote:
> Quoting Greg Kurz (2018-05-04 04:37:24)
> > On Thu, 3 May 2018 23:20:44 -0500
> > Michael Roth wrote:
> >
> > > In some cases (e.g. spapr) we record guest timebase after qmp_stop()
> > > via a runstate hook so we can restore it on q
On Fri, May 04, 2018 at 03:50:28PM +0200, Greg Kurz wrote:
> On Fri, 04 May 2018 07:18:13 -0500
> Michael Roth wrote:
>
> > Quoting Greg Kurz (2018-05-04 04:37:24)
> > > On Thu, 3 May 2018 23:20:44 -0500
> > > Michael Roth wrote:
> > >
> > > > In some cases (e.g. spapr) we record guest timeb
On Fri, May 04, 2018 at 10:45:50AM +0200, BALATON Zoltan wrote:
> Signed-off-by: BALATON Zoltan
Applied to ppc-for-2.13. There won't be a pull request until after
I'm back from holidays in a month, though. Sorry.
> ---
> hw/ppc/ppc440_pcix.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion
On 05/04/2018 12:59 PM, Philippe Mathieu-Daudé wrote:
> The block transfers data frames are upto 512 bytes and use a 16-bit CRC.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> include/hw/sd/sd.h | 29 +
> hw/sd/sdmmc-internal.c | 10 ++
> 2 files change
On Sat, May 5, 2018 at 11:54 AM, Alistair Francis
wrote:
> On Fri, May 4, 2018 at 4:44 PM Alistair Francis
> wrote:
>
> > On Thu, May 3, 2018 at 6:45 PM Michael Clark wrote:
>
>
>
> > > On Sat, Apr 28, 2018 at 4:17 AM, Alistair Francis <
> alistai...@gmail.com>
> > wrote:
>
> > >> On Thu, Apr 2
On Fri, May 4, 2018 at 4:44 PM Alistair Francis
wrote:
> On Thu, May 3, 2018 at 6:45 PM Michael Clark wrote:
> > On Sat, Apr 28, 2018 at 4:17 AM, Alistair Francis
> wrote:
> >> On Thu, Apr 26, 2018 at 10:34 PM Michael Clark wrote:
> >> > On Fri, Apr 27, 2018 at 5:22 PM, Michael Clark
w
On Thu, May 3, 2018 at 6:45 PM Michael Clark wrote:
> On Sat, Apr 28, 2018 at 4:17 AM, Alistair Francis
wrote:
>> On Thu, Apr 26, 2018 at 10:34 PM Michael Clark wrote:
>> > On Fri, Apr 27, 2018 at 5:22 PM, Michael Clark wrote:
>> >> On Fri, Apr 27, 2018 at 4:48 AM, Alistair Francis <
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180504074207.22634-1-f...@redhat.com
Subject: [Qemu-devel] [PATCH v6 0/4] slirp: Add query-usernet QMP command
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(
On Fri, May 4, 2018 at 9:03 AM Philippe Mathieu-Daudé
wrote:
> Fix style to keep patchew/checkpatch happy when moving this code
> in the next patch.
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/sd/sd.c | 16 ++--
> 1 file changed,
On Fri, May 4, 2018 at 9:00 AM Philippe Mathieu-Daudé
wrote:
> Since not all modelled controllers use the CRC verification (which is
> somehow expensive), let the controller have a configurable property
> to enable verification.
> So far only the Milkymist controller uses it.
> This silent the
On Sat, May 5, 2018 at 8:12 AM, Alistair Francis
wrote:
> Create a SiFive Unleashed U54 SoC and use that in the sifive_u machine.
>
> We leave the SoC, RAM, device tree and reset/fdt loading as part of the
> machine. All the other device creation has been moved to the SoC.
>
There is a tiny prob
This implements all of the v8.1-Atomics instructions except
for compare-and-swap, which is decoded elsewhere.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v3: Do not zero-extend X[s] via the third parameter to read_cpu_reg.
---
target/arm/translate-a64.c | 38 +++
On 04/05/2018 18:00, Daniel P. Berrangé wrote:
> Based on that doc and https://repology.org/metapackage/glib/versions,
> I identified that we could feasibly set min glib to 2.42. Note that
> this would be dropping RHEL-6 as a build host (RHEL-6.0 came out in
> 2010 so that's reasonable to drop IMHO
On 04/05/2018 19:01, Thomas Huth wrote:
> The -no-kvm* options are a remainder of the ancient "qemu-kvm"
> fork. They have never been officially documented in our qemu-doc,
> they have been marked as deprecated in the sources since a very
> long time, and we've marked them as deprecated in our qemu
On 04/05/2018 19:01, Thomas Huth wrote:
> The -no-kvm* options are a remainder of the ancient "qemu-kvm"
> fork. They have never been officially documented in our qemu-doc,
> they have been marked as deprecated in the sources since a very
> long time, and we've marked them as deprecated in our qemu
On 04/05/2018 17:13, Thomas Huth wrote:
> The qemu-doc already states that this option is only maintained for
> backward compatibility and "-device virtconsole" should be used
> instead. So let's take the next step and mark this option officially
> as deprecated.
>
> Reviewed-by: Markus Armbruster
Connect the Cadence GEM ethernet device. This also requires us to
expose the plic interrupt lines.
Signed-off-by: Alistair Francis
---
default-configs/riscv32-softmmu.mak | 1 +
default-configs/riscv64-softmmu.mak | 1 +
hw/riscv/sifive_u.c | 29 +
i
Signed-off-by: Alistair Francis
---
hw/riscv/sifive_e.c | 97 +++--
include/hw/riscv/sifive_e.h | 16 +-
2 files changed, 86 insertions(+), 27 deletions(-)
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index e4ecb7aa4b..0ab5e3ca45 100644
--- a
This series has two tasks:
1. To conver the SiFive U and E machines into SoCs and boards
2. To connect the Cadence GEM device to teh SiFive U board
After this series the SiFive E and U boards have their SoCs split into
seperate QEMU objects, which can be used on future boards if desired.
The RI
Create a SiFive Unleashed U54 SoC and use that in the sifive_u machine.
We leave the SoC, RAM, device tree and reset/fdt loading as part of the
machine. All the other device creation has been moved to the SoC.
Signed-off-by: Alistair Francis
---
hw/riscv/sifive_u.c | 90
Instead of creating the interrupt in lines with qemu_allocate_irq() use
qdev_init_gpio_in() as this gives us the ability to use the qdev*gpio*()
helpers later on.
Signed-off-by: Alistair Francis
---
hw/riscv/sifive_plic.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/hw
On Fri, May 04, 2018 at 08:07:53AM -0500, Eric Blake wrote:
> [adding a cross-post to the git mailing list]
>
> On 05/04/2018 02:10 AM, Cornelia Huck wrote:
> > On Thu, 3 May 2018 22:51:40 +0300
> > "Michael S. Tsirkin" wrote:
> >
> > > This way they are easier to find using standard rules.
> >
On Fri, May 04, 2018 at 09:40:06PM +0200, Olaf Hering wrote:
> Am Fri, 4 May 2018 17:00:23 +0100
> schrieb Daniel P. Berrangé :
>
> > - I suggested following libvirt's lead in writing a policy for how
> > we pick supported OS targets to inform maintainers when min versions
> > can be in
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180504183021.19318-1-richard.hender...@linaro.org
Subject: [Qemu-devel] [PATCH v2 00/10] target/arm: Implement v8.1-Atomics
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
On 05/04/2018 11:00 AM, Daniel P. Berrangé wrote:
Per supported platforms doc, the various min glib on relevant distros is:
RHEL-7: 2.50.3
Debian (Stretch): 2.50.3
Debian (Jessie): 2.42.1
OpenBSD (Ports): 2.54.3
FreeBSD (Ports): 2.50.3
OpenSUSE Leap 15: 2.54.3
Ubuntu (Xenial
CC'ing xen-devel in case Xen maintainers have a need for something that
will that conflict with this proposal wrt supported build platforms.
On Fri, May 04, 2018 at 05:00:23PM +0100, Daniel P. Berrangé wrote:
> This short series is a followup the discussions around min glib version
> when Olaf fou
Am Fri, 4 May 2018 17:00:23 +0100
schrieb Daniel P. Berrangé :
> - I suggested following libvirt's lead in writing a policy for how
> we pick supported OS targets to inform maintainers when min versions
> can be increased.
Since Xen depends on qemu, it also means that SLE11 will disapp
On Fri, May 04, 2018 at 09:30:45AM -0700, Jonathan Helman wrote:
> The Linux kernel commit b4325044 ("virtio_balloon: add array
> of stat names") defines an array of stat name strings for consumers
> of the virtio interface to use via the virtio_balloon.h header
> file, rather than requiring ea
Now that the (native or emulated) xen_be_copy_grant_refs() helper is
always available, the xen_disk code can be significantly simplified by
removing direct use of grant map and unmap operations.
Signed-off-by: Paul Durrant
---
Cc: Stefano Stabellini
Cc: Anthony Perard
Cc: Kevin Wolf
Cc: Max Re
Certain functions in xen_disk are called with a pointer to xendev
(struct XenDevice *). They then use continer_of() to acces the surrounding
blkdev (struct XenBlkDev) but then in various places use &blkdev->xendev
when use of the original xendev pointer is shorter to express and clearly
equivalent.
Now that helpers are available in xen_backend, use them throughout all
Xen PV backends.
Signed-off-by: Paul Durrant
---
Cc: Stefano Stabellini
Cc: Anthony Perard
Cc: Greg Kurz
Cc: Paolo Bonzini
Cc: Jason Wang
Cc: Gerd Hoffmann
v2:
- New in v2
---
hw/9pfs/xen-9p-backend.c | 32 +++
On Mon, Apr 23, 2018 at 06:51:17PM +0200, David Hildenbrand wrote:
[...]
> +/* always allocate the device memory information */
> +machine->device_memory = g_malloc(sizeof(*machine->device_memory));
[...]
> -/* initialize hotplug memory address space */
> +/* always allocate the dev
Now that helpers are present in xen_backend, this patch removes open-coded
calls to libxengnttab from the xen_disk code.
This patch also fixes one whitspace error in the assignment of the
XenDevOps initialise method.
Signed-off-by: Paul Durrant
---
Cc: Stefano Stabellini
Cc: Anthony Perard
Cc:
Not all Xen environments support the xengnttab_grant_copy() operation.
E.g. where the OS is FreeBSD or Xen is older than 4.8.0.
This patch introduces an emulation of that operation using
xengnttab_map_domain_grant_refs() and memcpy() for those environments.
Signed-off-by: Paul Durrant
---
Cc: St
There is no longer any use of this flag outside of the xen_backend code.
Signed-off-by: Paul Durrant
---
Cc: Stefano Stabellini
Cc: Anthony Perard
v2:
- New in v2
---
hw/xen/xen_backend.c | 2 +-
include/hw/xen/xen_backend.h | 1 -
2 files changed, 1 insertion(+), 2 deletions(-)
dif
Since xen_disk now always copies data to and from a guest there is no need
to maintain a vector entry corresponding to every page of a request.
This means there is less per-request state to maintain so the ioreq
structure can shrink significantly.
Signed-off-by: Paul Durrant
---
Cc: Stefano Stabe
The grant copy operation was added to libxengnttab in Xen 4.8.0 (released
nearly 18 months ago) but the xen_disk PV backend QEMU is still carrying
a significant amount of code purely to remain compatible with older
versions of Xen.
As can be inferred from the diff stats below, removing this suppor
This patch adds grant table helper functions to the xen_backend code to
localize error reporting and use of xen_domid.
The patch also defers the call to xengnttab_open() until just before the
initialise method in XenDevOps is invoked. This method is responsible for
mapping the shared ring. No prio
This implements all of the v8.1-Atomics instructions except
for compare-and-swap, which is decoded elsewhere.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 38 --
1 file changed, 36 insertions(+), 2 deletions(-)
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper-a64.h| 2 +
target/arm/helper-a64.c| 43
target/arm/translate-a64.c | 119 +++--
3 files changed, 161 insertions(+), 3 deletions(-)
diff --git a/
Signed-off-by: Jonathan Marler
---
device_tree.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/device_tree.c b/device_tree.c
index 52c3358..2b75905 100644
--- a/device_tree.c
+++ b/device_tree.c
@@ -379,8 +379,12 @@ uint32_t qemu_fdt_get_phandle(void *fdt, const char
The insns in the ARMv8.1-Atomics are added to the existing
load/store exclusive and load/store reg opcode spaces.
Rearrange the top-level decoders for these to accomodate.
The Atomics insns themselves still generate Unallocated.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h |
Given that this atomic operation will be used by both risc-v
and aarch64, let's not duplicate code across the two targets.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
accel/tcg/atomic_template.h | 71 +
accel/tcg/tcg-runtime.h
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu64.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 991d764674..c50dcd4077 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -248,6 +248,7 @@ static void aar
The generic expanders replace nearly identical code in the translator.
Acked-by: Max Filippov
Signed-off-by: Richard Henderson
---
target/xtensa/translate.c | 50 +++
1 file changed, 33 insertions(+), 17 deletions(-)
diff --git a/target/xtensa/transl
Suggested-by: Peter Maydell
Signed-off-by: Richard Henderson
---
accel/tcg/atomic_template.h | 49 +++--
1 file changed, 7 insertions(+), 42 deletions(-)
diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h
index 2489dd3ec1..3f41ef2782 1
Reviewed-by: Michael Clark
Signed-off-by: Richard Henderson
---
target/riscv/translate.c | 72 ++--
1 file changed, 20 insertions(+), 52 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 808eab7f50..9cab717088 100644
The generic expanders replace nearly identical code in the translator.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 46 ++
1 file changed, 14 insertions(+), 32 deletions(-)
diff --git a/target/arm/trans
This implements the Atomics extension, which is mandatory for v8.1.
While testing the v8.2-SVE extension, I've run into issues with the
GCC testsuite expecting this to exist.
Missing is the wiring up of the system registers to indicate that
the extension exists, but we have no system CPU model tha
These operations are re-invented by several targets so far.
Several supported hosts have insns for these, so place the
expanders out-of-line for a future introduction of tcg opcodes.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/tcg-op.h | 16
tcg/tcg-op.c
On 05/04/2018 09:49 AM, Collin Walling wrote:
When a user incorrectly provides an hmp command, an error response will be
printed that prompts the user to try "help ". However, when
the command contains multiple parts e.g. "info skeys", only the last
whitespace delimited string will be reported (i
On 05/04/2018 01:02 PM, Collin Walling wrote:
So rather than trying to reconstruct a string, you could reuse what you already
have. This is a shorter patch that I think accomplishes the same goal:
diff --git i/monitor.c w/monitor.c
index 39f8ee17ba7..38736b3a20d 100644
--- i/monitor.c
+++ w/m
On 05/04/2018 11:19 AM, Eric Blake wrote:
> On 05/04/2018 09:49 AM, Collin Walling wrote:
>> When a user incorrectly provides an hmp command, an error response will be
>> printed that prompts the user to try "help ". However, when
>> the command contains multiple parts e.g. "info skeys", only the l
; Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2018-05-04' into
> staging (2018-05-04 14:42:46 +0100)
>
> are available in the Git repository at:
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git
> tags/pull-target-arm-20180504
>
> for y
at:
git://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20180504-1
for you to fetch changes up to e24e3454829579eb815ec95d7b3679b0f65845b4:
hw/arm/virt: Introduce the iommu option (2018-05-04 18:52:58 +0100)
-
On Fri, May 04, 2018 at 04:50:12PM +0100, Stefan Hajnoczi wrote:
> The 185 qemu-iotests test case was in a bad state for the QEMU 2.12 release.
> We fudged the expected test output to make it pass, except for
> non-deterministic behavior.
>
> These patches get us back to pre-QEMU 2.12. Notably th
04.05.2018 18:50, Stefan Hajnoczi wrote:
Commit 8565c3ab537e78f3e69977ec2c609dc9417a806e ("qemu-iotests: fix
185") identified a race condition in a sub-test.
Similar issues also affect the other sub-tests. If disk I/O completes
quickly, it races with the QMP 'quit' command. This causes spuriou
From: Eric Auger
In case the MSI is translated by an IOMMU we need to fixup the
MSI route with the translated address.
Signed-off-by: Eric Auger
Signed-off-by: Bharat Bhushan
Message-id: 1524665762-31355-12-git-send-email-eric.au...@redhat.com
Reviewed-by: Peter Maydell
Signed-off-by: Peter M
From: Eric Auger
Let's introduce a helper function aiming at recording an
event in the event queue.
Signed-off-by: Eric Auger
Reviewed-by: Peter Maydell
Message-id: 1524665762-31355-9-git-send-email-eric.au...@redhat.com
Signed-off-by: Peter Maydell
---
hw/arm/smmuv3-internal.h | 148 +++
From: Eric Auger
At the moment, the SMMUv3 does not support notification on
TLB invalidation. So let's log an error as soon as such notifier
gets enabled.
Signed-off-by: Eric Auger
Reviewed-by: Peter Maydell
Message-id: 1524665762-31355-11-git-send-email-eric.au...@redhat.com
Signed-off-by: Pe
On 2018-05-02 09:59, Daniel P. Berrangé wrote:
> On Wed, May 02, 2018 at 12:43:10AM -0700, Liviu Ionescu wrote:
>> On 2 May 2018 at 10:38:09, Cornelia Huck (coh...@redhat.com) wrote:
>>
>>> a) Bump major version once a year, so we'll have 3.0, 3.1,
>>> 3.3,
>> 4.0, 4.1, 4.2, 5.0, ...etc We
From: Eric Auger
ARM virt machine now exposes a new "iommu" option.
The SMMUv3 IOMMU is instantiated using -machine virt,iommu=smmuv3.
Signed-off-by: Eric Auger
Signed-off-by: Prem Mallappa
Reviewed-by: Peter Maydell
Message-id: 1524665762-31355-15-git-send-email-eric.au...@redhat.com
Signed-
From: Eric Auger
We introduce helpers to read/write into the command and event
circular queues.
smmuv3_write_eventq and smmuv3_cmq_consume will become static
in subsequent patches.
Invalidation commands are not yet dealt with. We do not cache
data that need to be invalidated. This will change w
On 05/04/2018 06:20 AM, Kevin Wolf wrote:
> I'm not sure what the exact systemd model is, but as we came to the
> conclusion that there is no semantic difference between major and minor
> version number for QEMU, I'd just merge them.
>
> This would result in 3.0 for the next release, 3.1 etc. woul
From: Eric Auger
This patch implements the IOMMU Memory Region translate()
callback. Most of the code relates to the translation
configuration decoding and check (STE, CD).
Signed-off-by: Eric Auger
Signed-off-by: Prem Mallappa
Message-id: 1524665762-31355-10-git-send-email-eric.au...@redhat.c
From: Eric Auger
This patch implements the page table walk for VMSAv8-64.
Signed-off-by: Eric Auger
Signed-off-by: Prem Mallappa
Message-id: 1524665762-31355-4-git-send-email-eric.au...@redhat.com
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
hw/arm/smmu-internal.h | 99
From: Prem Mallappa
This patch builds the smmuv3 node in the ACPI IORT table.
The RID space of the root complex, which spans 0x0-0x1
maps to streamid space 0x0-0x1 in smmuv3, which in turn
maps to deviceid space 0x0-0x1 in the ITS group.
The guest must feature the IOMMU probe deferr
From: Eric Auger
Now we have relevant helpers for queue and irq
management, let's implement MMIO write operations.
Signed-off-by: Eric Auger
Signed-off-by: Prem Mallappa
Reviewed-by: Peter Maydell
Message-id: 1524665762-31355-8-git-send-email-eric.au...@redhat.com
Signed-off-by: Peter Maydell
From: Eric Auger
We set up the infrastructure to enumerate all the PCI devices
attached to the SMMU and create an associated IOMMU memory
region and address space.
Those info are stored in SMMUDevice objects. The devices are
grouped according to the PCIBus they belong to. A hash table
indexed by
From: Eric Auger
We introduce some helpers to handle wired IRQs and especially
GERROR interrupt. SMMU writes GERROR register on GERROR event
and SW acks GERROR interrupts by setting GERRORn.
The Wired interrupts are edge sensitive hence the pulse usage.
Signed-off-by: Eric Auger
Signed-off-by:
From: Richard Henderson
Path analysis shows that size == 3 && !is_q has been eliminated.
Fixes: Coverity CID1385853
Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
Message-id: 20180501180455.11214-3-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/translate-
From: Thomas Huth
When running omap1/2 or pxa2xx based ARM machines with -nodefaults,
they bail out immediately complaining about a "missing SecureDigital
device". That's not how the "default" devices in vl.c are meant to
work - it should be possible for a board to also start up without
default d
From: Prem Mallappa
Add code to instantiate an smmuv3 in virt machine. A new iommu
integer member is introduced in VirtMachineState to store the type
of the iommu in use.
Signed-off-by: Prem Mallappa
Signed-off-by: Eric Auger
Reviewed-by: Peter Maydell
Message-id: 1524665762-31355-13-git-send
For v8M the instructions VLLDM and VLSTM support lazy saving
and restoring of the secure floating-point registers. Even
if the floating point extension is not implemented, these
instructions must act as NOPs in Secure state, so they can
be used as part of the secure-to-nonsecure call sequence.
Fix
From: Prem Mallappa
This patch implements a skeleton for the smmuv3 device.
Datatypes and register definitions are introduced. The MMIO
region, the interrupts and the queue are initialized.
Only the MMIO read operation is implemented here.
Signed-off-by: Prem Mallappa
Signed-off-by: Eric Auger
From: Richard Henderson
The (size > 3 && !is_q) condition is identical to the preceeding test
of bit 3 in immh; eliminate it. For the benefit of Coverity, assert
that size is within the bounds we expect.
Fixes: Coverity CID1385846
Fixes: Coverity CID1385849
Fixes: Coverity CID1385852
Fixes: Cov
From: Jan Kiszka
This allows to pin the host controller in the Linux PCI domain space.
Linux requires that property to be available consistently or not at all,
in which case the domain number becomes unstable on additions/removals.
Adding it here won't make a difference in practice for most setup
On 08.11.2017 03:28, Philippe Mathieu-Daudé wrote:
> Hi,
>
> This series intends to provide a simple and common way to deprecate
> machines between releases. It may be extended to deprecate devices.
*ping*
Philippe, I just discovered your findings wrt to the Gumstix machines on
https://wiki.qemu
From: Igor Mammedov
Even though nothing is currently broken (since all boards
use first_cpu as boot cpu), make sure that boot_info is set
on all CPUs.
If some board would like support heterogenuos setup (i.e.
init boot_info on subset of CPUs) in future, it should add
a reasonable API to do it, in
Convert the smc91c111 device away from using the old_mmio field of
MemoryRegionOps. This device is used by several Arm board models.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20180427173611.10281-3-peter.mayd...@linaro.org
---
hw/net/smc91c111.c | 54 ++
From: Eric Auger
The patch introduces the smmu base device and class for the ARM
smmu. Devices for specific versions will be derived from this
base device.
We also introduce some important datatypes.
Signed-off-by: Eric Auger
Signed-off-by: Prem Mallappa
Reviewed-by: Peter Maydell
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