Laszlo Ersek writes:
[...]
> In brief, I think extending configure / the build system would only help
> with the less painful part of this (the scalar mapping), and so it's not
> worth doing.
We're going to leave deprecated query-cpus alone (see Eric's review of
the previous patch). Does that c
Laszlo Ersek writes:
> On 04/25/18 21:12, Eric Blake wrote:
>> On 04/25/2018 08:20 AM, Laszlo Ersek wrote:
>>
>>> ...
>>>
>>> and people would ask themselves ever after, "are there some common
>>> fields in there that we could extract ... hmmm, @props and @arch, okay,
>>> maybe, maybe not, grey
Fix has been included here:
https://git.qemu.org/?p=qemu.git;a=commitdiff;h=8dfa3061ce56d871dc9df
** Changed in: qemu
Status: New => Fix Released
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Fix has been included here:
https://git.qemu.org/?p=qemu.git;a=commitdiff;h=10fa993aae539fa8d0da1d
** Changed in: qemu
Status: New => Fix Released
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This should be fixed now in QEMU 2.12:
https://git.qemu.org/?p=qemu.git;a=commitdiff;h=7e563bfb8a5104ff0e
** Changed in: qemu
Status: New => Fix Released
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Fix has been included here:
https://git.qemu.org/?p=qemu.git;a=commitdiff;h=7a5235c9e679c58be4
** Changed in: qemu
Status: New => Fix Released
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A fix for this problem has finally been contributed here:
https://git.qemu.org/?p=qemu.git;a=commitdiff;h=7587855cd23755a7a6bd
** Changed in: qemu
Status: Confirmed => Fix Released
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Patch has been included here:
https://git.qemu.org/?p=qemu.git;a=commitdiff;h=7174970a94df10ee84143
** Changed in: qemu
Status: New => Fix Released
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Fixed here:
https://git.qemu.org/?p=qemu.git;a=commitdiff;h=4968a2c6edb7b46b127c
** Changed in: qemu
Status: New => Fix Released
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Title:
On 04/26/2018 05:43 AM, Thomas Huth wrote:
> On 25.04.2018 18:03, Christian Borntraeger wrote:
>>
>>
>> On 04/25/2018 05:36 PM, Thomas Huth wrote:
>>> On 25.04.2018 14:44, Christian Borntraeger wrote:
On 04/25/2018 02:41 PM, Christian Borntraeger wrote:
> You load from address
Fixed here:
https://git.qemu.org/?p=qemu.git;a=commitdiff;h=cb83d2efe1f591cdc7
** Changed in: qemu
Status: Fix Committed => Fix Released
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On Wed, Apr 25, 2018 at 12:26:58PM -0400, Emilio G. Cota wrote:
> On Wed, Apr 25, 2018 at 12:51:22 +0800, Peter Xu wrote:
> > Add a per-iommu big lock to protect IOMMU status. Currently the only
> > thing to be protected is the IOTLB cache, since that can be accessed
> > even without BQL, e.g., in
On Thu, Apr 19, 2018 at 07:40:09PM +0200, Cédric Le Goater wrote:
> On 04/16/2018 06:26 AM, David Gibson wrote:
> > On Thu, Apr 12, 2018 at 10:18:11AM +0200, Cédric Le Goater wrote:
> >> On 04/12/2018 07:07 AM, David Gibson wrote:
> >>> On Wed, Dec 20, 2017 at 08:38:41AM +0100, Cédric Le Goater wro
** Changed in: qemu
Status: Fix Committed => Fix Released
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Title:
migration state save/load of sdcard device is broken
Status in QEMU:
** Changed in: qemu
Status: Fix Committed => Fix Released
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Title:
cmsdk-apb-uart doesn't appear to clear interrupt flags
Status in QEMU:
** Changed in: qemu
Status: Fix Committed => Fix Released
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Title:
Set MIPS MSA in ELF Auxiliary Vectors
Status in QEMU:
Fix Released
** Changed in: qemu
Status: Fix Committed => Fix Released
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Title:
ARMv7 LPAE: IFSR doesn't have the LPAE bit in case of BKPT
Status in Q
** Changed in: qemu
Status: Fix Committed => Fix Released
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Title:
Possibly wrong GICv3 behavior when secure enabled
Status in QEMU:
Fi
** Changed in: qemu
Status: Fix Committed => Fix Released
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Title:
ARM M: Systick first wrap delayed (qemu-timers/icount prb?)
Status in
** Changed in: qemu
Status: Fix Committed => Fix Released
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Title:
qemu-io-test 58 segfaults when configured with gcov
Status in QEMU:
On Tue, Apr 24, 2018 at 10:19:58AM +0200, Cédric Le Goater wrote:
> On 04/24/2018 08:58 AM, David Gibson wrote:
> > On Thu, Apr 19, 2018 at 02:43:01PM +0200, Cédric Le Goater wrote:
> >> Bare-metal systems (PowerNV) have multiples interrupt sources. The
> >> XIVE interrupt controller has an interna
On Tue, Apr 24, 2018 at 11:46:04AM +0200, Cédric Le Goater wrote:
> On 04/24/2018 08:51 AM, David Gibson wrote:
> > On Thu, Apr 19, 2018 at 02:43:00PM +0200, Cédric Le Goater wrote:
> >> sPAPRXive is a model for the XIVE interrupt controller device of the
> >> sPAPR machine. It holds the routing XI
** Changed in: qemu
Status: Fix Committed => Fix Released
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Title:
fpu/softfloat: round_to_int_and_pack refactor broke TriCore ftoi insns
** Changed in: qemu
Status: Fix Committed => Fix Released
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Title:
qemu-aarch64-static docker arm64v8/openjdk coredump
Status in QEMU:
** Changed in: qemu
Status: Fix Committed => Fix Released
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Title:
UART in sabrelite machine simulation doesn't work with VxWorks 7
Statu
** Changed in: qemu
Status: Fix Committed => Fix Released
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Title:
Ethernet interrupt vectors for sabrelite machine are defined backwards
On Fri, Apr 20, 2018 at 06:57:21PM +0100, Dr. David Alan Gilbert (git) wrote:
[...]
> Saving the state of one device
> ==
>
> -The state of a device is saved using intermediate buffers. There are
> -some helper functions to assist this saving.
> -
> -There is a ne
On 25.04.2018 21:57, Warner Losh wrote:
> Greetings,
>
> I’ve foolishly volunteered to rebase all the changes that the bad-user mode
> folks have done to a recent master rev to get these changes upstreamed.
Great that finally someone dares to do this step! But I hope the "bad"
was just a typo ;-
On Tue, Apr 24, 2018 at 11:33:11AM +0200, Cédric Le Goater wrote:
> On 04/24/2018 08:46 AM, David Gibson wrote:
> > On Mon, Apr 23, 2018 at 09:58:43AM +0200, Cédric Le Goater wrote:
> >> On 04/23/2018 08:46 AM, David Gibson wrote:
> >>> On Thu, Apr 19, 2018 at 02:42:59PM +0200, Cédric Le Goater wro
On Tue, Apr 24, 2018 at 10:11:27AM +0200, Cédric Le Goater wrote:
> On 04/24/2018 08:41 AM, David Gibson wrote:
> > On Mon, Apr 23, 2018 at 09:31:24AM +0200, Cédric Le Goater wrote:
> >> On 04/23/2018 08:44 AM, David Gibson wrote:
> >>> On Thu, Apr 19, 2018 at 02:42:58PM +0200, Cédric Le Goater wro
On 25.04.2018 18:03, Christian Borntraeger wrote:
>
>
> On 04/25/2018 05:36 PM, Thomas Huth wrote:
>> On 25.04.2018 14:44, Christian Borntraeger wrote:
>>>
>>>
>>> On 04/25/2018 02:41 PM, Christian Borntraeger wrote:
You load from address 0.
On 04/25/2018 02:34 PM, Thomas Huth wro
On Wed, Apr 25, 2018 at 07:58:31AM +0100, Mark Cave-Ayland wrote:
> On 25/04/18 07:34, David Gibson wrote:
>
> > On Wed, Apr 25, 2018 at 07:06:03AM +0100, Mark Cave-Ayland wrote:
> > > On 06/04/18 06:33, Mark Cave-Ayland wrote:
> > >
> > > > On 25/03/18 22:11, Mark Cave-Ayland wrote:
> > > >
> >
If you have a capable file system (tmpfs is good, ext4 not so much;
run ./check with TEST_DIR pointing to a good location so as not
to skip the test), it's actually possible to create a qcow2 file
that expands to a sparse 512T image with just over 38M of content.
The test is not the world's fastest
Even though v5 was posted earlier today, it was worth a respin:
- 2/6: add R-b [Berto]
- 4/6, 6/6: improve commit messages [Max]
- 5/6: new patch, with an iotests proving that 4/6 is a bug fix [Max]
The new test is rather slow (nearly 90 seconds for me using
tmpfs) unless it skips entirely (such a
When reading a compressed image, we were allocating s->cluster_data
to 32*cluster_size + 512 (possibly over 64 megabytes, for an image
with 2M clusters). Let's check out the history:
Back when qcow2 was first written, we used s->cluster_data for
everything, including copy_sectors() and encryption
Our code was already checking that we did not attempt to
allocate more clusters than what would fit in an INT64 (the
physical maximimum if we can access a full off_t's worth of
data). But this does not catch smaller limits enforced by
various spots in the qcow2 image description: L1 and normal
clu
Match our code to the spec change in the previous patch - there's
no reason for the refcount table to allow larger offsets than the
L1/L2 tables. In practice, no image has more than 64PB of
allocated clusters anyways, as anything beyond that can't be
expressed via L2 mappings to host offsets.
Sugg
Although off_t permits up to 63 bits (8EB) of file offsets, in
practice, we're going to hit other limits first. Document some
of those limits in the qcow2 spec, and how choice of cluster size
can influence some of the limits.
While at it, notice that since we cannot map any virtual cluster
to any
We had only a few sector-based stragglers left; convert them to use
our preferred byte-based accesses.
Signed-off-by: Eric Blake
Reviewed-by: Alberto Garcia
---
v5: commit message tweak
v2: indentation fix
---
block/qcow2-cluster.c | 5 ++---
block/qcow2-refcount.c | 6 +++---
2 files changed
On 04/25/2018 10:08 AM, Max Reitz wrote:
>
>> Also, that does raise the question of whether you have more work to
>> support write-zero requests with WRITE_UNCHANGED (which indeed sounds
>> like something plausible to support).
>
> I'm afraid I don't quite understand the question.
> BDRV_REQ_WRI
One last quick note.
We are tracking RISC-V QEMU issues in the riscv.org repo:
- https://github.com/riscv/riscv-qemu/issues
We have tagged issues that are resolved in the 'qemu-2.13-for-upstream'
branch (this branch can be rebased if we re-spin)
- https://github.com/riscv/riscv-qemu/tree/qemu-2
Hi All,
As a first-time QEMU contributor, it was quite a challenge to get an entire
port accepted upstream into QEMU. As folk who have followed the progress of
the port will know; at moments my nerves got the better of me as we
approached soft-freeze. In any case, I'd like to thank everyone who he
On Wed, Apr 25, 2018 at 11:34:24AM +0200, Cédric Le Goater wrote:
> Secondary CPUs do not start at SPAPR_ENTRY_POINT but at an address
> given by the guest OS.
>
> Fixes commit c79128c14c20 ("spapr: Make a helper to set up cpu entry
> point state")
>
> Signed-off-by: Cédric Le Goater
Oops. Sin
On Wed, Apr 25, 2018 at 06:09:26PM +0200, Andrea Bolognani wrote:
> On Fri, 2018-04-20 at 20:21 +1000, David Gibson wrote:
> > On Fri, Apr 20, 2018 at 11:31:10AM +0200, Andrea Bolognani wrote:
> > > Is the 16 MiB page size available for both POWER8 and POWER9?
> >
> > No. That's a big part of wha
On Wed, 25 Apr 2018 16:45:13 PDT (-0700), Michael Clark wrote:
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
target/riscv/translate.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/riscv/translate.c b/target/r
This adds the necessary minimum to support S-mode
virtualization for priv ISA >= v1.10
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Cc: Matthew Suozzo
Signed-off-by: Michael Clark
Co-authored-by: Matthew Suozzo
Co-authored-by: Michael Clark
---
targ
Previous CSR code uses csr_read_helper and csr_write_helper
to update CSR registers however this interface prevents
atomic read/modify/write CSR operations; in addition
there is no trap-free method to access to CSRs due
to the monolithic CSR functions call longjmp.
The current iCSR interface is no
Use the new CSR read/modify/write interface to implement
atomic updates to mip/sip.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
target/riscv/csr.c | 56 +++---
1 file chan
This patch makes op_helper.c contain only instruction
operation helpers used by translate.c and moves any
unrelated cpu helpers into cpu_helper.c. No logic is
changed by this patch.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
The PLIC previously used a mutex to protect against concurrent
access to the claimed and pending bitfields. Instead of using
a mutex, we update the bitfields using atomic_cmpxchg.
Rename sifive_plic_num_irqs_pending to sifive_plic_irqs_pending
and add an early out if any interrupts are pending as
The mstatus.MXR alias in sstatus should only be writable
by S-mode if the privileged ISA version >= v1.10. Also MXR
was masked in sstatus CSR read but not sstatus CSR writes.
Now we correctly mask sstatus.mxr in both read and write.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
* Add riscv prefix to raise_exception function
* Add riscv prefix to CSR read/write functions
* Add riscv prefix to signal handler function
* Add riscv prefix to get fflags function
* Remove redundant declaration of riscv_cpu_init
and rename cpu_riscv_init to riscv_cpu_init
* rename riscv_set_mod
Vectored traps for asynchrounous interrupts are optional.
The mtvec/stvec mode field is WARL and hence does not trap
if an illegal value is written. Illegal values are ignored.
Later we can add RISCV_FEATURE_VECTORED_TRAPS however
until then the correct behavior for WARL (Write Any, Read
Legal) fi
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 9871e6f..f3f131b 100644
--- a/targ
This allows hardware and/or derived cpu instances
to override or implement new CSR operations.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
target/riscv/cpu.h | 18 ++
target/riscv/csr.c | 35
Add carriage return that was erroneously removed
when converting to qemu_log. Change hard coded
core number to the actual hartid.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
target/riscv/cpu_helper.c | 18 ++
CSR predicate functions are added to the CSR table.
mstatus.FS and counter enable checks are moved
to predicate functions and two new predicates are
added to check misa.S for s* CSRs and a new PMP
CPU feature for pmp* CSRs.
Processors that don't implement S-mode will trap
on access to s* CSRs and
The sifive_u machine already marks its ROM readonly. This fixes
the remaining boards. This commit also makes all boards use
mask_rom as the variable name for the ROM. This change also
makes space for the maximum device tree size size and adds
an explicit bounds check and error message.
Cc: Sagar K
From: Richard Henderson
Modifed from Richard Henderson's patch [1] to integrate
with the new control and status register implementation.
[1] https://lists.nongnu.org/archive/html/qemu-devel/2018-03/msg07034.html
Note: the f* CSRs already mark mstatus.FS dirty using
env->mstatus |= mstatus.FS so
Change the API of riscv_set_local_interrupt to take a
write mask and value to allow setting and clearing of
multiple local interrupts atomically in a single call.
Rename the new function to riscv_cpu_update_mip.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
* Add user-mode CSR defininitions.
* Reorder CSR definitions to match the specification.
* Change H mode interrupt comment to 'reserved'.
* Remove unused X_COP interrupt.
* Add user-mode and core-level interrupts.
* Remove erroneous until comemnts on machine mode interrupts.
* Move together paging
From: Richard Henderson
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Cc: Richard Henderson
Signed-off-by: Michael Clark
---
target/riscv/cpu.h | 6 +++---
target/riscv/translate.c | 10 +-
2 files changed, 8 insertions(+), 8 deletions(-
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
target/riscv/translate.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 808eab7..c3a029a 100644
--- a/target/riscv
Previously the mycycle/minstret CSRs and rdcycle/rdinstret
psuedo instructions would return the time as a proxy for an
increasing instruction counter in the absence of having a
precise instruction count. If QEMU is invoked with -icount,
the mcycle/minstret CSRs and rdcycle/rdinstret psuedo
instruct
mtval/stval must be set on all exceptions but zero is
a legal value if there is no exception specific info.
Placing the instruction bytes for illegal instruction
exceptions in mtval/stval is an optional feature and
is currently not supported by QEMU RISC-V.
Cc: Sagar Karandikar
Cc: Bastian Koppel
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
---
include/hw/riscv/spike.h | 4 ++--
include/hw/riscv/virt.h | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/hw/riscv/
Privileged ISA v1.9.1 defines mscounteren and mucounteren:
* mscounteren contains a mask of counters available to S-mode
* mucounteren contains a mask of counters available to U-mode
Privileged ISA v1.10 defines mcounteren and scounteren:
* mcounteren contains a mask of counters available to S-m
This commit is intended to improve readability.
There is no change to the logic.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
target/riscv/helper.c | 34 --
1 file changed, 12 insertions(+
satp is WARL so it should not trap on illegal writes, rather
it can be hardwired to zero and silently ignore illegal writes.
It seems the RISC-V WARL behaviour is preferred to having to
trap overhead versus simply reading back the value and checking
if the write took (saves hundreds of cycles and
Removes a whole lot of unnecessary boilerplate code. Machines
don't need to be objects. The expansion of the SOC object model
for the RISC-V machines will happen in the future as SiFive
plans to add their FE310 and FU540 SOCs to QEMU. However, it
seems that this present boilerplate is complete unne
Section 22.8 Subset Naming Convention of the RISC-V ISA Specification
defines the canonical order for extensions in the ISA string. It is
silent on the position of the E extension however E is a substitute
for I so it must come early in the extension list order. A comment
is added to state E and I
These fields are marked WARL (Write Any Values, Reads
Legal Values) in the RISC-V Privileged Architecture
Specification so instead of raising exceptions,
illegal writes are silently dropped.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Mich
This was added to help debug issues using -d in_asm. It is
useful to see the instruction bytes, as one can detect if
one is trying to execute ASCII or device-tree magic.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe
When load_elf is called with NULL as an argument to the
address translate callback, it does an identity translation.
This commit removes the redundant identity_translate callback.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by
This makes 'qemu-system-riscv64 -machine help' output more tidy
and consistent.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
---
hw/riscv/virt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Pointless indirection. Other ports use EM_ constants directly.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
---
hw/riscv/sifive_e.c | 2 +-
hw/riscv/sifive_u.c | 2 +-
hw/riscv/spike.c| 2 +-
hw
- Inline PTE_TABLE check for better readability
- Change access checks from ternary operator to if
- Improve readibility of User page U mode and SUM test
- Disallow non U mode from fetching from User pages
- Add reserved PTE flag check: W or W|X
- Add misaligned PPN check
- Set READ protection for
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
---
include/hw/riscv/virt.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 3a
Another case of replacing hard coded constants, this time
referring to the definition in the virt machine's memmap.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
---
hw/riscv/virt.c | 4 ++--
The RISC-V device-tree code has a number of hard-coded
constants and this change moves them into header enums.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
---
hw/riscv/sifive_clint.c | 9 ++
This is a series of bug fixes, specification conformance
fixes and CPU feature modularily updates to allow more
precise modelling of the SiFive U Series CPUs (multi-core
application processors with MMU, Supervisor and User modes)
and SiFive E Series CPUs (embedded microcontroller cores
without MMU
On 04/25/18 21:08, Eric Blake wrote:
> On 04/25/2018 02:05 PM, Laszlo Ersek wrote:
>
> + 'x86_64', 'xtensa', 'xtensaeb' ] }
x86_64 doesn't match our typical conventions of preferring '-' over '_';
also, wikipedia mentions both spellings but under the page name
'
On 04/25/18 21:12, Eric Blake wrote:
> On 04/25/2018 08:20 AM, Laszlo Ersek wrote:
>
>> ...
>>
>> and people would ask themselves ever after, "are there some common
>> fields in there that we could extract ... hmmm, @props and @arch, okay,
>> maybe, maybe not, grey area". Let's do it now and save
On 04/24/2018 05:23 AM, Alex Bennée wrote:
> # Update TESTS
> -TESTS+=$(I386_TESTS)
> +TESTS+=$(I386_ONLY_TESTS)
Doesn't this depend on a variable you introduce in the next patch?
r~
On 04/24/2018 05:24 AM, Alex Bennée wrote:
> +run-%: %
> + $(call quiet-command, $(QEMU) $< > $<.out, "TEST", "$< on
> $(TARGET_NAME)")
I've just had an x86_64 guest test run for 70 minutes. We need to limit the
amount of time spent here in some way, with excessive time reported as test
fail
On 04/25/2018 03:27 PM, Philippe Mathieu-Daudé wrote:
Hi Corey,
On 04/25/2018 12:27 PM, miny...@acm.org wrote:
From: Corey Minyard
The vmstate for isa_ipmi_bt was referencing into the bt structure,
instead create a bt structure separate and use that.
The version 1 of the BT transfer was fair
I didn't really want MTP. Someone suggested it on IRC.
What I really wanted is to be able to run my filters while using the normal
QEMU USB driver.
I'm not sure how MTP even works so I figured that before I learn anything
about MTP I'll check here to see if I can implement this easily and
contribut
On 04/25/18 16:07, Gerd Hoffmann wrote:
> Hi,
>
>>> We should make sure that any device model that combines ramfb with
>>> another PCI display device is not matched by the OVMF driver for that
>>> PCI display device. IOW, we should use separate PCI IDs or subsystem
>>> IDs (I don't recall the de
On 04/25/2018 03:03 PM, Dr. David Alan Gilbert (git) wrote:
> From: Alexey Perevalov
>
> Postcopy total blocktime is available on destination side only.
> But query-migrate was possible only for source. This patch
> adds ability to call query-migrate on destination.
> To be able to see postcopy b
On 04/25/2018 03:03 PM, Dr. David Alan Gilbert (git) wrote:
> From: Alexey Perevalov
>
> Right now it could be used on destination side to
> enable vCPU blocktime calculation for postcopy live migration.
> vCPU blocktime - it's time since vCPU thread was put into
> interruptible sleep, till memor
On 04/25/2018 09:44 AM, Max Reitz wrote:
> Here's what you do:
> (1) Create a 513 TB image with cluster_size=2M,refcount_bits=1
> (2) Take a hex editor and enter 16 refblocks into the reftable
> (3) Fill all of those refblocks with 1s
>
> (Funny side note: qemu-img check thinks that image is clea
Hi Corey,
On 04/25/2018 12:27 PM, miny...@acm.org wrote:
> From: Corey Minyard
>
> The vmstate for isa_ipmi_bt was referencing into the bt structure,
> instead create a bt structure separate and use that.
>
> The version 1 of the BT transfer was fairly broken, if a migration
> occured during an
Omer Katz writes:
> What would be a simpler way to do this so that the guest machine would
> still be able to recognize the USB drive?
> Right now we're triggering a script whenever udev recognizes that a USB
> drive is plugged in.
> The script copies the allowed files to a certain folder. The gu
From: Xiao Guangrong
The function is called by both ram_save_page and ram_save_target_page,
so move it to the common caller to cleanup the code
Reviewed-by: Peter Xu
Signed-off-by: Xiao Guangrong
Message-Id: <20180330075128.26919-8-xiaoguangr...@tencent.com>
Signed-off-by: Dr. David Alan Gilbe
From: Xiao Guangrong
Now, we can reuse the path in ram_save_page() to post the page out
as normal, then the only thing remained in ram_save_compressed_page()
is compression that we can move it out to the caller
Reviewed-by: Peter Xu
Reviewed-by: Dr. David Alan Gilbert
Signed-off-by: Xiao Guang
From: Xiao Guangrong
Abstract the common function control_save_page() to cleanup the code,
no logic is changed
Reviewed-by: Peter Xu
Reviewed-by: Dr. David Alan Gilbert
Signed-off-by: Xiao Guangrong
Message-Id: <20180330075128.26919-6-xiaoguangr...@tencent.com>
Signed-off-by: Dr. David Alan G
From: Xiao Guangrong
save_zero_page() is always our first approach to try, move it to
the common place before calling ram_save_compressed_page
and ram_save_page
Reviewed-by: Peter Xu
Reviewed-by: Dr. David Alan Gilbert
Signed-off-by: Xiao Guangrong
Message-Id: <20180330075128.26919-9-xiaoguan
From: Xiao Guangrong
Currently the page being compressed is allowed to be updated by
the VM on the source QEMU, correspondingly the destination QEMU
just ignores the decompression error. However, we completely miss
the chance to catch real errors, then the VM is corrupted silently
To make the mi
From: Xiao Guangrong
Current code uses uncompress() to decompress memory which manages
memory internally, that causes huge memory is allocated and freed
very frequently, more worse, frequently returning memory to kernel
will flush TLBs
So, we maintain the memory by ourselves and reuse it for eac
From: Alexey Perevalov
Postcopy total blocktime is available on destination side only.
But query-migrate was possible only for source. This patch
adds ability to call query-migrate on destination.
To be able to see postcopy blocktime, need to request postcopy-blocktime
capability.
The query-migr
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