Signed-off-by: Alexey Kardashevskiy
---
hw/vfio/pci.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/hw/vfio/pci.h b/hw/vfio/pci.h
index c5e168e..06dcf99 100644
--- a/hw/vfio/pci.h
+++ b/hw/vfio/pci.h
@@ -93,8 +93,6 @@ typedef struct VFIOMSIXInfo {
uint16_t entries;
uint32_t table
Intel IceLake cpu has added new cpu features,AVX512_VBMI2/GFNI/
VAES/VPCLMULQDQ/AVX512_VNNI/AVX512_BITALG. Those new cpu features
need expose to guest VM.
The bit definition:
CPUID.(EAX=7,ECX=0):ECX[bit 06] AVX512_VBMI2
CPUID.(EAX=7,ECX=0):ECX[bit 08] GFNI
CPUID.(EAX=7,ECX=0):ECX[bit 09] VAES
CPUI
Dne 22.11.2017 v 01:16 John Snow napsal(a):
> Both of these tests are for formats which now stipulate that they are
> read-only. Adjust the tests to match.
>
> Signed-off-by: John Snow
> ---
> tests/qemu-iotests/075 | 18 +-
> tests/qemu-iotests/078 | 14 +++---
> 2 files
This code is preventing the MMU debug code from displaying virtual
mappings of IO devices (anything that is not located in the RAM).
Before this patch, Qemu would output 0x (-1) as the
physical address corresponding to a IO device virtual address.
With this patch the intended phys
Sorry again, "MPIDR"
Gotta learn to type!
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1733720
Title:
raspi2 with multiple CPU's #1
Status in QEMU:
Invalid
Bug description:
Greetings,
I
NOT A BUG
Reviewed the code and found the problem.
asm volatile("mrc p15, 0, %[id], c0, c0, 0 @ read MIDR\n\t" ...
I miscopied the code above; MIDR should have been MIPDR ( 5 )
I now get:
Linux:armv7l: ~/Downloads/RaspiTest/BareBones >>> ./qemu.sh
0H312ello, kernel World!
Sorry about the bog
On some platforms INTx may not be enabled on a KVM host (one such
example is IBM pHyp hypervisor and this is intentional). However
the PCI_INTERRUPT_PIN is not 0 so QEMU tries initializing INTx, fails as
(!vdev->pdev->irq) in the VFIO's vfio_intx_enable() and this is
a fatal error.
This adds a deb
The vfio_iommu_spapr_tce driver always advertises v1 and v2 IOMMU support,
however PR KVM (a special version of KVM designed to work in
a paravirtualized system; these days used for nested virtualizaion) only
supports the "pseries" platform which does not support v2. Since there is
no way to choose
在 2017/11/22 上午2:07, Pierre Morel 写道:
On 21/11/2017 11:42, Cornelia Huck wrote:
On Thu, 16 Nov 2017 18:51:52 +0100
Pierre Morel wrote:
Enhance the fault detection.
Fixup the precedence to check the destination path existance
before checking for the source accessibility.
Add the maxstbl en
Hi all. Firstly, sorry if it's the wrong place to ask such a question!
In the early stages of boot process, kernel need identity mapped page
setup when switching gdt
[https://github.com/torvalds/linux/blob/ed30b147e1f6e396e70a52dbb6c7d66befedd786/arch/x86/kernel/head_64.S#L133-L137]
as code here
Public bug reported:
Greetings,
I am running a small program for raspi2 (from
http://wiki.osdev.org/ARM_RaspberryPi_Tutorial_C).
This code writes "Hello World", but the output ir repeated 4 times.
My thought was that this is emulating a 4 cpu core system.
However, when I check the MPIDR regist
On 11/21/2017 10:12 PM, David Gibson wrote:
...
> I've applied several patches from this series to ppc-for-2.12, others
> I've commented on. If you could address the comments and rebase
> what's left on ppc-for-2.12, that would be great.
Will do.
signature.asc
Description: OpenPGP digital sign
On 11/21/2017 09:46 PM, David Gibson wrote:
> On Sun, Nov 19, 2017 at 09:24:11PM -0600, Michael Davidsaver wrote:
>> Signed-off-by: Michael Davidsaver
>
> I'm not sure if you're saying you think there is a hardware bug which
> we're faithfully emulating, or a software bug.
I mean that the emulat
From: Laurent Vivier
Migration of a system under stress (for example, with
"stress-ng --numa 2") triggers on the destination
some kernel watchdog messages like:
NMI watchdog: BUG: soft lockup - CPU#0 stuck for 3489660870s!
NMI watchdog: BUG: soft lockup - CPU#1 stuck for 3489660884s!
This probl
The spapr-vty device implements the PAPR defined virtual console,
which is also implemented by IBM's proprietary PowerVM hypervisor.
PowerVM's implementation has a bug where it inserts an extra \0 after
every \r going to the guest. Because of that Linux's guest side
driver has a workaround which
The following changes since commit a15d835f00dce270fd3194e83d9910f4b5b44ac0:
Update version for v2.11.0-rc2 release (2017-11-21 17:50:36 +)
are available in the Git repository at:
git://github.com/dgibson/qemu.git tags/ppc-for-2.11-20171122
for you to fetch changes up to 6dd836f5d32b989
From: Thomas Huth
LUNs >= 256 have to be encoded with the so-called "flat space
addressing method" for virtio-scsi, where an additional bit has to
be set. SLOF already took care of this with the following commit:
https://git.qemu.org/?p=SLOF.git;a=commitdiff;h=f72a37713fea47da
(see https://bug
On Sun, Nov 19, 2017 at 09:24:16PM -0600, Michael Davidsaver wrote:
> Signed-off-by: Michael Davidsaver
You're adding what seems to be a fairly specific device to the general
e500 init - this again suggests that it should be split, putting
creation of devices under control of individual machines.
On Sun, Nov 19, 2017 at 09:24:17PM -0600, Michael Davidsaver wrote:
> Signed-off-by: Michael Davidsaver
Applied to ppc-for-2.12.
> ---
> hw/nvram/Makefile.objs | 1 +
> hw/nvram/eeprom_at24c.c | 205
>
> 2 files changed, 206 insertions(+)
>
On Sun, Nov 19, 2017 at 09:24:08PM -0600, Michael Davidsaver wrote:
> This series adds simulation of MVME3100 powerpc SBCs, originally from
> Motorola,
> and now sold by Artesyn[1]. There are two variants differing in CPU
> speed and memory size.
>
> I've been working on this sporadically for th
On Sun, Nov 19, 2017 at 09:24:09PM -0600, Michael Davidsaver wrote:
> allow board code to skip common NIC and guest image setup
> and configure decrementor frequency.
> Existing boards unchanged.
>
> Signed-off-by: Michael Davidsaver
So, it's spelled "decrementer".
Other than that, the patch lo
On Sun, Nov 19, 2017 at 09:24:14PM -0600, Michael Davidsaver wrote:
> Signed-off-by: Michael Davidsaver
I can't speak to the accuracy of the emulation, but it's presumably
better than nothing at all. Therefore, applied to ppc-for-2.12.
> ---
> hw/i2c/Makefile.objs | 1 +
> hw/i2c/mpc8540_i2c
On Sun, Nov 19, 2017 at 09:24:10PM -0600, Michael Davidsaver wrote:
> Preparation for adding more MPC control
> registers.
>
> Use e500 SVR to enable part specific registers.
> Only the mpc8544 reset register at present.
>
> Expose CCSR as SysBusDevice region to eliminate
> e500-ccsr.h.
>
>
On Sun, Nov 19, 2017 at 09:24:12PM -0600, Michael Davidsaver wrote:
> Add CCSRBAR to allow CCSR region to be relocated.
> Guest memory size introspection.
> Dummy RAM error controls.
> Guest clock introspection.
>
> Signed-off-by: Michael Davidsaver
Looks fine from the POV of someone who doesn't
On Sun, Nov 19, 2017 at 09:24:13PM -0600, Michael Davidsaver wrote:
> Signed-off-by: Michael Davidsaver
Applied to ppc-for-2.12.
> ---
> hw/ppc/e500.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
> index 057be1751b..6f77844303 100644
> --- a/hw/ppc
On Sun, Nov 19, 2017 at 09:24:11PM -0600, Michael Davidsaver wrote:
> Signed-off-by: Michael Davidsaver
I'm not sure if you're saying you think there is a hardware bug which
we're faithfully emulating, or a software bug.
> ---
> hw/pci-host/ppce500.c | 3 +++
> 1 file changed, 3 insertions(+)
>
On Sun, Nov 19, 2017 at 09:24:18PM -0600, Michael Davidsaver wrote:
> only basic functionality implemented (read time and sram).
> no set time or alarms.
>
> Signed-off-by: Michael Davidsaver
I know there about a zillion different Dallas/Maxim sram/rtc chips,
many of which have a lot of similari
Quoting Christian Borntraeger (2017-11-21 15:38:32)
> forgot to cc qemu-devel
>
> On 11/21/2017 10:37 PM, Christian Borntraeger wrote:
> > a quick heads up . Rc2 now triggers
> > +qemu-img: block/block-backend.c:2088: blk_root_drained_end: Assertion
> > `blk->quiesce_counter' failed.
> > for
On Mon, Nov 20, 2017 at 11:03:46AM +0100, Cédric Le Goater wrote:
> Just like for hot unplug CPUs, when a guest is rebooted, the secondary
> CPUs can be awaken by the decrementer and start entering SLOF at the
> same time the boot CPU is.
>
> To be safe, let's disable on the secondaries all the ex
On Mon, Nov 20, 2017 at 11:03:45AM +0100, Cédric Le Goater wrote:
> When a CPU is stopped with the 'stop-self' RTAS call, its state
> 'halted' is switched to 1 and, in this case, the MSR is not taken into
> account anymore in the cpu_has_work() routine. Only the pending
> hardware interrupts are ch
Cc: John Snow
Cc: Kevin Wolf
Cc: Max Reitz
Cc: Keith Busch
Cc: Stefan Hajnoczi
Cc: "Michael S. Tsirkin"
Cc: Paolo Bonzini
Cc: Gerd Hoffmann
Cc: Markus Armbruster
Signed-off-by: Mao Zhongyi
Reviewed-by: Stefan Hajnoczi
---
hw/block/fdc.c| 17 ++---
hw/block/nvme.c
The function name of usb_msd_{realize,unrealize}_*,
usb_msd_class_initfn_* are unusual. Rename it to
usb_msd_*_{realize,unrealize}, usb_msd_class_*_initfn.
Cc: Gerd Hoffmann
Signed-off-by: Mao Zhongyi
Reviewed-by: Philippe Mathieu-Daudé
---
hw/usb/dev-storage.c | 20 ++--
1 fi
When the function no success value to transmit, it usually make the
function return void. It has turned out not to be a success, because
it means that the extra local_err variable and error_propagate() will
be needed. It leads to cumbersome code, therefore, transmit success/
failure in the return v
This series mainly implements the conversions of ide, floppy and nvme
device to realize. Add some error handling messages and remove the local
variable local_err, use errp to propagate the error directly. Also
fix the unusual function name.
v4:
-rebased it on top of block-next branch
v3:
-pat
Convert nvme_init() to realize and rename it to nvme_realize().
Cc: John Snow
Cc: Keith Busch
Cc: Kevin Wolf
Cc: Max Reitz
Cc: Markus Armbruster
Signed-off-by: Mao Zhongyi
---
hw/block/nvme.c | 18 ++
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/hw/block/n
> -Original Message-
> From: Michael S. Tsirkin [mailto:m...@redhat.com]
> Sent: Tuesday, November 21, 2017 4:45 AM
> To: Stefan Hajnoczi
> Cc: Liu, Changpeng ; qemu-devel@nongnu.org;
> pbonz...@redhat.com; marcandre.lur...@redhat.com; fel...@nutanix.com;
> Harris, James R
> Subject: Re
> -Original Message-
> From: Stefan Hajnoczi [mailto:stefa...@gmail.com]
> Sent: Tuesday, November 21, 2017 12:27 AM
> To: Liu, Changpeng
> Cc: qemu-devel@nongnu.org; pbonz...@redhat.com; m...@redhat.com;
> marcandre.lur...@redhat.com; fel...@nutanix.com; Harris, James R
>
> Subject: Re
On 07/11/17 11:58, John Snow wrote:
>
>
> On 10/26/2017 02:46 AM, Alexey Kardashevskiy wrote:
>> A "powernv" machine type defines an ISA bus but it does not add any DMA
>> controller to it so it is possible to hit assert(fdctrl->dma) by
>> adding "-machine powernv -device isa-fdc".
>>
>> This rep
> -Original Message-
> From: Paolo Bonzini [mailto:pbonz...@redhat.com]
> Sent: Tuesday, November 21, 2017 8:16 AM
> To: Michael S. Tsirkin ; Stefan Hajnoczi
> Cc: Liu, Changpeng ; qemu-devel@nongnu.org;
> marcandre.lur...@redhat.com; fel...@nutanix.com; Harris, James R
>
> Subject: Re:
Hi, Kevin
On 11/10/2017 10:25 PM, Kevin Wolf wrote:
Am 19.09.2017 um 01:59 hat John Snow geschrieben:
On 09/18/2017 10:05 AM, Mao Zhongyi wrote:
This series mainly implements the conversions of ide, floppy and nvme
device to realize. Add some error handling messages and remove the local
variab
On 11/21/2017 06:16 PM, John Snow wrote:
> Both of these tests are for formats which now stipulate that they are
> read-only. Adjust the tests to match.
>
> Signed-off-by: John Snow
> ---
> tests/qemu-iotests/075 | 18 +-
> tests/qemu-iotests/078 | 14 +++---
> 2 files ch
Hi,
This series failed build test on s390x host. Please find the details below.
Subject: [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations
Type: series
Message-id: 20171121212534.5177-1-richard.hender...@linaro.org
=== TEST SCRIPT BEGIN ===
#!/bin/bash
# Testing script will be invoked
Both of these tests are for formats which now stipulate that they are
read-only. Adjust the tests to match.
Signed-off-by: John Snow
---
tests/qemu-iotests/075 | 18 +-
tests/qemu-iotests/078 | 14 +++---
2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/te
CC Jeff Cody
... who may or may not be preoccupied with Thanksgiving travel now.
Convenient URL for reading past replies:
https://lists.nongnu.org/archive/html/qemu-devel/2017-11/msg03844.html
On 11/21/2017 10:31 AM, Alberto Garcia wrote:
> On Tue 21 Nov 2017 04:18:13 PM CET, Anton Nefedov wrote
On 11/21/2017 12:23 PM, Kevin Wolf wrote:
> Am 17.11.2017 um 22:35 hat John Snow geschrieben:
> usage is like this:
>
> 1. we have dirty bitmap bitmap0 for incremental backup.
>
> 2. prepare image fleecing (create temporary image with backing=our_disk)
> 3. in qmp transact
The last sub-test in 059, which uses an AFL fuzzer image to test for how
a large L1 table of a specific size is handled has a slight regression.
Previously, QEMU expects -EFBIG to come out the vmdk_open call. Now, we
get -EINVAL. Not too ominous.
Now, QEMU actually allocates the L1 table (1.6GB)
On Tue, Nov 21, 2017 at 09:16:43PM +0100, Laurent Vivier wrote:
> Migration of a system under stress (for example, with
> "stress-ng --numa 2") triggers on the destination
> some kernel watchdog messages like:
>
> NMI watchdog: BUG: soft lockup - CPU#0 stuck for 3489660870s!
> NMI watchdog: BUG: s
Hi,
This series failed automatic build test. Please find the testing commands and
their output below. If you have docker installed, you can probably reproduce it
locally.
Subject: [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations
Type: series
Message-id: 20171121212534.5177-1-richard.h
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations
Type: series
Message-id: 20171121212534.5177-1-richard.hender...@linaro.org
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
Commit 2b7731938d9 adds a blkdebug driver test for failing commits, but
the vmdk driver doesn't appear to appreciate this format:
+_qemu_img_wrapper create -f vmdk -b "json:{'driver': 'raw',
+ 'file': {
+ 'driver': 'blkdebug',
+
Signed-off-by: Richard Henderson
---
accel/tcg/tcg-runtime.h | 5 +
tcg/i386/tcg-target.h| 1 +
tcg/tcg-op-gvec.h| 2 ++
tcg/tcg-op.h | 1 +
tcg/tcg-opc.h| 1 +
tcg/tcg.h| 1 +
accel/tcg/tcg-runtime-gvec.c | 44
forgot to cc qemu-devel
On 11/21/2017 10:37 PM, Christian Borntraeger wrote:
> a quick heads up . Rc2 now triggers
> +qemu-img: block/block-backend.c:2088: blk_root_drained_end: Assertion
> `blk->quiesce_counter' failed.
> for several qemu iotests.
>
> I have not looked into any details.
>
Signed-off-by: Richard Henderson
---
accel/tcg/tcg-runtime.h | 30 +++
tcg/i386/tcg-target.h| 1 +
tcg/tcg-op-gvec.h| 4 +
tcg/tcg-op.h | 3 +
tcg/tcg-opc.h| 2 +
tcg/tcg.h| 1 +
accel/tcg/tcg-runtime-gvec
There are some wrong hid usage mapping in hid_usage_keys table.
It can be confirmed with "sendkey" command in monitor and verify
the behavior in guest OS.
This CL fixed some wrong hid usage mapping for these keys:
kp_equals kp_comma audiomute volumedown volumeup power
There still are some wrong m
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 386 ++---
tcg/tcg-op-gvec.c | 18 ++-
tcg/tcg-op-vec.c | 9 +-
3 files changed, 351 insertions(+), 62 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm
Signed-off-by: Richard Henderson
---
accel/tcg/tcg-runtime.h | 8 +++
tcg/i386/tcg-target.h| 2 +
tcg/tcg-op-gvec.h| 9 +++
tcg/tcg-op.h | 5 ++
tcg/tcg-opc.h| 5 ++
tcg/tcg.h| 2 +
accel/tcg/tcg-runtime-gvec
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 103 +++--
1 file changed, 35 insertions(+), 68 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 55a4902fc2..8769b4505a 100644
--- a/target/arm/transla
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.h | 4 +-
tcg/i386/tcg-target.opc.h | 1 +
tcg/i386/tcg-target.inc.c | 186 ++
3 files changed, 174 insertions(+), 17 deletions(-)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 96 ++
1 file changed, 62 insertions(+), 34 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index c47faa5633..1ea7e37b03 100644
--- a/target/arm/transla
I just reported the bug in the kernel:
https://bugzilla.kernel.org/show_bug.cgi?id=197951
If you reported or commented on the bug here, please go comment on that
report confirming as well. A lot of open-source bugzilla projects tend
to rarely pay attention to bug reports that only one person has
c
The x86 vector instruction set is extremely irregular. With newer
editions, Intel has filled in some of the blanks. However, we don't
get many 64-bit operations until SSE4.2, introduced in 2009.
The subsequent edition was for AVX1, introduced in 2011, which added
three-operand addressing, and ad
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 29 -
1 file changed, 12 insertions(+), 17 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index c47d9caa49..1f7e9c4e19 100644
--- a/target/arm/translate-a64.c
+++ b/ta
Includes zip, unzip, and transform.
Signed-off-by: Richard Henderson
---
accel/tcg/tcg-runtime.h | 15 ++
tcg/i386/tcg-target.h| 3 +
tcg/tcg-op-gvec.h| 17 +++
tcg/tcg-op.h | 6 +
tcg/tcg-opc.h| 7 +
tcg/tcg.h|
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 207 +
1 file changed, 134 insertions(+), 73 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index ba94f7d045..572af456d1 1006
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.h | 6 +-
tcg/i386/tcg-target.opc.h | 7 +
tcg/i386/tcg-target.inc.c | 595 +-
3 files changed, 598 insertions(+), 10 deletions(-)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.h | 30 +-
tcg/aarch64/tcg-target.opc.h | 3 +
tcg/aarch64/tcg-target.inc.c | 674 ---
3 files changed, 660 insertions(+), 47 deletions(-)
create mode 100644 tcg/aarch64/tcg-target.opc.h
d
Nothing uses or enables them yet.
Signed-off-by: Richard Henderson
---
Makefile.target | 4 +-
tcg/tcg-op.h | 30 +
tcg/tcg-opc.h| 26
tcg/tcg.h| 56 +
tcg/tcg-op-vec.c | 362 +++
tcg/tcg.c| 100 ++
Signed-off-by: Richard Henderson
---
Makefile.target |2 +-
accel/tcg/tcg-runtime.h | 29 ++
tcg/tcg-gvec-desc.h | 49 ++
tcg/tcg-op-gvec.h| 152 +++
tcg/tcg-op.h |1 +
accel/tcg/tcg-runtime-gvec.c | 295
tcg/tc
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 171 -
1 file changed, 138 insertions(+), 33 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 1ea7e37b03..c47d9caa49 100644
--- a/target/arm/transl
Opcodes are added for scalar and vector shifts, but considering the
varied semantics of these do not expose them to the front ends. Do
go ahead and provide them in case they are needed for backend expansion.
Signed-off-by: Richard Henderson
---
accel/tcg/tcg-runtime.h | 15 +++
tcg/i386/t
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 89d49cdcb2..8238edaba9 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -492,7 +492,7 @@ typedef str
This will be required for storing vector constants.
Signed-off-by: Richard Henderson
---
tcg/tcg-pool.inc.c | 115 +++--
1 file changed, 93 insertions(+), 22 deletions(-)
diff --git a/tcg/tcg-pool.inc.c b/tcg/tcg-pool.inc.c
index 8a85131405..0f76e
These will be useful in the next few patches adding shifts,
permutes, and multiplication.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.opc.h | 3 +++
tcg/tcg-opc.h | 6 ++
tcg/tcg.h | 11 +++
tcg/i386/tcg-target.inc.c | 21 +++
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 43 ++-
1 file changed, 38 insertions(+), 5 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 572af456d1..bc14c28e71 100644
--- a/target/arm/translate-a
These are now trivial sets and tests against NULL. Unwrap.
Signed-off-by: Richard Henderson
---
tcg/tcg-op.h | 4 ---
tcg/tcg.h| 9 ---
target/alpha/translate.c | 22
target/arm/translate-a64.c | 35 +++-
targe
With no fixed array allocation, we can't overflow a buffer.
This will be important as optimizations related to host vectors
may expand the number of ops used.
Use QTAILQ to link the ops together.
Signed-off-by: Richard Henderson
---
include/exec/gen-icount.h | 9 ++--
include/qemu/queue.h
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 83 +++---
1 file changed, 34 insertions(+), 49 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index bc14c28e71..55a4902fc2 100644
--- a/target/arm/transla
Quite a lot has changed since last time.
The representation has changed such that the vector length and element
size is stored in the TCGOp structure. The functions have changed such
that the element size is passed explicitly rather than being encoded in
the function name.
I've added additional
We had two fields specific to INDEX_op_call. Rename these and
add some macros so that the fields may be reused for other opcodes.
Signed-off-by: Richard Henderson
---
tcg/tcg.h | 10 ++
tcg/optimize.c | 4 ++--
tcg/tcg.c | 22 +++---
3 files changed, 19 insert
Complimenting the existing tcg_unsigned_cond.
Signed-off-by: Richard Henderson
---
tcg/tcg.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 2acebd387a..49d4c5fe05 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -517,6 +517,12 @@ static inline TCGCond tcg_unsigned
I have yet to try disabling swap, but in the 5 days since I downgraded
the kernel to 4.12.12 from 4.12.13, I have not had a single BSOD. I
think 4.12.13 is the culprit.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.laun
Am 16.11.2017 um 17:37 schrieb Stefan Weil:
> It was broken by commit 8ecc89f6e792152496eccb684d6c8c48aba8027d which
> moved the SDL linker flags from macro libs_softmmu to macro SDL_LIBS.
>
> Signed-off-by: Stefan Weil
> ---
>
> Peter, can you apply this fix directly, or do you need a pull requ
I am on Arch as well, using a customized kernel using the vfio patchset
(in this case 4.13.11). I was having the same issue as you guys, where
my Windows 10 VM with an NVIDIA card passed in was getting the
CRITICAL_STRUCTURE_CORRUPTION blue screen error message after running
for a while. Usually I
Migration of a system under stress (for example, with
"stress-ng --numa 2") triggers on the destination
some kernel watchdog messages like:
NMI watchdog: BUG: soft lockup - CPU#0 stuck for 3489660870s!
NMI watchdog: BUG: soft lockup - CPU#1 stuck for 3489660884s!
This problem appears with the cha
On 11/21/2017 04:07 PM, Peter Maydell wrote:
> The cpu-exec-common.c file includes memory-internal.h, but it doesn't
> actually use anything from that header. Remove the unnecessary include.
>
> Signed-off-by: Peter Maydell
> ---
> accel/tcg/cpu-exec-common.c | 1 -
> 1 file changed, 1 deletion(
Hello,
On behalf of the QEMU Team, I'd like to announce the availability of the
third release candidate for the QEMU 2.11 release. This release is meant
for testing purposes and should not be used in a production environment.
http://download.qemu-project.org/qemu-2.11.0-rc2.tar.xz
http://dow
* Juan Quintela (quint...@redhat.com) wrote:
> Daniel Henrique Barboza wrote:
> > When migrating a VM with 'migrate_set_capability postcopy-ram on'
> > a postcopy_state is set during the process, ending up with the
> > state POSTCOPY_INCOMING_END when the migration is over. This
> > postcopy_state
36 +)
>
> are available in the git repository at:
>
> git://github.com/juanquintela/qemu.git tags/migration/20171121
>
> for you to fetch changes up to 383d8a77222c016610d626887de80e770cdd9936:
>
> migration/ram.c: do not set 'postcopy_running
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v3 00/45] Windbg supporting
Type: series
Message-id: 151127322955.6888.16198535123422076171.st...@misha-pc.lan02.inno
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
From: Anthony PERARD
When doing a live migration of a Xen guest with libxl, the images for
block devices are locked by the original QEMU process, and this prevent
the QEMU at the destination to take the lock and the migration fail.
>From QEMU point of view, once the RAM of a domain is migrated,
From: Daniel Henrique Barboza
When migrating a VM with 'migrate_set_capability postcopy-ram on'
a postcopy_state is set during the process, ending up with the
state POSTCOPY_INCOMING_END when the migration is over. This
postcopy_state is taken into account inside ram_load to check
how it will loa
tags/migration/20171121
for you to fetch changes up to 383d8a77222c016610d626887de80e770cdd9936:
migration/ram.c: do not set 'postcopy_running' in POSTCOPY_INCOMING_END
(2017-11-21 19:42:26 +0100)
migration/next fo
On 8 November 2017 at 11:32, KONRAD Frederic
wrote:
> We want to add this model to the xlnx-zynqmp board so let's make
> CadenceTTCState available in an header file.
>
> Signed-off-by: KONRAD Frederic
> ---
> hw/timer/cadence_ttc.c | 35 +---
> include/hw/timer/cadenc
Anthony PERARD wrote:
> When doing a live migration of a Xen guest with libxl, the images for
> block devices are locked by the original QEMU process, and this prevent
> the QEMU at the destination to take the lock and the migration fail.
>
> From QEMU point of view, once the RAM of a domain is mi
Daniel Henrique Barboza wrote:
> When migrating a VM with 'migrate_set_capability postcopy-ram on'
> a postcopy_state is set during the process, ending up with the
> state POSTCOPY_INCOMING_END when the migration is over. This
> postcopy_state is taken into account inside ram_load to check
> how i
On 3 November 2017 at 00:00, Francisco Iglesias
wrote:
> Hi,
>
> This patch series is an attempt to add support for the ZynqMP QSPI (consisting
> of the Generic QSPI and the legacy QSPI) to the xlnx-zcu102 board and connect
> Numonyx n25q512a11 flashes to the QSPI. Also some functionality is added
On Tue, 2017-11-21 at 10:26 -0800, Dan Williams wrote:
> On Tue, Nov 21, 2017 at 10:19 AM, Rik van Riel
> wrote:
> > On Fri, 2017-11-03 at 14:21 +0800, Xiao Guangrong wrote:
> > > On 11/03/2017 12:30 AM, Dan Williams wrote:
> > > >
> > > > Good point, I was assuming that the mmio flush interface
On 6 November 2017 at 15:47, Andrey Smirnov wrote:
> Hi everyone,
> - Added proper USB emulation code, so now it should be possible to
> emulated guest's USB bus
The patchset is huge as it is, if you add more stuff to it
it makes it even more likely to sink to the bottom of my
to-review
On Tue, Nov 21, 2017 at 10:19 AM, Rik van Riel wrote:
> On Fri, 2017-11-03 at 14:21 +0800, Xiao Guangrong wrote:
>> On 11/03/2017 12:30 AM, Dan Williams wrote:
>> >
>> > Good point, I was assuming that the mmio flush interface would be
>> > discovered separately from the NFIT-defined memory range.
On 6 November 2017 at 15:48, Andrey Smirnov wrote:
> Implement code needed to set up emulation of MCIMX7SABRE board from
> NXP. For more info about the HW see:
>
> https://www.nxp.com/support/developer-resources/hardware-development-tools/sabre-development-system/sabre-board-for-smart-devices-base
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