On 2017/4/12 22:28, Eric Blake wrote:
On 04/12/2017 09:05 AM, zhanghailiang wrote:
We use these two options to identify which disk is
shared
Signed-off-by: zhanghailiang
Signed-off-by: Wen Congyang
Signed-off-by: Zhang Chen
---
v4:
- Add proper comment for primary_disk (Stefan)
v2:
- Move g_
On Tue, Apr 11, 2017 at 08:18:49AM -0500, Eric Blake wrote:
> On 04/11/2017 03:49 AM, He Chen wrote:
> > This patch is going to add SLIT table support in QEMU, and provides
> > additional option `dist` for command `-numa` to allow user set vNUMA
> > distance by QEMU command.
> >
> > With this patc
Hi Peter,
On 04/10/2017 02:13 PM, Peter Maydell wrote:
For M profile exception-return handling we'd like to generate different
code for some instructions depending on whether we are in Handler
mode or Thread mode. This isn't the same as "are we privileged
or user", so we need an extra bit in the
On 02/16/2017 01:35 PM, Peter Maydell wrote:
From: Michael Davidsaver
Now that the NVIC is its own separate implementation, we can
clean up the GIC code by removing REV_NVIC and conditionals
which use it.
Signed-off-by: Michael Davidsaver
Signed-off-by: Peter Maydell
Reviewed-by: Alex Bennée
On 02/20/2017 03:51 PM, Peter Maydell wrote:
On 20 February 2017 at 17:43, Philippe Mathieu-Daudé wrote:
On 02/20/2017 12:36 PM, Peter Maydell wrote:
+/* Conversion factor from qemu timer to SysTick frequencies. */
+static inline int64_t systick_scale(SysTickState *s)
+{
+if (s->control &
On Mon, Apr 17, 2017 at 11:49 AM, Fam Zheng wrote:
> On Fri, 04/14 14:30, 858585 jemmy wrote:
>> Do you know some other format which have very small cluster size?
>
> 64k is the default cluster size for qcow2 but it can be configured at image
> creation time, as 512 bytes, for example:
>
> $ q
Hi Peter,
On Mon, Feb 20, 2017 at 12:35 PM, Peter Maydell
wrote:
> Create a proper QOM object for the armv7m container, which
> holds the CPU, the NVIC and the bitband regions.
>
> Signed-off-by: Peter Maydell
> ---
> include/hw/arm/armv7m.h | 51 ++
> hw/arm/armv7m.c
On Fri, Apr 14, 2017 at 07:40:56PM +0200, Maxime Coquelin wrote:
[...]
> +IOMMU support
> +-
> +
> +When the VIRTIO_F_IOMMU_PLATFORM feature has been negotiated, the master has
> +to send IOTLB entries update & invalidation by sending VHOST_USER_IOTLB_MSG
> +requests to the slave with
On Fri, 04/14 14:30, 858585 jemmy wrote:
> Do you know some other format which have very small cluster size?
64k is the default cluster size for qcow2 but it can be configured at image
creation time, as 512 bytes, for example:
$ qemu-img create -f qcow2 test.qcow2 -o cluster_size=512 1G
Fam
On 02/16/2017 01:36 PM, Peter Maydell wrote:
Extract the code from the tail end of arm_v7m_do_interrupt() which
enters the exception handler into a pair of utility functions
v7m_exception_taken() and v7m_push_stack(), which correspond roughly
to the pseudocode PushStack() and ExceptionTaken().
T
On Fri, 04/14 14:48, 858585 jemmy wrote:
> >> Effectively, if no cluster is zero, this patch still splits a big write
> >> into
> >> small ones, which is the opposition of usual performance optimizations
> >> (i.e.
> >> trying to coalesce requests).
> >
> > Good point!
> >
> > Another patch can m
On 02/16/2017 01:35 PM, Peter Maydell wrote:
From: Michael Davidsaver
All the places in armv7m_cpu_do_interrupt() which pend an
exception in the NVIC are doing so for synchronous
exceptions. We know that we will always take some
exception in this case, so we can just acknowledge it
immediately,
On 02/16/2017 01:35 PM, Peter Maydell wrote:
Having armv7m_nvic_acknowledge_irq() return the new value of
env->v7m.exception and its one caller assign the return value
back to env->v7m.exception is pointless. Just make the return
type void instead.
Signed-off-by: Peter Maydell
Reviewed-by: Alex
On 04/15/2017 05:38 AM, Michael S. Tsirkin wrote:
On Fri, Apr 14, 2017 at 04:37:52PM +0800, Wei Wang wrote:
On 04/14/2017 12:34 AM, Michael S. Tsirkin wrote:
On Thu, Apr 13, 2017 at 05:35:05PM +0800, Wei Wang wrote:
So we don't need the bitmap to talk to host, it is just
a data structure we ch
On Sun, 04/16 10:37, Stefan Hajnoczi wrote:
> On Sat, Apr 15, 2017 at 01:10:02AM +0800, Paolo Bonzini wrote:
> >
> >
> > On 14/04/2017 16:51, Stefan Hajnoczi wrote:
> > > On Fri, Apr 14, 2017 at 9:02 AM, Fam Zheng wrote:
> > >> @@ -398,11 +399,15 @@ void bdrv_drain_all(void);
> > >> */
On Fri, Apr 14, 2017 at 07:40:55PM +0200, Maxime Coquelin wrote:
[...]
> @@ -486,6 +500,18 @@ Message types
>If VHOST_USER_PROTOCOL_F_REPLY_ACK is negotiated, slave must respond
>with zero in case the specified MTU is valid, or non-zero otherwise.
>
> + * VHOST_USER_SET_SLAVE_RE
On 02/20/2017 12:36 PM, Peter Maydell wrote:
Make the NVIC device expose a memory region for its users
to map, rather than mapping itself into the system memory
space on realize, and get the one user (the ARMv7M object)
to do this.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Da
On 02/20/2017 12:35 PM, Peter Maydell wrote:
Make the legacy armv7m_init() function use the newly QOMified
armv7m object rather than doing everything by hand.
We can return the armv7m object rather than the NVIC from
armv7m_init() because its interface to the rest of the
board (GPIOs, etc) is id
On 02/20/2017 12:35 PM, Peter Maydell wrote:
Create a proper QOM object for the armv7m container, which
holds the CPU, the NVIC and the bitband regions.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
---
include/hw/arm/armv7m.h | 51 ++
hw/arm/armv7m.c
On 02/02/2017 05:02 PM, Peter Maydell wrote:
From: Michael Davidsaver
Now that the NVIC is its own separate implementation, we can
clean up the GIC code by removing REV_NVIC and conditionals
which use it.
Signed-off-by: Michael Davidsaver
Signed-off-by: Peter Maydell
Reviewed-by: Philippe
We think this problem coulde be solevd in qga modules。can anybody give some
advice ?
[BUG] network : windows os lost ip address of the network card in some cases
we found this problem for a long time 。For example, if we has three network
card in virtual xml file ，such as "network connection
On 02/16/2017 01:35 PM, Peter Maydell wrote:
The M profile condition for when we can take a pending exception or
interrupt is not the same as that for A/R profile. The code
originally copied from the A/R profile version of the
cpu_exec_interrupt function only worked by chance for the
very simple
Hi,
This series failed automatic build test. Please find the testing commands and
their output below. If you have docker installed, you can probably reproduce it
locally.
Type: series
Subject: [Qemu-devel] [PATCH 0/6] calculate downtime for postcopy live migration
Message-id: 1492175840-5021-1-gi
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Subject: [Qemu-devel] [PATCH 0/6] calculate downtime for postcopy live migration
Message-id: 1492175840-5021-1-git-send-email-a.pereva...@samsung.com
=== TEST SCRIPT BEGIN ===
#!/bin/bas
Hi Daniel,
I will fix this error in V3, please continue reviewing V2.
Thx.
Regards,
Longpeng
On 2017/4/17 10:12, no-re...@patchew.org wrote:
> Hi,
>
> This series failed automatic build test. Please find the testing commands and
> their output below. If you have docker installed, you can proba
Hi,
This series failed automatic build test. Please find the testing commands and
their output below. If you have docker installed, you can probably reproduce it
locally.
Type: series
Subject: [Qemu-devel] [PATCH v2 for-2.10 00/18] crypto: add afalg-backend
support
Message-id: 1492392806-53720-1
Adds afalg-backend hmac support: introduces some private APIs
firstly, and then intergrates them into qcrypto_hmac_afalg_driver.
Signed-off-by: Longpeng(Mike)
---
crypto/hash-afalg.c | 108 +++---
crypto/hmac.c | 27 -
crypto/hma
Moves crypto/hmac.h into include/crypto/, likes cipher.h and hash.h
Signed-off-by: Longpeng(Mike)
---
crypto/hmac.h | 166 --
include/crypto/hmac.h | 166 ++
2 files changed, 166 insertions(+)
Adds afalg-backend cipher support: introduces some private APIs
firstly, and then intergrates them into qcrypto_cipher_afalg_driver.
Signed-off-by: Longpeng(Mike)
---
crypto/Makefile.objs | 1 +
crypto/afalgpriv.h | 9 ++
crypto/cipher-afalg.c | 225 +++
This patch add a hmac speed benchmark, it helps us to
measure the performance by using "make check-speed" or
using "./tests/benchmark-crypto-hmac" directly.
Signed-off-by: Longpeng(Mike)
---
tests/Makefile.include| 2 +
tests/benchmark-crypto-hmac.c | 96
This patch add a hash speed benchmark, it helps us to
measure the performance by using "make check-speed" or
using "./tests/benchmark-crypto-cipher" directly.
Signed-off-by: Longpeng(Mike)
---
tests/Makefile.include| 2 ++
tests/benchmark-crypto-hash.c | 67 +
Now we have two qcrypto backends, libiary-backend and afalg-backend,
but which one is faster? This patch add a cipher speed benchmark, it
helps us to measure the performance by using "make check-speed" or
using "./tests/benchmark-crypto-cipher" directly.
Signed-off-by: Longpeng(Mike)
---
tests/M
Adds afalg-backend hash support: introduces some private APIs
firstly, and then intergrates them into qcrypto_hash_afalg_driver.
Signed-off-by: Longpeng(Mike)
---
crypto/Makefile.objs | 1 +
crypto/afalgpriv.h | 1 +
crypto/hash-afalg.c | 151 ++
Extracts qcrypto_hmac_ctx_new() from qcrypto_hmac_new() for
nettle-backend impls.
Signed-off-by: Longpeng(Mike)
---
crypto/hmac-nettle.c | 34 --
1 file changed, 24 insertions(+), 10 deletions(-)
diff --git a/crypto/hmac-nettle.c b/crypto/hmac-nettle.c
index 4a9e
1) makes the public APIs in cipher-nettle/gcrypt/builtin static,
and rename them with "nettle/gcrypt/builtin" prefix.
2) introduces cipher framework, including QCryptoCipherDriver
and new public APIs.
Signed-off-by: Longpeng(Mike)
---
crypto/cipher-builtin.c | 64 +
1) makes the public APIs in hmac-nettle/gcrypt/glib static,
and rename them with "nettle/gcrypt/glib" prefix.
2) introduces hmac framework, including QCryptoHmacDriver
and new public APIs.
Signed-off-by: Longpeng(Mike)
---
crypto/hmac-gcrypt.c | 51 ---
cr
Extracts qcrypto_hmac_ctx_new() from qcrypto_hmac_new() for
glib-backend impls.
Signed-off-by: Longpeng(Mike)
---
crypto/hmac-glib.c | 34 --
1 file changed, 24 insertions(+), 10 deletions(-)
diff --git a/crypto/hmac-glib.c b/crypto/hmac-glib.c
index 08a1fdd..d9f
1) makes the public APIs in hash-nettle/gcrypt/glib static,
and rename them with "nettle/gcrypt/glib" prefix.
2) introduces hash framework, including QCryptoHashDriver
and new public APIs.
Signed-off-by: Longpeng(Mike)
---
crypto/hash-gcrypt.c | 19 +--
crypto/hash-glib.c
The AF_ALG socket family is the userspace interface for linux
crypto API, this patch adds af_alg family support and some common
functions for af_alg backend. It'll be used by afalg-backend crypto
latter.
Signed-off-by: Longpeng(Mike)
---
configure| 21 ++
crypto/Makefile.obj
The AF_ALG socket family is the userspace interface for linux
crypto API, users can use it to access hardware accelerators.
This patchset adds a afalg-backend for qemu crypto subsystem. Currently
when performs encrypt/decrypt, we'll try afalg-backend first and will
back to libiary-backend if it fa
Extracts qcrypto_cipher_ctx_new() from qcrypto_cipher_new() for
nettle-backend impls.
Signed-off-by: Longpeng(Mike)
---
crypto/cipher-nettle.c | 41 +
1 file changed, 29 insertions(+), 12 deletions(-)
diff --git a/crypto/cipher-nettle.c b/crypto/cipher-ne
1) Fix a handle-leak problem in qcrypto_hmac_new(), doesn't free
ctx->handle if gcry_mac_setkey fails.
2) Extracts qcrypto_hmac_ctx_new() from qcrypto_hmac_new() for
gcrypt-backend impls.
Signed-off-by: Longpeng(Mike)
---
crypto/hmac-gcrypt.c | 35 +--
1 fi
Refactors the qcrypto_cipher_free(), splits it into two parts. One
is gcrypt/nettle__cipher_free_ctx() to free the special context.
This makes code more clear, what's more, it would be used by the
later patch.
Signed-off-by: Longpeng(Mike)
---
crypto/cipher-gcrypt.c | 31 ++-
Extracts qcrypto_cipher_ctx_new() from qcrypto_cipher_new() for
builtin-backend impls.
Signed-off-by: Longpeng(Mike)
---
crypto/cipher-builtin.c | 101 ++--
1 file changed, 55 insertions(+), 46 deletions(-)
diff --git a/crypto/cipher-builtin.c b/crypt
Extracts qcrypto_cipher_ctx_new() from qcrypto_cipher_new() for
gcrypt-backend impls.
Signed-off-by: Longpeng(Mike)
---
crypto/cipher-gcrypt.c | 50 +-
1 file changed, 33 insertions(+), 17 deletions(-)
diff --git a/crypto/cipher-gcrypt.c b/crypto/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Subject: [Qemu-devel] [PATCH 0/7] Openrisc misc features / fixes
Message-id: cover.1492384862.git.sho...@gmail.com
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log --
Previously serialization did not persist the tlb, timer, pic and other
key state items. This meant snapshotting and restoring a running os
would crash. After adding these I am able to take snapshots of a
running linux os and restore at a later time.
I am currently not trying to maintain capatibil
In openRISC we are implementing the shadow registers as a 2d array.
Using this target long method rather than direct 32-bit alternatives is
consistent with the rest of our vm state serialization logic.
Signed-off-by: Stafford Horne
---
include/migration/cpu.h | 7 +++
1 file changed, 7 inser
For openrisc we implement tlb state as a 2d array of tlb entry structs.
This is added to allow easy storing of state of 2d arrays.
Signed-off-by: Stafford Horne
---
include/migration/vmstate.h | 15 +++
1 file changed, 15 insertions(+)
diff --git a/include/migration/vmstate.h b/incl
These are used to identify the processor in SMP system. Their
definition has been defined in verilog cores but it not yet part of the
spec but it will be soon.
The proposal for this is available:
https://openrisc.io/proposals/core-identifier-and-number-of-cores
Signed-off-by: Stafford Horne
-
When debugging in gdb you might want to inspect instructions in mapped
pages or in exception vectors like 0x800 etc. This was previously not
possible in qemu since the *get_phys_page_debug() routine only looked
into the data tlb.
Change to fall back to look into instruction tlb and plain physical
In openrisc simulators we use hooks like 'l.nop 1' to cause the
simulator to exit. Implement that for qemu too.
Reported-by: Waldemar Brodkorb
Signed-off-by: Stafford Horne
---
target/openrisc/helper.h | 1 +
target/openrisc/sys_helper.c | 17 +
target/openrisc/translate.c
Shadow registers are part of the openrisc spec along with sr[cid], as
part of the fast context switching feature. When exceptions occur,
instead of having to save registers to the stack if enabled the CID will
increment and a new set of registers will be available.
This patch only implements shad
Hello,
The first patch here I sent a few weeks ago and got go response. Sending
again.
The second was requested by the uclibc-ng maintainer as when he is testing
his builds he uses qemu and would like to have a way for the system to shut
down. This models how our other simulators shutdown, so n
This issue still exists for me in 2.9 rc4.
-Original Message-
From: Samuel Thibault [mailto:samuel.thiba...@gnu.org]
Sent: Sunday, April 16, 2017 04:10
To: FONNEMANN Mark
Cc: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] dns server not working in QEMU using usermode
networking (SLIR
On Sat, Apr 15, 2017 at 04:40:35 -0700, Richard Henderson wrote:
> On 04/11/2017 06:17 PM, Emilio G. Cota wrote:
> >This will be used by TCG targets to implement a fast path
> >for indirect branches.
> >
> >I only have implemented and tested this on an i386 host, so
> >make this opcode optional and
On Sat, Apr 15, 2017 at 01:10:02AM +0800, Paolo Bonzini wrote:
>
>
> On 14/04/2017 16:51, Stefan Hajnoczi wrote:
> > On Fri, Apr 14, 2017 at 9:02 AM, Fam Zheng wrote:
> >> @@ -398,11 +399,15 @@ void bdrv_drain_all(void);
> >> */\
> >>
Exynos4210 has four SD/MMC controllers supporting:
- SD Standard Host Specification Version 2.0,
- MMC Specification Version 4.3,
- SDIO Card Specification Version 2.0,
- DMA and ADMA.
Add emulation of SDHCI devices which allows accessing storage through SD
cards. Differences from real hardwar
According to the second suggestion listed on Dead code Removal
of BiteSizedTasks, I modify some *_exit functions to make them
return void. Some *_exit and *_exitfn functions that already
return void remain unchanged. Also, the checks for the callers
are deleted.
Signed-off-by:
In the first patch, we add tcp options support to optimize compare performance.
and another patch simplified code and adjust trace print format.
Zhang Chen (2):
COLO-compare: Optimize tcp compare for option field
COLO-compare: Optimize tcp compare trace event
net/colo-compare.c | 54
In this patch we support packet that have tcp options field.
Add tcp options field check, If the packet have options
field we just skip it and compare tcp payload,
Avoid unnecessary checkpoint, optimize performance.
Signed-off-by: Zhang Chen
---
net/colo-compare.c | 27 ++
Optimize two trace events as one, adjust print format make
it easy to read. rename trace_colo_compare_pkt_info_src/dst
to trace_colo_compare_tcp_info.
Signed-off-by: Zhang Chen
---
net/colo-compare.c | 29 +
net/trace-events | 3 +--
2 files changed, 18 insertions(
Hello,
I hadn't seen the original report on the list, sorry. There is too much
traffic on qemu-devel for me to manage to catch these :/
This problem was fixed by
e42f869b ("slirp: Make RA build more flexible") and
a2f80fdf ("slirp: Send RDNSS in RA only if host has an IPv6 DNS server")
which wil
This has been filed as a bug: https://bugs.launchpad.net/qemu/+bug/1683084.
Mark.
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