On 02/22/2017 12:20 AM, Eric Blake wrote:
On 02/21/2017 08:07 AM, Markus Armbruster wrote:
Zhang Chen writes:
On 02/21/2017 07:15 PM, Markus Armbruster wrote:
Zhang Chen writes:
We can call this qmp command to do checkpoint outside of qemu.
Xen colo will need this function.
I know noth
on 2017/2/22 2:44, Alex Williamson wrote:
On Tue, 21 Feb 2017 18:09:04 +
Peter Maydell wrote:
On 21 February 2017 at 16:34, Paolo Bonzini wrote:
On 21/02/2017 17:21, Alex Williamson wrote:
On Tue, 21 Feb 2017 14:46:55 +0800
Yongji Xie wrote:
At the moment ram device's memory regi
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Subject: [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222
Message-id: 20170222063348.32176-1-da...@gibson.dropbear.id.au
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(
From: Igor Mammedov
Generic helper machine_query_hotpluggable_cpus() replaced
target specific query_hotpluggable_cpus() callbacks so
there is no need in it anymore. However inon NULL callback
value is used to detect/report hotpluggable cpus support,
therefore it can be removed completely.
Replace
On Thu, Feb 16, 2017 at 02:47:26PM +0100, Cédric Le Goater wrote:
> A list of ICS objects was introduced under the XICS object for the
> PowerNV machine, but, for the sPAPR machine, it brings extra complexity
> as there is only a single ICS. To simplify the code, let's add the ICS
> pointer under t
From: Suraj Jitindar Singh
The DPFD field in the LPCR is 3 bits wide. This has always been defined
as 0x3 << shift which indicates a 2 bit field, which is incorrect.
Correct this.
Signed-off-by: Suraj Jitindar Singh
Signed-off-by: David Gibson
---
target/ppc/cpu.h | 2 +-
1 file changed, 1 in
From: Igor Mammedov
Replace SPAPR specific cores[] array with generic
machine->possible_cpus and store core objects there.
It makes cores bookkeeping similar to x86 cpus and
will allow to unify similar code.
It would allow to replace cpu_index based NUMA node
mapping with iproperty based one (for
From: Thomas Huth
On POWER, the valid page sizes that the guest can use are bound
to the CPU and not to the memory region. QEMU already has some
fancy logic to find out the right maximum memory size to tell
it to the guest during boot (see getrampagesize() in the file
target/ppc/kvm.c for more in
From: Igor Mammedov
so that it would be possible to reuse it with
spapr/virt-aarch64 targets.
Signed-off-by: Igor Mammedov
Signed-off-by: David Gibson
---
hw/i386/pc.c | 57 ++--
include/hw/boards.h | 1 +
include/hw/i386/pc.h | 1 -
From: Sam Bobroff
The spapr-vlan device in QEMU has always presented it's MAC address in
the device tree as an 8 byte value, even though PAPR requires it to be
6 bytes. This is because, at the time, AIX required the value to be 8
bytes. However, modern versions of AIX support the (correct) 6
by
From: Igor Mammedov
All callbacks FOO_query_hotpluggable_cpus() are practically
the same except of setting vcpus_count to different values.
Convert them to a generic machine_query_hotpluggable_cpus()
callback by moving vcpus_count initialization to per machine
specific callback possible_cpu_arch_
From: Igor Mammedov
so it could be reused for SPAPR cores as well
Signed-off-by: Igor Mammedov
Signed-off-by: David Gibson
---
hw/acpi/cpu.c | 2 +-
hw/i386/pc.c| 8
include/hw/boards.h | 2 +-
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/acpi/cpu.c
From: Suraj Jitindar Singh
POWER9 processors implement the mmu as defined in version 3.00 of the ISA.
Add a definition for this mmu model and set the POWER9 cpu model to use
this mmu model.
Signed-off-by: Suraj Jitindar Singh
Signed-off-by: David Gibson
---
target/ppc/cpu-qom.h| 5 ++
From: Alex Zuepke
The Book-E TLB matching process should bail out early when a TLB
entry matches, but the access permissions are wrong. The CPU
will then raise a DSI error instead of a Data TLB error, as
described for TLB matching in Freescale and IBM documents.
Signed-off-by: Alex Zuepke
Signe
From: Thomas Huth
hw_error() is for CPU related errors only (it prints out a
register dump and calls abort()), so we should not use it
if we just failed to load the bios image. Apart from that,
realize() functions should not exit directly but always set
the errp with error_setg() in case of error
From: Suraj Jitindar Singh
The logical partitioning control register controls a threads operation
based on the partition it is currently executing. Add new definitions and
update the mask used when writing to the LPCR based on the POWER9 spec.
Signed-off-by: Suraj Jitindar Singh
Signed-off-by:
From: Bharata B Rao
xsaddqpo: VSX Scalar Add Quad-Precision using round to Odd
xsmulqo: VSX Scalar Multiply Quad-Precision using round to Odd
xsdivqpo: VSX Scalar Divide Quad-Precision using round to Odd
xscvqpdpo: VSX Scalar round & Convert Quad-Precision format to
Double-Precisio
From: Igor Mammedov
Signed-off-by: Igor Mammedov
Signed-off-by: David Gibson
---
hw/i386/pc.c | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 50ba977..3475174 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1789,12 +1789,1
From: Laurent Vivier
Signed-off-by: Laurent Vivier
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: David Gibson
---
hw/ppc/mac_newworld.c | 15 +++
hw/ppc/trace-events | 4
2 files changed, 7 insertions(+), 12 deletions(-)
diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/ma
From: Igor Mammedov
Fill in CpuInstanceProperties once at board init time and
just copy them whenever query_hotpluggable_cpus() is called.
It will keep topology info always available without need
to recalculate it every time it's needed.
Considering it has NUMA node id, it will be used to keep
NU
From: Suraj Jitindar Singh
The vpm0 bit was removed from the LPCR in POWER9, this bit controlled
whether ISI and DSI interrupts were directed to the hypervisor or the
partition. These interrupts now go to the hypervisor irrespective, thus
it is no longer necessary to check the vmp0 bit in the LPC
From: Bharata B Rao
Implement float128_to_uint64() and use that to implement
float128_to_uint64_round_to_zero()
This is required by xscvqpudz instruction of PowerPC ISA 3.0.
Signed-off-by: Bharata B Rao
Reviewed-by: Peter Maydell
Signed-off-by: David Gibson
---
fpu/softfloat.c | 59
From: Peter Maydell
When performing clock calculations, the ppc405_uc code
has several places where it multiplies together two
32-bit variables and assigns the result to a 64-bit
variable. This doesn't quite do what is intended because
C will compute a 32-bit multiply result. Add casts to
ensure
From: Laurent Vivier
Signed-off-by: Laurent Vivier
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: David Gibson
---
hw/ppc/ppc4xx_pci.c | 13 +++--
hw/ppc/trace-events | 4
2 files changed, 7 insertions(+), 10 deletions(-)
diff --git a/hw/ppc/ppc4xx_pci.c b/hw/ppc/ppc4xx_pci
From: Nikunj A Dadhania
slbieg: SLB Invalidate Entry Global
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target/ppc/helper.h | 1 +
target/ppc/mmu-hash64.c | 16 ++--
target/ppc/translate.c | 14 ++
3 files changed, 29 insertions(+), 2 deletio
From: Bharata B Rao
xscvqpudz: VSX Scalar truncate & Convert Quad-Precision format to
Unsigned Doubleword format
xscvqpuwz: VSX Scalar truncate & Convert Quad-Precision format to
Unsigned Word format
Signed-off-by: Bharata B Rao
Signed-off-by: David Gibson
---
target/ppc
From: Igor Mammedov
possible_cpus could be initialized earlier then cpu objects,
i.e. when -smp is parsed so move init code to possible_cpu_arch_ids()
interface func and do initialization on the first call.
it should help later with making -numa cpu/-smp parsing a machine state
properties.
Sign
From: Bharata B Rao
Power ISA 3.0 introduces a few quadruple precision floating point
instructions that support round-to-odd rounding mode. The
round-to-odd mode is explained as under:
Let Z be the intermediate arithmetic result or the operand of a convert
operation. If Z can be represented exac
From: Jose Ricardo Ziviani
xsrqpi[x]: VSX Scalar Round to Quad-Precision Integer
[with Inexact].
Signed-off-by: Jose Ricardo Ziviani
Signed-off-by: David Gibson
---
target/ppc/fpu_helper.c | 59 +
target/ppc/helper.h | 1 +
targ
From: Laurent Vivier
Signed-off-by: Laurent Vivier
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: David Gibson
---
hw/ppc/spapr_ovec.c | 17 +++--
hw/ppc/trace-events | 4
2 files changed, 7 insertions(+), 14 deletions(-)
diff --git a/hw/ppc/spapr_ovec.c b/hw/ppc/spapr_
From: Bharata B Rao
xsmaxjdp: VSX Scalar Maximum Type-J Double-Precision
xsminjdp: VSX Scalar Minimum Type-J Double-Precision
Signed-off-by: Bharata B Rao
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target/ppc/fpu_helper.c | 55 +++
From: Bharata B Rao
float128_to_uint32_round_to_zero() is needed by xscvqpuwz instruction
of PowerPC ISA 3.0.
Signed-off-by: Bharata B Rao
Reviewed-by: Peter Maydell
Signed-off-by: David Gibson
---
fpu/softfloat.c | 28
include/fpu/softfloat.h | 1 +
2 f
From: Bharata B Rao
xsmaxcdp: VSX Scalar Maximum Type-C Double-Precision
xsmincdp: VSX Scalar Minimum Type-C Double-Precision
Signed-off-by: Bharata B Rao
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target/ppc/fpu_helper.c | 38 +++
From: Balamuruhan S
stwat: Store Word Atomic
stdat: Store Doubleword Atomic
The instruction includes as function code (5 bits) which gives a detail
on the operation to be performed. The patch implements five such
functions.
Signed-off-by: Balamuruhan S
Signed-off-by: Harish S
Signed-off-by: A
From: Balamuruhan S
lwat: Load Word Atomic
ldat: Load Doubleword Atomic
The instruction includes as function code (5 bits) which gives a detail
on the operation to be performed. The patch implements five such
functions.
Signed-off-by: Balamuruhan S
Signed-off-by: Harish S
Signed-off-by: Athir
From: Nikunj A Dadhania
Use the available wait instruction implementation.
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target/ppc/translate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index b1a6aee..3ba2616 100644
From: Nikunj A Dadhania
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target/ppc/translate.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 255735a..80f9f15 100644
--- a/target/ppc/translate.c
+++ b/
From: Jose Ricardo Ziviani
xssqrtqp: VSX Scalar Square Root Quad-Precision.
Signed-off-by: Jose Ricardo Ziviani
Signed-off-by: David Gibson
---
target/ppc/fpu_helper.c | 38 +
target/ppc/helper.h | 1 +
target/ppc/translate/vsx-
From: Thomas Huth
error_report() already puts a prefix with the program name in front
of the error strings, so the "qemu:" prefix is not necessary here
anymore.
Reported-by: Markus Armbruster
Signed-off-by: Thomas Huth
Signed-off-by: David Gibson
---
hw/ppc/pnv.c | 6 +++---
1 file changed,
From: Igor Mammedov
spapr_core_pre_plug/spapr_core_plug/spapr_core_unplug() are managing
wiring CPU core into spapr machine state and not internal CPU core state.
So move them from spapr_cpu_core.c to spapr.c where other similar
(spapr_memory_[foo]plug()) callbacks are located, which also matches
From: Sam Bobroff
The last byte of the option vector was missing due to an off-by-one
error. Without this fix, client architecture support negotiation will
fail because the last byte of option vector 5, which contains the MMU
support, will be missed.
Signed-off-by: Sam Bobroff
Reviewed-by: Thom
On Thu, Feb 16, 2017 at 02:47:25PM +0100, Cédric Le Goater wrote:
> Today, the ICP (Interrupt Controller Presenter) objects are created by
> the 'nr_servers' property handler of the XICS object and a class
> handler. They are realized in the XICS object realize routine.
>
> Let's simplify the proc
From: Jose Ricardo Ziviani
xsrqpxp: VSX Scalar Round Quad-Precision to Double-Extended Precision.
Signed-off-by: Jose Ricardo Ziviani
Signed-off-by: David Gibson
---
target/ppc/fpu_helper.c | 56 +
target/ppc/helper.h | 1 +
tar
From: Jose Ricardo Ziviani
xssubqp: VSX Scalar Subtract Quad-Precision.
Signed-off-by: Jose Ricardo Ziviani
Signed-off-by: David Gibson
---
target/ppc/fpu_helper.c | 34 ++
target/ppc/helper.h | 1 +
target/ppc/translate/vsx-impl.in
The following changes since commit 796b288f7be875045670f963ce1b3c8e96ac:
Merge remote-tracking branch 'remotes/cody/tags/block-pull-request' into
staging (2017-02-21 15:48:22 +)
are available in the git repository at:
git://github.com/dgibson/qemu.git tags/ppc-for-2.9-20170222
for
From: Sam Bobroff
Programs run under qemu-ppc64 on an x86_64 host currently segfault
if they use pthread_create() due to the adjustment made to the NIP in
commit bd6fefe71cec5a0c7d2be4ac96307f25db56abf9.
This patch changes cpu_loop() to set the NIP back to the
pre-incremented value before callin
From: Igor Mammedov
spapr_core_unplug() were essentially spapr_core_unplug_request()
handler that requested CPU removal and registered callback
which did actual cpu core removali but it was called from
spapr_machine_device_unplug() which is intended for actual object
removal. Commit (cf632463 spa
From: Igor Mammedov
Split off destroying VCPU threads from drc callback
spapr_core_release() into new spapr_cpu_core_unrealizefn()
which takes care of internal cpu core state cleanup (i.e.
VCPU threads) and is called when object_unparent(core)
is called.
That leaves spapr_core_release() only wit
From: Nikunj A Dadhania
slbsync: SLB Synchoronize
The instruction provides an ordering function for the effects of all
slbieg instructions executed by the thread executing the slbsync
instruction.
Signed-off-by: Nikunj A Dadhania
Signed-off-by: David Gibson
---
target/ppc/translate.c | 12 ++
I know this has been committed already, but here goes anyway:
Marek Vasut writes:
> From: Chris Wulff
>
> Add the Altera Nios2 internal interrupt controller model.
>
> Signed-off-by: Marek Vasut
> Cc: Chris Wulff
> Cc: Jeff Da Silva
> Cc: Ley Foon Tan
> Cc: Sandra Loosemore
> Cc: Yves Vand
On 02/22/2017 12:07 AM, Alex Williamson wrote:
> On Tue, 21 Feb 2017 18:21:53 +0800
> Cao jin wrote:
>
>> Hi,
>>
>> First, sorry for such a long time delay on the AER job. I was on 12 days
>> holiday, and start to work on the patch 2 weeks ago, because I use a
>> newer version kernel(4.10 rc8)
Ping?
Le 18/11/2016 à 23:43, Hervé Poussineau a écrit :
This simplifies the code a lot, and this fixes big memory leaks
introduced in a3d586f704609a45b6037534cb2f34da5dfd8895
Windows NT is now able to boot without using gigabytes of ram on the host.
Signed-off-by: Hervé Poussineau
---
hw/dma
Intel vIOMMU devices are created with "-device" parameter, while here
actually we need to make sure this device will be created before some
other PCI devices (like vfio-pci devices) so that we know iommu_fn will
be setup correctly before realizations of those PCI devices.
Here we do explicit check
I thought it might help to explain some more of the background to Yong
Ji's recent patch "memory: make ram device read/write endian
sensitive". I don't know whether that patch touches the right code or
not, but with a bit more background, maybe somebody can tell us what
code does need to be fixed.
We use g_queue_init() to init s->conn_list, so we should use g_queue_clear()
to instead of g_queue_free().
Signed-off-by: Zhang Chen
Reviewed-by: zhanghailiang
---
net/colo-compare.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/net/colo-compare.c b/net/colo-compare.c
inde
On 02/22/2017 11:15 AM, Jason Wang wrote:
On 2017年02月22日 11:09, Jason Wang wrote:
On 2017年02月22日 09:47, Hailiang Zhang wrote:
On 2017/2/21 10:44, Zhang Chen wrote:
We use g_queue_init() to init s->conn_list, so we should use
g_queue_clear()
to instead of g_queue_free().
Signed-off-by:
On Thu, Feb 16, 2017 at 02:47:23PM +0100, Cédric Le Goater wrote:
> Hello,
>
> The goal behind this series is to simplify the XICS interface by
> moving back in the machine the way the ICS and ICP objects interact
> together. It's up to the machine to implement this "fabric" logic by
> providing a
On Wed, 22 Feb 2017 11:08:51 +0800
Peter Xu wrote:
> [cc Jintack]
>
> On Tue, Feb 21, 2017 at 02:43:03PM -0700, Alex Williamson wrote:
> > Since commit 4bb571d857d9 ("pci/pcie: don't assume cap id 0 is
> > reserved") removes the internal use of extended capability ID 0, the
> > comment here beco
On Tue, Feb 21, 2017 at 08:54:31PM -0700, Alex Williamson wrote:
[...]
> I prefer the existing code. I don't really see why you consider it a
> hack. I think it's pretty elegant that we can ignore the header
> through the course of iterating through the capabilities, that we drop
> other masked
Richard Henderson writes:
> On 02/21/2017 08:26 PM, Nikunj A Dadhania wrote:
>> Richard Henderson writes:
>>
>>> On 02/20/2017 09:11 PM, Nikunj A Dadhania wrote:
For 64-bit mode if the register RA contains 0x8000___, OV
and OV32 are set to 1.
For 32-bit mode if th
9:24:35 host-12 chronyd[1157]: Disabled command socket
/var/run/chrony/chronyd.sock
Feb 22 09:24:35 host-12 chronyd[1157]: Frequency -3.470 +/- 0.756 ppm read from
/var/lib/chrony/drift
Feb 22 09:24:35 host-12 smartd[1137]: smartd 6.2 2013-07-26 r3841
[x86_64-linux-4.10.0-linux-next-3d4ffb9-next-2
After a net connection is closed, we didn't clear its releated resources
in connection_track_table, which will lead to memory leak.
Let't track the state of net connection, if it is closed, its related
resources will be cleared up.
Signed-off-by: zhanghailiang
---
net/colo.h| 4 +++
Hi,
This series tries to integrate colo frame with block replication
and net compare. Block replcation and colo proxy (net compare) parts
have been merged in upstream for last version. We need to integrate
all of them to realize complete capability of COLO.
Besides, for colo frame, there are some
Hi,
Patch 1 fixes a double free bug, and patch 2 fixes a memory leak bug.
Patch 3 is an optimization for filter-rewriter.
Please review, thanks.
zhanghailiang (3):
net/colo: fix memory double free error
filter-rewriter: fix memory leak for connection in
connection_track_table
filter-re
While the offset of packets's sequence for primary side and
secondary side is zero, it is unnecessary to call net_checksum_calculate()
to recalculate the checksume value of packets.
Signed-off-by: zhanghailiang
---
net/filter-rewriter.c | 18 +++---
1 file changed, 11 insertions(+),
The 'primary_list' and 'secondary_list' members of struct Connection
is not allocated through dynamically g_queue_new(), but we free it by using
g_queue_free(), which will lead to a double-free bug.
Signed-off-by: zhanghailiang
---
net/colo.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletion
There are several stages during loadvm/savevm process. In different stage,
migration incoming processes different types of sections.
We want to control these stages more accuracy, it will benefit COLO
performance, we don't have to save type of QEMU_VM_SECTION_START
sections everytime while do check
We separate the process of saving/loading ram and device state when do
checkpoint. We add new helpers for save/load ram/device. With this change,
we can directly transfer RAM from primary side to secondary side without
using channel-buffer as assistant, which also reduce the size of extra memory
wa
If some errors happen during VM's COLO FT stage, it's important to
notify the users of this event. Together with 'x_colo_lost_heartbeat',
Users can intervene in COLO's failover work immediately.
If users don't want to get involved in COLO's failover verdict,
it is still necessary to notify users th
While do checkpoint, we need to flush all the unhandled packets,
By using the filter notifier mechanism, we can easily to notify
every compare object to do this process, which runs inside
of compare threads as a coroutine.
Cc: Jason Wang
Signed-off-by: zhanghailiang
Signed-off-by: Zhang Chen
--
Don't need to flush all VM's ram from cache, only
flush the dirty pages since last checkpoint
Cc: Juan Quintela
Signed-off-by: Li Zhijian
Signed-off-by: Zhang Chen
Signed-off-by: zhanghailiang
---
migration/ram.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/migration/ram.c
It is unnecessary to call qemu_savevm_state_begin() in every checkpoint process.
It mainly sets up devices and does the first device state pass. These data will
not change during the later checkpoint process. So, we split it out of
colo_do_checkpoint_transaction(), in this way, we can reduce these
It's a good idea to use notifier to notify COLO frame of
inconsistent packets comparing.
Cc: Jason Wang
Signed-off-by: Zhang Chen
Signed-off-by: zhanghailiang
---
net/colo-compare.c | 32
net/colo-compare.h | 2 ++
2 files changed, 30 insertions(+), 4 deletion
COLO's checkpoint process is based on migration process,
everytime we do checkpoint we will repeat the process of savevm and loadvm.
So we will call qemu_loadvm_section_start_full() repeatedly, It will
add all migration sections information into loadvm_handlers list everytime,
which will lead to m
If VM is in COLO FT state, we need to do some extra works before
starting normal shutdown process.
Secondary VM will ignore the shutdown command if users issue it directly
to Secondary VM. COLO will capture shutdown command and after
shutdown request from user.
Cc: Paolo Bonzini
Signed-off-by: z
Make sure master start block replication after slave's block
replication started.
Signed-off-by: zhanghailiang
Signed-off-by: Wen Congyang
Signed-off-by: Li Zhijian
Cc: Stefan Hajnoczi
Cc: Kevin Wolf
Cc: Max Reitz
Cc: Changlong Xie
---
migration/colo.c | 56
We should not load PVM's state directly into SVM, because there maybe some
errors happen when SVM is receving data, which will break SVM.
We need to ensure receving all data before load the state into SVM. We use
an extra memory to cache these data (PVM's ram). The ram cache in secondary side
is i
For COLO FT, both the PVM and SVM run at the same time,
only sync the state while it needs.
So here, let SVM runs while not doing checkpoint,
Besides, change DEFAULT_MIGRATE_X_CHECKPOINT_DELAY to 200*100.
Cc: Jason Wang
Signed-off-by: zhanghailiang
---
migration/colo.c | 25 ++
We record the address of the dirty pages that received,
it will help flushing pages that cached into SVM.
We record them by re-using migration dirty bitmap.
Cc: Juan Quintela
Signed-off-by: zhanghailiang
Reviewed-by: Dr. David Alan Gilbert
---
migration/ram.c | 30 +
During the time of VM's running, PVM may dirty some pages, we will transfer
PVM's dirty pages to SVM and store them into SVM's RAM cache at next checkpoint
time. So, the content of SVM's RAM cache will always be same with PVM's memory
after checkpoint.
Instead of flushing all content of PVM's RAM
We will use this notifier to help COLO to notify filter object
to do something, like do checkpoint, or process failover event.
Cc: Jason Wang
Signed-off-by: zhanghailiang
---
net/colo.c | 92 ++
net/colo.h | 18
2 files ch
On Thu, Feb 16, 2017 at 02:47:24PM +0100, Cédric Le Goater wrote:
> Today, the ICS (Interrupt Controller Source) object is created and
> realized by the init and realize routines of the XICS object, but some
> of the parameters are only known at the machine level.
>
> These parameters are passed f
On 2017年02月22日 11:09, Jason Wang wrote:
On 2017年02月22日 09:47, Hailiang Zhang wrote:
On 2017/2/21 10:44, Zhang Chen wrote:
We use g_queue_init() to init s->conn_list, so we should use
g_queue_clear()
to instead of g_queue_free().
Signed-off-by: Zhang Chen
Reviewed-by: zhanghailiang
On Tue, Feb 21, 2017 at 10:15:46AM +0530, Nikunj A Dadhania wrote:
> Richard Henderson writes:
>
> > On 02/20/2017 09:11 PM, Nikunj A Dadhania wrote:
> >> +#ifndef TARGET_PPC64
> >> static inline target_ulong cpu_read_xer(CPUPPCState *env)
> >> {
> >> return env->xer | (env->so << XER_SO)
[cc Jintack]
On Tue, Feb 21, 2017 at 02:43:03PM -0700, Alex Williamson wrote:
> Since commit 4bb571d857d9 ("pci/pcie: don't assume cap id 0 is
> reserved") removes the internal use of extended capability ID 0, the
> comment here becomes invalid. However, peeling back the onion, the
> code is stil
On 2017年02月22日 09:47, Hailiang Zhang wrote:
On 2017/2/21 10:44, Zhang Chen wrote:
We use g_queue_init() to init s->conn_list, so we should use
g_queue_clear()
to instead of g_queue_free().
Signed-off-by: Zhang Chen
Reviewed-by: zhanghailiang
Applied, thanks.
---
net/colo-compare.c
On 02/19/2017 10:38 PM, Han, Huaitong wrote:
Hi, Gaohuai
I tried to debug the problem, and I found the indirect cause may be that
the rmap value is not cleared when KVM mmu page is freed. I have read
code without the root cause. Can you stable reproduce the the issue?
Many guesses need to be ver
* Cornelia Huck [2017-02-21 16:43:07 +0100]:
> On Tue, 21 Feb 2017 15:36:23 +0800
> Dong Jia Shi wrote:
>
> > * Cornelia Huck [2017-02-20 19:31:13 +0100]:
> >
> > > On Fri, 17 Feb 2017 09:29:28 +0100
> > > Dong Jia Shi wrote:
> > >
> > > > To make vfio support subchannel devices, we need a
Python is no longer installed implicitly, but the QEMU build system
requires it. List it in PACKAGES.
Reported-by: Auger Eric
Signed-off-by: Fam Zheng
---
tests/docker/dockerfiles/fedora.docker | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/docker/dockerfiles/fedora.d
On 2017/2/21 10:44, Zhang Chen wrote:
We use g_queue_init() to init s->conn_list, so we should use g_queue_clear()
to instead of g_queue_free().
Signed-off-by: Zhang Chen
Reviewed-by: zhanghailiang
---
net/colo-compare.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On Tue, Feb 21, 2017 at 11:14:53PM +0100, Gerd Hoffmann wrote:
> This switches over ppc to use the new ppc_graphic_* defines.
>
> Signed-off-by: Gerd Hoffmann
Reviewed-by: David Gibson
Of course, the idea of a per-arch, rather than per-machine, default
graphics size is nuts, but this change do
On Tue, Feb 21, 2017 at 01:33:41PM +, Peter Maydell wrote:
> When performing clock calculations, the ppc405_uc code
> has several places where it multiplies together two
> 32-bit variables and assigns the result to a 64-bit
> variable. This doesn't quite do what is intended because
> C will com
On 02/21/17 23:14, Gerd Hoffmann wrote:
> Bring documentation in line with the recent changes.
> Text suggested by László Érsek.
>
> Signed-off-by: Gerd Hoffmann
> ---
> qemu-options.hx | 13 -
> 1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/qemu-options.hx b/qemu
From: Paul Burton
Introduce support for emulating the MIPS Boston development board. The
Boston board is built around an FPGA & 3 PCIe controllers, one of which
is connected to an Intel EG20T Platform Controller Hub. It is used
during the development & debug of new CPUs and the software intended
From: Paul Burton
Provide a new function mips_gictimer_get_freq() which returns the
frequency at which a GIC timer will count. This will be useful for
boards which perform setup based upon this frequency.
Signed-off-by: Paul Burton
Reviewed-by: Leon Alrae
Reviewed-by: Philippe Mathieu-Daudé
S
Hi,
This is the v2 of the pull-req for target-mips.
The warning treated as error has been fixed and the file is now isolated for
mips64el only.
Boston has further update to have default -drive to if=ide.
Regards,
Yongbok
The following changes since commit 796b288f7be875045670f963ce1b3c8e96
From: Paul Burton
Provide a new cpu_supports_isa function which allows callers to
determine whether a CPU supports one of the ISA_ flags, by testing
whether the associated struct mips_def_t sets the ISA flags in its
insn_flags field.
An example use of this is to allow boards which generate bootl
From: Paul Burton
Add support for emulating the Xilinx AXI Root Port Bridge for PCI
Express as described by Xilinx' PG055 document. This is a PCIe
controller that can be used with certain series of Xilinx FPGAs, and is
used on the MIPS Boston board which will make use of this code.
Signed-off-by
From: Paul Burton
Introduce support for loading Flattened Image Trees, as used by modern
U-Boot. FIT images are essentially flattened device tree files which
contain binary images such as kernels, FDTs or ramdisks along with one
or more configuration nodes describing boot configurations.
The MIP
From: Paul Burton
Support moving the GCR base address & updating the CPU's CP0 CMGCRBase
register appropriately. This is required if a platform needs to move its
GCRs away from other memory, as the MIPS Boston development board does
to avoid its flash memory.
Signed-off-by: Paul Burton
Reviewed
1 - 100 of 544 matches
Mail list logo
