On 30/09/2016 03:27, David Gibson wrote:
> On Thu, Sep 29, 2016 at 07:15:05PM +0200, Laurent Vivier wrote:
>> Signed-off-by: Laurent Vivier
>
> This could do with a commit message, even if it's just to say that
> this is supposed to be a refactor without behavioural change.
OK
>
>> ---
>> t
+-- On Fri, 30 Sep 2016, Jason Wang wrote --+
| Thanks but there're still several other places that needs to be fixed were
| reported by robot.
|
| Please fix them too.
Done. Sent a revised patch v2.
Thank you.
--
Prasad J Pandit / Red Hat Product Security Team
47AF CE69 3A90 54AA 9045 1053 D
From: Prasad J Pandit
Fix indentations and source format at few places. Add braces
around 'if' and 'while' statements.
Signed-off-by: Prasad J Pandit
---
hw/net/pcnet.c | 130 +
1 file changed, 67 insertions(+), 63 deletions(-)
Update pe
On 2016/9/30 13:53, Amit Shah wrote:
On (Thu) 29 Sep 2016 [16:46:20], zhanghailiang wrote:
This is the 20th version of COLO frame series.
COLO Block replication and proxy (COLO compare) series are both been
merged into upstream already. And further works can be done now to
realize the full COLO
Hi,
On (Thu) 29 Sep 2016 [19:06:32], Li Zhijian wrote:
> Priviously, if the source and distination have different devices, source
> could goto
> the status "paused (postmigrate)", and the distination will exit that means
> no qemu
> is alive.
>
> After this patch, at above case, source can dect
On 09/29/2016 10:35 PM, Markus Armbruster wrote:
Cao jin writes:
@@ -2349,7 +2342,7 @@ static void megasas_scsi_realize(PCIDevice *dev, Error
**errp)
memory_region_init_io(&s->mmio_io, OBJECT(s), &megasas_mmio_ops, s,
"megasas-mmio", 0x4000);
-if (m
Currently the CPU does not get reset when the system_reset command is
invoked. We register a handler in the pxa2xx SoC code, to reset the
CPU as well.
Signed-off-by: Vijay Kumar B.
Reviewed-by: Deepak S.
---
hw/arm/pxa2xx.c | 8
1 file changed, 8 insertions(+)
diff --git a/hw/arm/pxa2
On (Thu) 29 Sep 2016 [16:46:20], zhanghailiang wrote:
> This is the 20th version of COLO frame series.
>
> COLO Block replication and proxy (COLO compare) series are both been
> merged into upstream already. And further works can be done now to
> realize the full COLO feature.
>
> Athough there a
On (Mon) 26 Sep 2016 [22:55:01], Chunguang Li wrote:
>
>
>
> > -原始邮件-
> > 发件人: "Dr. David Alan Gilbert"
> > 发送时间: 2016年9月26日 星期一
> > 收件人: "Chunguang Li"
> > 抄送: qemu-devel@nongnu.org, amit.s...@redhat.com, pbonz...@redhat.com,
> > stefa...@redhat.com, quint...@redhat.com
> > 主题: Re: [
On 09/29/2016 10:17 PM, Markus Armbruster wrote:
Cao jin writes:
-/* Initialize the MSI-X structures */
+/* Make PCI device @dev MSI-X capable
+ * @nentries is the max number of MSI-X vectors that the device support.
+ * @table_bar is the MemoryRegion that MSI-X table structure resides.
+
On Thu, Sep 29, 2016 at 01:23:29PM +0200, Radim Krčmář wrote:
[...]
> @@ -2481,11 +2482,14 @@ static void vtd_realize(DeviceState *dev, Error
> **errp)
> if (s->intr_eim == ON_OFF_AUTO_AUTO && !x86_iommu->intr_supported) {
> s->intr_eim = ON_OFF_AUTO_OFF;
> }
> +if (s->int
Alistair Francis writes:
> On Thu, Sep 29, 2016 at 2:24 AM, Markus Armbruster wrote:
>> Alistair Francis writes:
>>
>>> Signed-off-by: Alistair Francis
>>> Reviewed-by: Peter Maydell
>>> ---
>>> V11:
>>> - Fix corrections
>>> V10:
>>> - Split the data loading and PC setting
>>> V9:
>>> - C
Hello Jason,
+-- On Fri, 30 Sep 2016, Jason Wang wrote --+
| On 2016年09月30日 02:57, P J P wrote:
| > The AMD PC-Net II emulator has set of control and status(CSR)
| > registers. Of these, CSR76 and CSR78 hold receive and transmit
| > descriptor ring length respectively. This ring length could ran
On Thu, 09/29 09:47, Paolo Bonzini wrote:
>
>
> On 29/09/2016 05:05, Fam Zheng wrote:
> > > So whether we can move a certain BB from some context to another depends
> > > on what the frontend supports, I don't think there is a generic answer
> > > we can implement here in the generic BB code. NBD
On 9/29/2016 8:12 PM, Tian, Kevin wrote:
>> From: Daniel P. Berrange [mailto:berra...@redhat.com]
>> Sent: Thursday, September 29, 2016 10:39 PM
>>
>> On Thu, Sep 29, 2016 at 02:35:48PM +, Tian, Kevin wrote:
From: Daniel P. Berrange [mailto:berra...@redhat.com]
Sent: Thursday, Septe
On Thu, Sep 29, 2016 at 01:23:27PM +0200, Radim Krčmář wrote:
> The default (auto) emulates the current behavior.
>
> Signed-off-by: Radim Krčmář
> ---
> hw/i386/intel_iommu.c | 20 +++-
> include/hw/i386/intel_iommu.h | 1 +
> 2 files changed, 20 insertions(+), 1 deleti
On Tue, Sep 20, 2016 at 8:40 PM, David Kiarie wrote:
> Hello all,
>
> This patchset mainly adds AMD IOMMU interrupt remapping logic to Qemu. Doing
> that
> I have solved an existing issue where platform devices are not able to make
> interrupt
> requests with and explicit SID.
>
> This series is
find_and_check_chardev() uses 'opts' member of CharDriverState to
check if the chardev is 'socket' chardev or not, which the opts
will be NULL if We add the chardev by qmp 'chardev-add' command.
All the related info can be found in 'filename' member of CharDriverState,
For tcp socket device, it wi
(Re-post, as my mail client somehow made my previous post attach to the wrong
thread.
I do not mean to spam y'all, but maybe my previous mail got lost in your
filters ...
... as I have not yet seen any answer to my questions/remarks.
)
> On 2016/9/14 6:55, Alex Williamson wrote:
>
> [cc +Paolo
On Thu, Sep 29, 2016 at 09:55:30AM -0700, Jianjun Duan wrote:
> ping
I'm sorry, this fell off my radar. Can you please rebase and resend
your latest version.
>
> On 06/27/2016 09:59 AM, Jianjun Duan wrote:
> > Hi all,
> >The previous patches seem to get buried deep somewhere. I am resending
On Wed, Sep 21, 2016 at 03:31:00PM +1000, David Gibson wrote:
> On Wed, Sep 21, 2016 at 10:18:00AM +0530, Bharata B Rao wrote:
> > CPU unplug doesn't work in TCG mode currently and causes frequent system
> > freeze. In addition to other potential problems, the main problem arises
> > of out the req
On 09/30/2016 10:58 AM, Jike Song wrote:
> On 09/29/2016 11:06 PM, Kirti Wankhede wrote:
>>
>>
>> On 9/29/2016 7:47 AM, Jike Song wrote:
>>> +Guangrong
>>>
>>> On 08/25/2016 11:53 AM, Kirti Wankhede wrote:
>>
>> ...
>>
+static long vfio_iommu_type1_pin_pages(void *iommu_data,
+
On 2016年09月30日 02:57, P J P wrote:
From: Prasad J Pandit
Fix indentations and source format at few places. Add braces
around few 'if' and 'while' statements.
Signed-off-by: Prasad J Pandit
Thanks but there're still several other places that needs to be fixed
were reported by robot.
Ple
On 2016年09月30日 02:57, P J P wrote:
From: Prasad J Pandit
The AMD PC-Net II emulator has set of control and status(CSR)
registers. Of these, CSR76 and CSR78 hold receive and transmit
descriptor ring length respectively. This ring length could range
from 1 to 65535. Setting ring length to zero
On 09/29/2016 11:06 PM, Kirti Wankhede wrote:
>
>
> On 9/29/2016 7:47 AM, Jike Song wrote:
>> +Guangrong
>>
>> On 08/25/2016 11:53 AM, Kirti Wankhede wrote:
>
> ...
>
>>> +static long vfio_iommu_type1_pin_pages(void *iommu_data,
>>> + unsigned long *user_pfn,
>>
On 2016年09月29日 12:55, Thomas Huth wrote:
On 29.09.2016 03:41, Jason Wang wrote:
On 2016年09月26日 18:35, Thomas Huth wrote:
On 26.09.2016 03:58, Brad Smith wrote:
Update the tap-bsd code now that OpenBSD uses tap(4).
Signed-off-by: Brad Smith
diff --git a/net/tap-bsd.c b/net/tap-bsd.c
inde
On 09/29/2016 06:58 PM, Kirti Wankhede wrote:
>
>
> On 9/29/2016 2:47 PM, Neo Jia wrote:
>> On Thu, Sep 29, 2016 at 04:55:39PM +0800, Jike Song wrote:
>>> Hi all,
>>>
>>> In order to have a clear understanding about the VFIO mdev upstreaming
>>> status, I'd like to summarize it. Please share your
Signed-off-by: Zhang Chen
---
net/filter-mirror.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/net/filter-mirror.c b/net/filter-mirror.c
index 35df374..0ee58d9 100644
--- a/net/filter-mirror.c
+++ b/net/filter-mirror.c
@@ -198,7 +198,7 @@ static void filter_mirror_setup
On Thu, 09/29 13:41, Stefan Hajnoczi wrote:
> On Tue, Sep 27, 2016 at 07:14:52PM +0800, Fam Zheng wrote:
> > We already specified BDRV_O_UNMAP when opening images in 'qemu-img
> > commit', but didn't turn on the "unmap" in the active commit job. This
> > patch fixes that so that zeroed clusters in
On Thu, 09/29 12:39, Kevin Wolf wrote:
> Am 29.09.2016 um 11:55 hat Fam Zheng geschrieben:
> > On Thu, 09/29 11:29, Kevin Wolf wrote:
> > > Am 28.09.2016 um 09:04 hat Fam Zheng geschrieben:
> > > > Handling this is similar to what is done to the L2 entry in the case of
> > > > compressed clusters.
On 22 September 2016 at 23:33, Michael Olbrich wrote:
> On Thu, Sep 22, 2016 at 05:23:17PM +0100, Peter Maydell wrote:
>> On 10 September 2016 at 16:07, Michael Olbrich
>> wrote:
>> > diff --git a/vl.c b/vl.c
>> > index ee557a1d3f8a..bbea51e0ce7d 100644
>> > --- a/vl.c
>> > +++ b/vl.c
>> > @@ -4
On Thu, 09/29 11:25, Markus Armbruster wrote:
> no-re...@ec2-52-6-146-230.compute-1.amazonaws.com writes:
>
> > Hi,
> >
> > Your series failed automatic build test. Please find the testing commands
> > and
> > their output below. If you have docker installed, you can probably
> > reproduce it
>
On 29 September 2016 at 17:42, Alistair Francis
wrote:
> On Thu, Sep 29, 2016 at 5:04 PM, Peter Maydell
> wrote:
>> On 26 September 2016 at 10:49, Alistair Francis
>> wrote:
>>> There was an error with some of the register implementation assuming
>>> there are 16 priority queues supported when
On 29 September 2016 at 17:25, Alistair Francis
wrote:
> This work is based on the original work by Li Guang with extra
> features added by Peter C and myself.
>
> The idea of this loader is to allow the user to load multiple images
> or values into QEMU at startup.
>
> Memory values can be loaded
On 22 September 2016 at 02:53, Peter Maydell wrote:
> This is clearly a bug, but your suggested change won't deal with the
> problem, which is that we're trying to set a bool so the ? 32 : 64
> construct is just wrong.
> Bug description:
> target-arm/translate-a64.c:2028:37: warning: ?: using i
On 16 September 2016 at 10:34, Thomas Hanson wrote:
> If tagged addresses are enabled, then addresses being loaded into the
> PC must be cleaned up by overwriting the tag bits with either all 0's
> or all 1's as specified in the ARM ARM spec. The decision process is
> dependent on
On Thu, Sep 29, 2016 at 07:15:05PM +0200, Laurent Vivier wrote:
> Signed-off-by: Laurent Vivier
This could do with a commit message, even if it's just to say that
this is supposed to be a refactor without behavioural change.
> ---
> tests/virtio-9p-test.c | 53
> tests/virti
On Thu, Sep 29, 2016 at 07:15:06PM +0200, Laurent Vivier wrote:
> This allows to store it and not have to rescan the list
> each time we need it.
>
> Signed-off-by: Laurent Vivier
> Reviewed-by: Greg Kurz
Reviewed-by: David Gibson
In that it looks technically correct. The whole notion of gue
On Thu, Sep 29, 2016 at 07:15:07PM +0200, Laurent Vivier wrote:
> but disable MSI-X tests on SPAPR as we can't check the result
> (the memory region used on PC is not readable on SPAPR).
>
> Signed-off-by: Laurent Vivier
> ---
> tests/Makefile.include| 3 ++-
> tests/libqos/virtio-pci.c | 2
On 16 September 2016 at 10:34, Thomas Hanson wrote:
> Certain instructions which can not directly load a tagged address value
> may trigger a corner case when the address size is 56 bits. This is
> because incrementing or offsetting from the current PC can cause an
> arithetic roll-over into the
On 16 September 2016 at 10:34, Thomas Hanson wrote:
> gen_intermediate_code_a64() transfers TBI values from TB->flags to
> DisasContext structure.
>
> disas_uncond_b_reg() calls new function gen_a64_set_pc_reg() to handle BR,
> BLR and RET instructions.
>
> gen_a64_set_pc_reg() implements all of t
On 16 September 2016 at 10:34, Thomas Hanson wrote:
This patch is mostly good; minor comments below.
> New arm_regime_tbi0() and arm_regime_tbi0() to extract the TBI values from
> the correct TCR for the current EL.
>
> New shift, mask and accessor macro definitions needed to add TBI flag bits
>
On Sep 29, 2016, at 8:39 PM, David Gibson wrote:
> On Thu, Sep 29, 2016 at 12:55:23PM -0400, Programmingkid wrote:
>>
>> On Sep 29, 2016, at 11:41 AM, Peter Maydell wrote:
>>
>>> On 28 September 2016 at 21:17, David Gibson
>>> wrote:
I think there is a way you could get both speed and ac
2016-09-30 2:40 GMT+08:00 Eduardo Habkost :
> (CCing Richard, sorry I forgot to CC you)
>
> Ping? Any objection to this fix?
>
> On Wed, Sep 28, 2016 at 01:33:15PM -0300, Eduardo Habkost wrote:
>> A regression was introduced by commit 96193c22a "target-i386:
>> Move xsave component mask to features
On Thu, Sep 29, 2016 at 4:59 PM, Peter Maydell wrote:
> On 24 September 2016 at 12:20, Alistair Francis wrote:
>> Connect the ADC devices to the STM32F205 SoC.
>>
>> Signed-off-by: Alistair Francis
>> ---
>>
>> #define FLASH_BASE_ADDRESS 0x0800
>> #define FLASH_SIZE (1024 * 1024)
>> @@ -52
On 29 September 2016 at 17:38, Peter Maydell wrote:
> On 23 September 2016 at 00:43, Eric Auger wrote:
>> From: Pavel Fedin
>>
>> The ITS control frame is in-kernel emulated while accesses to the
>> GITS_TRANSLATER are mediated through the KVM_SIGNAL_MSI ioctl (MSI
>> direct MSI injection advert
On Thu, Sep 29, 2016 at 4:54 PM, Peter Maydell wrote:
> On 24 September 2016 at 12:20, Alistair Francis wrote:
>> Signed-off-by: Alistair Francis
>> ---
>> As the migration framework is not included in user mode this needs to be a
>> new file.
>>
>> V8:
>> - Use the standard qdev_init_gpio_in()
On 23 September 2016 at 00:43, Eric Auger wrote:
> From: Pavel Fedin
>
> The ITS control frame is in-kernel emulated while accesses to the
> GITS_TRANSLATER are mediated through the KVM_SIGNAL_MSI ioctl (MSI
> direct MSI injection advertised by the CAP_SIGNAL_MSI capability)
>
> the kvm_gsi_direc
On Thu, Sep 29, 2016 at 5:04 PM, Peter Maydell wrote:
> On 26 September 2016 at 10:49, Alistair Francis
> wrote:
>> There was an error with some of the register implementation assuming
>> there are 16 priority queues supported when the IP only supports 8. This
>> patch corrects the registers to o
On 23 September 2016 at 00:43, Eric Auger wrote:
> This series introduces support for in-kernel GICv3 ITS emulation.
>
> On dt guest the functionality is complete and was tested on Cavium ThunderX
> with virtio-net-pci and vhost-net.
>
> On ACPI guest the series was tested with virtio-net-pci only
On 23 September 2016 at 00:43, Eric Auger wrote:
> From: Pavel Fedin
>
> Introduce global kvm_msi_use_devid flag plus associated
> kvm_msi_devid_required() macro. Passes the device ID,
> if needed, while building the MSI route entry. Device IDs are
> required by the ARM GICv3 ITS (IRQ remapping f
On Thu, Sep 29, 2016 at 12:55:23PM -0400, Programmingkid wrote:
>
> On Sep 29, 2016, at 11:41 AM, Peter Maydell wrote:
>
> > On 28 September 2016 at 21:17, David Gibson
> > wrote:
> >> I think there is a way you could get both speed and accuracy, but it's
> >> a huge project:
> >>
> >> You'd n
On 29 September 2016 at 17:04, Jonathan Neuschäfer
wrote:
> Signed-off-by: Jonathan Neuschäfer
>
> ---
> v2:
> - Preserve the poetic sound of "Many a flamewar", which Peter Maydell
> pointed out.
> ---
> CODING_STYLE | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/CODI
Signed-off-by: Alistair Francis
Reviewed-by: Peter Maydell
---
V11:
- Fix corrections
V10:
- Split the data loading and PC setting
V9:
- Clarify the image loading options
V8:
- Improve documentation
V6:
- Fixup documentation
V4:
- Re-write to be more comprehensive
docs/generic-loader.txt
On Thu, Sep 29, 2016 at 5:09 PM, Alistair Francis
wrote:
> On Thu, Sep 29, 2016 at 5:00 PM, Peter Maydell
> wrote:
>> On 29 September 2016 at 02:25, Markus Armbruster wrote:
>>> Patchew hiccup or a real problem?
>>
>> Looks like a hiccup to me.
>
> Same, it looks like it can't clone dtc.
>
> Th
This work is based on the original work by Li Guang with extra
features added by Peter C and myself.
The idea of this loader is to allow the user to load multiple images
or values into QEMU at startup.
Memory values can be loaded like this: -device
loader,addr=0xfd1a0104,data=0x800e,data-len
On 29 September 2016 at 13:15, John Snow wrote:
> The following changes since commit c640f2849ee8775fe1bbd7a2772610aa77816f9f:
>
> Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into
> staging (2016-09-28 23:02:56 +0100)
>
> are available in the git repository at:
>
> https:
On 23 September 2016 at 07:41, Andrew Jones wrote:
> Signed-off-by: Andrew Jones
>
> ---
>
> This will conflict with Wei's PMU property series (which is why I
> asked him to add it to that series...), but anyway, it'll be a minor
> resolution to make.
> ---
Applied to target-arm.next, thanks.
On 27 September 2016 at 05:02, Dr. David Alan Gilbert (git)
wrote:
> From: "Dr. David Alan Gilbert"
>
> Two more register_savevm users converted to vmstate.
> This is split out from an earlier series where some of the others
> have gone in.
>
> Note I've not been able to test the changes (other t
On Thu, Sep 29, 2016 at 2:24 AM, Markus Armbruster wrote:
> Alistair Francis writes:
>
>> Signed-off-by: Alistair Francis
>> Reviewed-by: Peter Maydell
>> ---
>> V11:
>> - Fix corrections
>> V10:
>> - Split the data loading and PC setting
>> V9:
>> - Clarify the image loading options
>> V8:
Add a generic loader to QEMU which can be used to load images or set
memory values.
Internally inside QEMU this is a device. It is a strange device that
provides no hardware interface but allows QEMU to monkey patch memory
specified when it is created. To be able to do this it has a reset
callback
On 29 September 2016 at 17:09, Alistair Francis
wrote:
> On Thu, Sep 29, 2016 at 5:00 PM, Peter Maydell
> wrote:
>> On 29 September 2016 at 02:25, Markus Armbruster wrote:
>>> Patchew hiccup or a real problem?
>>
>> Looks like a hiccup to me.
>
> Same, it looks like it can't clone dtc
I think
On Thu, Sep 29, 2016 at 2:32 AM, Markus Armbruster wrote:
> Alistair Francis writes:
>
>> Add a generic loader to QEMU which can be used to load images or set
>> memory values.
>>
>> Internally inside QEMU this is a device. It is a strange device that
>> provides no hardware interface but allows
On 25 September 2016 at 13:35, Jakub Jermář wrote:
>
> Initialization of a class instance cannot depend on its own properties
> as these are not yet set. Move parts of integratorcm_init() that depend
> on the "memsz" property to the newly added integratorcm_realize().
>
> This fixes: https://bugs
On Thu, Sep 29, 2016 at 5:00 PM, Peter Maydell wrote:
> On 29 September 2016 at 02:25, Markus Armbruster wrote:
>> Patchew hiccup or a real problem?
>
> Looks like a hiccup to me.
Same, it looks like it can't clone dtc.
Thanks,
Alistair
>
> Can you let me know if you're happy with the new com
On 26 September 2016 at 10:49, Alistair Francis
wrote:
> There was an error with some of the register implementation assuming
> there are 16 priority queues supported when the IP only supports 8. This
> patch corrects the registers to only support 8 queues.
>
> Signed-off-by: Alistair Francis
> R
Signed-off-by: Jonathan Neuschäfer
---
v2:
- Preserve the poetic sound of "Many a flamewar", which Peter Maydell
pointed out.
---
CODING_STYLE | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/CODING_STYLE b/CODING_STYLE
index e7fde15..f53180b 100644
--- a/CODING_STYLE
+++ b/
On 28 September 2016 at 04:43, Vijay Kumar B wrote:
> Resending, since I missed qemu-devel in the previous submission. Sorry
> about that.
>
> This patch series fixes the key mappings for the mainstone board. The
> incorrect mappings renders the console unusable when used with the
> Linux kernel's
On 29 September 2016 at 02:25, Markus Armbruster wrote:
> Patchew hiccup or a real problem?
Looks like a hiccup to me.
Can you let me know if you're happy with the new commit messages?
If so I'll apply these to target-arm.next.
thanks
-- PMM
On 24 September 2016 at 12:20, Alistair Francis wrote:
> Connect the ADC devices to the STM32F205 SoC.
>
> Signed-off-by: Alistair Francis
> ---
>
> #define FLASH_BASE_ADDRESS 0x0800
> #define FLASH_SIZE (1024 * 1024)
> @@ -52,6 +55,9 @@ typedef struct STM32F205State {
> STM32F2XXSyscf
On 24 September 2016 at 12:20, Alistair Francis wrote:
> Signed-off-by: Alistair Francis
> ---
> As the migration framework is not included in user mode this needs to be a
> new file.
>
> V8:
> - Use the standard qdev_init_gpio_in() function
> V7:
> - Use the standard QEMU init/realise function
On Thu, Sep 29, 2016 at 03:14:45PM -0700, Peter Maydell wrote:
> On 29 September 2016 at 13:46, Jonathan Neuschäfer
> wrote:
> > Signed-off-by: Jonathan Neuschäfer
> > ---
> > CODING_STYLE | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/CODING_STYLE b/CODING_STYLE
On Thu, Sep 29, 2016 at 12:16:48PM +0200, Andreas Färber wrote:
> Am 29.09.2016 um 02:16 schrieb David Gibson:
> > is there really any value to supporting the "class"
> > properties in addition to the "instance" properties?
>
> Yes, it makes enumerating available properties easier by not requiring
On Thu, Sep 29, 2016 at 12:23:41PM +0200, Andreas Färber wrote:
> Am 29.09.2016 um 12:21 schrieb Daniel P. Berrange:
> > On Thu, Sep 29, 2016 at 12:12:32PM +0200, Andreas Färber wrote:
> >> Am 29.09.2016 um 10:14 schrieb Daniel P. Berrange:
> >>> Practically all instances properties should become c
On Thu, Sep 29, 2016 at 09:14:16AM +0100, Daniel P. Berrange wrote:
> On Thu, Sep 29, 2016 at 10:16:41AM +1000, David Gibson wrote:
> > QOM has the concept of both "object class" properties and "object
> > instance" properties.
> >
> > The accessor functions installed for the rarely-used class pro
On Thu, Sep 29, 2016 at 12:48:07PM +0200, Thomas Huth wrote:
> Transactional memory is also supported on POWER8 KVM-HV if the
> KVM_CAP_PPC_HTM is not available in the kernel yet, so add a hack
> to allow TM here, too.
>
> Signed-off-by: Thomas Huth
Applied to ppc-for-2.8.
> ---
> hw/ppc/spapr
On Thu, Sep 29, 2016 at 12:48:06PM +0200, Thomas Huth wrote:
> It makes more sense if we have a proper function to check
> for KVM-PR than to check for the GET_PVINFO extension all
> over the place.
>
> Signed-off-by: Thomas Huth
Applied to ppc-for-2.8. I expanded your comment to say this shoul
On Thu, Sep 29, 2016 at 03:52:37PM +0530, Nikunj A Dadhania wrote:
> A few of the new instructions added inadvertently changed the type of
> old instruction(PPC_ALTIVEC) to PPC2_ALTIVEC_207 in the dual form
> declaration.
>
> commit: b5d569a1 (target-ppc: add vector extract instructions)
> commit:
On Thu, Sep 29, 2016 at 07:11:39PM +0300, Michael Tokarev wrote:
>05.03.2016 16:47, Wei Yang wrote:
>>According to linux kernel commit <89c1e79eb30> ("linux/bitmap.h: improve
>>BITMAP_{LAST,FIRST}_WORD_MASK"), these two macro could be improved.
>>
>>This patch takes this change and also move them a
On Sep 29, 2016, at 6:36 PM, Alex Bennée wrote:
>
> Programmingkid writes:
>
>> On Sep 29, 2016, at 2:19 PM, Alex Bennée wrote:
>>
>>>
>>> Programmingkid writes:
>>>
On Sep 29, 2016, at 12:17 AM, David Gibson wrote:
> On Tue, Sep 27, 2016 at 09:58:02AM -0700, Peter Maydell w
Programmingkid writes:
> On Sep 29, 2016, at 2:19 PM, Alex Bennée wrote:
>
>>
>> Programmingkid writes:
>>
>>> On Sep 29, 2016, at 12:17 AM, David Gibson wrote:
>>>
On Tue, Sep 27, 2016 at 09:58:02AM -0700, Peter Maydell wrote:
> On 27 September 2016 at 09:51, G 3 wrote:
>> The pr
On 29 September 2016 at 13:46, Jonathan Neuschäfer
wrote:
> Signed-off-by: Jonathan Neuschäfer
> ---
> CODING_STYLE | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/CODING_STYLE b/CODING_STYLE
> index e7fde15..a03a994 100644
> --- a/CODING_STYLE
> +++ b/CODING_STYLE
> @@
On 09/05/2016 11:43 AM, Kevin Wolf wrote:
Floppy controllers automatically create two floppy drive devices in qdev
now. (They always created two drives, but managed them only internally.)
This appears to *actually* create and expose two drives by default, is
this intentional?
Previously,
On Sep 29, 2016, at 2:19 PM, Alex Bennée wrote:
>
> Programmingkid writes:
>
>> On Sep 29, 2016, at 12:17 AM, David Gibson wrote:
>>
>>> On Tue, Sep 27, 2016 at 09:58:02AM -0700, Peter Maydell wrote:
On 27 September 2016 at 09:51, G 3 wrote:
> The problem with your reasoning is you
Hi everyone,
I am pleased to announce that the QEMU v2.6.2 stable release is now
available:
http://wiki.qemu.org/download/qemu-2.6.2.tar.bz2
v2.6.2 is now tagged in the official qemu.git repository,
and the stable-2.6 branch has been updated accordingly:
http://git.qemu.org/?p=qemu.git;a=sh
When probing for CPU model information, we need to reuse the code
that initializes CPUID fields, but not the remaining side-effects
of x86_cpu_realizefn(). Move that code to a separate function
that can be reused later.
Signed-off-by: Eduardo Habkost
---
Changes series v3 -> v4:
* New patch added
On Thu, Sep 29, 2016 at 06:14:49PM -0300, Eduardo Habkost wrote:
> Add a new test case to ensure the existing behavior of the
> feature parsing code wlil be kept.
s/wlil/will/
>
> Signed-off-by: Eduardo Habkost
Jonathan Neuschäfer
signature.asc
Description: PGP signature
Instead of treating the FP and SSE bits as special cases, add
them to the x86_ext_save_areas array. This will simplify the code
that calculates the supported xsave components and the size of
the xsave area.
Signed-off-by: Eduardo Habkost
---
Changes series v3 -> v4:
* New patch added to series
--
Instead of using custom feature name lookup code for
plus_features/minus_features, save the property names used in
"[+-]feature" and use object_property_set_bool() to set them.
Signed-off-by: Eduardo Habkost
---
Changes series v3 -> v4:
* New patch added to series
---
target-i386/cpu.c | 108 +++
On 09/29/2016 10:21 PM, Michael S. Tsirkin wrote:
On Thu, Sep 29, 2016 at 10:05:22PM +0200, Maxime Coquelin wrote:
On 09/29/2016 07:57 PM, Michael S. Tsirkin wrote:
On Thu, Sep 29, 2016 at 05:30:53PM +0200, Maxime Coquelin wrote:
...
Before enabling anything by default, we should first o
Add a new optional field to query-cpu-definitions schema:
"unavailable-features". It will contain a list of QOM properties
that prevent the CPU model from running in the current host.
Cc: David Hildenbrand
Cc: Michael Mueller
Cc: Christian Borntraeger
Cc: Cornelia Huck
Cc: Jiri Denemark
Cc: l
Fill the "unavailable-features" field on the x86 implementation
of query-cpu-definitions.
Cc: Jiri Denemark
Cc: libvir-l...@redhat.com
Signed-off-by: Eduardo Habkost
---
Changes v3 -> v4:
* Handle missing XSAVE components cleanly, but looking up
the original feature that required it
* Use x86_
VME is already disabled automatically when using TCG. So, instead
of pretending it is there when reporting CPU model data on
query-cpu-* QMP commands (making every CPU model to be reported
as not runnable), we can disable it by default on all CPU models
when using TCG.
Do that by adding a tcg_defa
x86_cpu_filter_features() will be reused by code that shouldn't
print any warning. Move the warning code to a new
x86_cpu_report_filtered_features() function, and call it from
x86_cpu_realizefn().
Signed-off-by: Eduardo Habkost
---
Changes v3 -> v4:
* Made x86_cpu_filter_features() void, make
x
Instead of keeping the aliases inside the feature name arrays and
require parsing the strings, just register alias properties
manually. This simplifies the property registration code and will
simplify code that needs to look up property names for CPUID
bits.
Signed-off-by: Eduardo Habkost
---
Cha
This series extends query-cpu-definitions to include an extra
field: "unavailable-features". The new field can be used to find
out reasons that prevent the CPU model from running in the
current host.
This will return information based on the current machine and
accelerator only. In the future we m
Instead of using the builtin_x86_defs array, use the QOM subclass
list to list CPU models on "-cpu ?" and "query-cpu-definitions".
Signed-off-by: Andreas Färber
[ehabkost: copied code from a patch by Andreas:
"target-i386: QOM'ify CPU", from March 2012]
Signed-off-by: Eduardo Habkost
---
targe
Add a new test case to ensure the existing behavior of the
feature parsing code wlil be kept.
Signed-off-by: Eduardo Habkost
---
Changes series v3 -> v4:
* New patch added to series
---
tests/test-x86-cpuid-compat.c | 39 +++
1 file changed, 39 insertions(+)
Instead of translating the feature name entries when adding
property names, store the actual property names in the feature
name array.
Signed-off-by: Eduardo Habkost
---
Changes series v3 -> v4:
* New patch added to series
---
target-i386/cpu.c | 31 ---
1 file change
On 09/29/2016 07:33 AM, Kevin Wolf wrote:
Am 28.09.2016 um 14:16 hat Vladimir Sementsov-Ogievskiy geschrieben:
I think jobs will need to remain "one coroutine, one job" for now,
but there's no reason why drive-backup or blockdev-backup can't
just create multiple jobs each if that's what they n
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