On 07/23/2016 02:14 PM, Nikunj A Dadhania wrote:
maddhd: Multiply-Add High Doubleword
maddhdu: Multiply-Add High Doubleword Unsigned
Above two instruction are dual form and differ by 1 bit
(31st bit)
Multiplies two 64-bit registers (RA * RB), adds third register(RC) to
the result(quadword) and
On 07/23/2016 02:14 PM, Nikunj A Dadhania wrote:
From: Vivek Andrew Sha
The CR number is provided in the opcode as - BFA (11:13)
Returns:
-1 if bit 0 of CR field is set
1 if bit 1 of CR field is set
0 otherwise.
Signed-off-by: Vivek Andrew Sha
[ reworded commit, used 32bit ops as crf
On 07/23/2016 02:14 PM, Nikunj A Dadhania wrote:
maddld: Multiply-Add Low Doubleword
Multiplies two 64-bit registers (RA * RB), adds third register(RC) to
the result(quadword) and returns the lower dword in the target
register(RT).
Signed-off-by: Nikunj A Dadhania
---
target-ppc/translate.c |
On 07/23/2016 02:14 PM, Nikunj A Dadhania wrote:
Search a byte in the stream of 8bytes provided in the register
Suggested-by: Richard Henderson
Signed-off-by: Nikunj A Dadhania
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 22 ++
target-ppc/translate.c | 1
On 07/23/2016 02:14 PM, Nikunj A Dadhania wrote:
Add ISA3.0: Count trailing zeros word instruction.
Signed-off-by: Nikunj A Dadhania
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 5 +
target-ppc/translate.c | 11 +++
3 files changed, 17 insertions(+)
Reviewed-b
On 07/23/2016 02:14 PM, Nikunj A Dadhania wrote:
From: Sandipan Das
Add ISA3.0 Count trailing zeros double word
Signed-off-by: Sandipan Das
[ added ISA300 flag ]
Signed-off-by: Nikunj A Dadhania
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 5 +
target-ppc/translate.c
On 07/23/2016 02:14 PM, Nikunj A Dadhania wrote:
Adding following instructions:
moduw: Modulo Unsigned Word
modsw: Modulo Signed Word
Signed-off-by: Nikunj A Dadhania
---
target-ppc/helper.h | 2 ++
target-ppc/int_helper.c | 15 +++
target-ppc/translate.c | 19 ++
On 07/23/2016 02:14 PM, Nikunj A Dadhania wrote:
ISA 3.0 Compare Ranged Byte instruction useful for
isupper/islower/isaplha kind of operation.
Signed-off-by: Nikunj A Dadhania
---
target-ppc/translate.c | 38 ++
1 file changed, 38 insertions(+)
Reviewed-by
On 07/23/2016 11:38 AM, Nikunj A Dadhania wrote:
> (2) You need to use ULL for 32-bit hosts, or casts, e.g.
Having it defined only for 64-bit
32-bit *host*, not 32-bit guest.
I.e. i686 host emulating ppc64 guest.
r~
Signed-off-by: Michael Rolnik
---
target-avr/Makefile.objs|2 +-
target-avr/translate-inst.c | 2622 +++
target-avr/translate.c |1 -
target-avr/translate.h |1 +
4 files changed, 2624 insertions(+), 2 deletions(-)
create mode 100
Signed-off-by: Michael Rolnik
---
target-avr/helper.c | 59 -
1 file changed, 58 insertions(+), 1 deletion(-)
diff --git a/target-avr/helper.c b/target-avr/helper.c
index ffc9378..3e61193 100644
--- a/target-avr/helper.c
+++ b/target-avr/helper
Signed-off-by: Michael Rolnik
---
target-avr/cpu.h | 13 ++-
target-avr/helper.c| 284 ++---
target-avr/helper.h| 8 +-
target-avr/translate.c | 9 ++
4 files changed, 299 insertions(+), 15 deletions(-)
diff --git a/target-avr/cpu.h
Signed-off-by: Michael Rolnik
---
target-avr/cpugen/CMakeLists.txt | 38 +++
target-avr/cpugen/README.md| 17 ++
target-avr/cpugen/cpu/avr.yaml | 214 ++
target-avr/cpugen/src/CMakeLists.txt | 63
target-avr/cpugen/src/cpugen.cpp
1. basic CPU structure
2. registers
3. no instructions
4. saving sreg, rampD, rampX, rampY, rampD, eind in HW representation
Signed-off-by: Michael Rolnik
---
arch_init.c | 2 +
configure | 5 +
default-configs/avr-softmmu.mak | 21 +
Signed-off-by: Michael Rolnik
---
target-avr/cpu.c | 313 ++-
target-avr/cpu.h | 48
target-avr/machine.c | 1 +
3 files changed, 361 insertions(+), 1 deletion(-)
diff --git a/target-avr/cpu.c b/target-avr/cpu.c
index 7e8d34b..0
Signed-off-by: Michael Rolnik
---
target-avr/Makefile.objs | 1 +
target-avr/decode.c | 693 +++
target-avr/helper.c | 2 +
target-avr/helper.h | 1 +
target-avr/translate.c | 12 -
5 files changed, 697 insertions(+), 12 deletion
Signed-off-by: Michael Rolnik
---
MAINTAINERS | 6 ++
hw/avr/Makefile.objs | 21 ++
hw/avr/sample-io.c | 176 +++
hw/avr/sample.c | 137 +++
4 files changed, 340 insertions(+)
create mode 1
Signed-off-by: Michael Rolnik
---
target-avr/translate-inst.h | 805
1 file changed, 805 insertions(+)
create mode 100644 target-avr/translate-inst.h
diff --git a/target-avr/translate-inst.h b/target-avr/translate-inst.h
new file mode 100644
index 00
This series of patches adds 8bit AVR cores to QEMU.
All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully tested
yet.
However I was able to execute simple code with functions. e.g fibonacci
calculation.
This series of patches include a non real, sample board.
No fuses support yet
On Sat, Jul 23, 2016 at 12:54:51 +0200, Paolo Bonzini wrote:
> On 23/07/2016 12:01, Peter Maydell wrote:
> > On 22 July 2016 at 17:36, Emilio G. Cota wrote:
> > This looks like we're passing NULL pointers to
> > printf %s specifiers. This is undefined behaviour at least
> > for POSIX printf, and I
On 20.07.2016 16:30, Colin Lord wrote:
> Here's v5 of the modularization series. Since it seems the concensus is
> that modularizing the format drivers is unnecessary, this series no
> longer modularizes those and is thus much shorter than before.
>
> v5:
> - No format drivers are modularized, the
On 07/23/2016 10:16 AM, Paolo Bonzini wrote:
On 23/07/2016 15:18, Corey Minyard wrote:
On 07/23/2016 02:46 AM, Paolo Bonzini wrote:
On 22/07/2016 21:50, miny...@acm.org wrote:
This has kind of opened a can of worms for me, though. Looking
at a lot of the devices, there is no unrealize functi
On Sat, Jul 23, 2016 at 1:34 PM, Paolo Bonzini wrote:
>> Ping for review!
>
> Hi,
>
> we're on hard freeze so it's normal that maintainers focus on bugfixes
> at this time.
>
OK. I will wait for 2 weeks and then ping to remind.
Thanks!
--
Pranith
> Ping for review!
Hi,
we're on hard freeze so it's normal that maintainers focus on bugfixes
at this time.
Paolo
> On Thu, Jul 14, 2016 at 4:20 PM, Pranith Kumar wrote:
> > Hello,
> >
> > The following series adds fence instruction generation support to
> > TCG. Based on feedback to the last
Add Alistair Francis as the maintainer for the Netduino 2
and SMM32F205 SoC.
Signed-off-by: Alistair Francis
Reviewed-by: Peter Crosthwaite
---
MAINTAINERS | 15 +++
1 file changed, 15 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d1439a8..e55be55 100644
--- a/MAINTAI
Add two functions one to get the irq handler function and another to get the
opaque data from a qemu_irq.
Signed-off-by: Alistair Francis
---
hw/core/irq.c| 10 ++
include/hw/irq.h | 4
2 files changed, 14 insertions(+)
diff --git a/hw/core/irq.c b/hw/core/irq.c
index 49ff2e6
If correctly configured allow the STM32F2xx timer to print
out the PWM duty cycle information.
Signed-off-by: Alistair Francis
Reviewed-by: Peter Crosthwaite
---
V3:
- Use OR instead of + for masking
- Improve clarity of print statement
V2:
- Fix up if statement braces
- Remove stm32f2xx_tim
Add the STM32F2xx SPI device.
Signed-off-by: Alistair Francis
---
V4:
- Add VMState
- Small fixes
V2:
- Address Peter C's comments
default-configs/arm-softmmu.mak | 1 +
hw/ssi/Makefile.objs| 1 +
hw/ssi/stm32f2xx_spi.c | 227
Cleanup the individual DeviceState and SysBusDevice
variables to re-use the same variable for each
device.
Signed-off-by: Alistair Francis
Reviewed-by: Peter Crosthwaite
---
hw/arm/stm32f205_soc.c | 35 +--
1 file changed, 17 insertions(+), 18 deletions(-)
diff
Add the STM32F2xx ADC device. This device randomly
generates values on each read.
This also includes creating a hw/adc directory.
Signed-off-by: Alistair Francis
---
V4:
- Remove the rand() function
- Add VMState
- Small cleanups
V2:
- Address Peter C's comments
- Create a ADC folder and mo
This patchset continues with the Netduino 2 and STM32F205 SoC
work.
This patch series makes a small change to the STM32F2xx
SoC to tidy up the code.
Next a feature is added to the STM32F2xx timer to display the
PWM duty cycle, when debugging is enabled.
Then the STM32F2xx SPI and ADC devices are
Ping for review!
On Thu, Jul 14, 2016 at 4:20 PM, Pranith Kumar wrote:
> Hello,
>
> The following series adds fence instruction generation support to
> TCG. Based on feedback to the last series, I added the four
> combinations of orderings modeled after Sparc membar.
>
> This has been tested and
On 23/07/2016 15:18, Corey Minyard wrote:
> On 07/23/2016 02:46 AM, Paolo Bonzini wrote:
>>
>> On 22/07/2016 21:50, miny...@acm.org wrote:
>>> This has kind of opened a can of worms for me, though. Looking
>>> at a lot of the devices, there is no unrealize function and that
>>> can leave a lot o
On Fri, Jul 22, 2016 at 09:28:58AM +0200, Laurent Vivier wrote:
>
>
> On 22/07/2016 08:43, David Gibson wrote:
> > On Thu, Jul 21, 2016 at 06:47:56PM +0200, Laurent Vivier wrote:
> >> As userfaultfd syscall is available on powerpc, migration
> >> postcopy can be used.
> >>
> >> This patch adds th
On 07/23/2016 02:46 AM, Paolo Bonzini wrote:
On 22/07/2016 21:50, miny...@acm.org wrote:
This has kind of opened a can of worms for me, though. Looking
at a lot of the devices, there is no unrealize function and that
can leave a lot of things hanging. And for ISA bus devices, there
is no way
On 23/07/2016 12:01, Peter Maydell wrote:
> On 22 July 2016 at 17:36, Emilio G. Cota wrote:
>> So far, QHT functions assume that the passed qht has previously been
>> initialized--otherwise they segfault.
>>
>> This patch makes an exception for qht_statistics_init, with the goal
>> of simplifyin
On 22 July 2016 at 17:36, Emilio G. Cota wrote:
> So far, QHT functions assume that the passed qht has previously been
> initialized--otherwise they segfault.
>
> This patch makes an exception for qht_statistics_init, with the goal
> of simplifying calling code. For instance, qht_statistics_init i
22.07.2016, 23:06, "Peter Maydell" :
> On 22 July 2016 at 03:30, Icenowy Zheng wrote:
>> According to comments in /usr/include/linux/eventpoll.h, x86_64 have
>> the same memory layout of struct target_epoll_event as i386. So on a
>> aligned host, if x86_64 should be packed, i386 will also nee
ISA 3.0 has introduced EO - Expanded Opcode. Introduce third level
indirect opcode table and corresponding parsing routines.
EO (11:12) Expanded opcode field
Formats: XX1
EO (11:15) Expanded opcode field
Formats: VX, X, XX2
Signed-off-by: Nikunj A Dadhania
---
target-ppc/translate.c | 82
Search a byte in the stream of 8bytes provided in the register
Suggested-by: Richard Henderson
Signed-off-by: Nikunj A Dadhania
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 22 ++
target-ppc/translate.c | 12
3 files changed, 35 insertions(+)
maddld: Multiply-Add Low Doubleword
Multiplies two 64-bit registers (RA * RB), adds third register(RC) to
the result(quadword) and returns the lower dword in the target
register(RT).
Signed-off-by: Nikunj A Dadhania
---
target-ppc/translate.c | 14 ++
1 file changed, 14 insertions(+
maddhd: Multiply-Add High Doubleword
maddhdu: Multiply-Add High Doubleword Unsigned
Above two instruction are dual form and differ by 1 bit
(31st bit)
Multiplies two 64-bit registers (RA * RB), adds third register(RC) to
the result(quadword) and returns the higher dword in the target
register(RT)
Adding following instructions:
moduw: Modulo Unsigned Word
modsw: Modulo Signed Word
Signed-off-by: Nikunj A Dadhania
---
target-ppc/helper.h | 2 ++
target-ppc/int_helper.c | 15 +++
target-ppc/translate.c | 19 +++
3 files changed, 36 insertions(+)
diff --gi
From: Sandipan Das
Add ISA3.0 Count trailing zeros double word
Signed-off-by: Sandipan Das
[ added ISA300 flag ]
Signed-off-by: Nikunj A Dadhania
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 5 +
target-ppc/translate.c | 10 ++
3 files changed, 16 insertions(+)
Add ISA3.0: Count trailing zeros word instruction.
Signed-off-by: Nikunj A Dadhania
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 5 +
target-ppc/translate.c | 11 +++
3 files changed, 17 insertions(+)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 8a
From: Vivek Andrew Sha
The CR number is provided in the opcode as - BFA (11:13)
Returns:
-1 if bit 0 of CR field is set
1 if bit 1 of CR field is set
0 otherwise.
Signed-off-by: Vivek Andrew Sha
[ reworded commit, used 32bit ops as crf is 32bits ]
Signed-off-by: Nikunj A Dadhania
---
ISA 3.0 Compare Ranged Byte instruction useful for
isupper/islower/isaplha kind of operation.
Signed-off-by: Nikunj A Dadhania
---
target-ppc/translate.c | 38 ++
1 file changed, 38 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
in
ISA 3.0 instruction for adding immediate value shifted with next
instruction address and return the result in the target register.
Signed-off-by: Nikunj A Dadhania
Reviewed-by: David Gibson
---
target-ppc/translate.c | 26 ++
1 file changed, 26 insertions(+)
diff --git
This flag will be used for POWER9 instructions.
Signed-off-by: Nikunj A Dadhania
Reviewed-by: David Gibson
---
target-ppc/cpu.h| 5 -
target-ppc/translate_init.c | 2 +-
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 5fce
This set starts adding new instructions for POWER9 described in ISA3.0.
Patches:
01-02: First two patches adds the required POWER9 cpu model and ISA defines.
03-12: Adds following instructions:
addpcis : Add PC Immediate Shifted
cmprb : Compare Ranged Byte
Adding following instructions for ISA3.0 support
modud: Modulo Unsigned Dword
modsd: Modulo Signed Dword
Signed-off-by: Nikunj A Dadhania
---
target-ppc/helper.h | 2 ++
target-ppc/int_helper.c | 16
target-ppc/translate.c | 15 +++
3 files changed, 33 inserti
From: "Aneesh Kumar K.V"
Signed-off-by: Aneesh Kumar K.V
[ rebased and added POWER9 alias and POWER9 SPAPR core ]
Signed-off-by: Nikunj A Dadhania
---
hw/ppc/spapr_cpu_core.c | 5 +++
target-ppc/cpu-models.c | 5 +++
target-ppc/cpu-models.h | 1 +
target-ppc/cpu-qom.h|
Hello all,
I, working on AMD IOMMU interrupt remapping would like to ask some
questions on Qemu IOAPIC id.
I currently have a problem in that Linux AMD IOMMU driver expects at least
one IOAPIC on the chipset to have ID 0xa0 while Qemu IOAPIC id is always 0.
I am faced with two options
-Change
> On 07/20/2016 09:27 PM, Dave Hansen wrote:
> > QEMU 2.6 added support for the XSAVE family of instructions, which
> > includes the XSETBV instruction which allows setting the 'XCR0'
> > register.
> >
> > But, when booting Linux kernels with XSAVE support enabled, I was
> > getting very early cras
On 22/07/2016 21:50, miny...@acm.org wrote:
>
> This has kind of opened a can of worms for me, though. Looking
> at a lot of the devices, there is no unrealize function and that
> can leave a lot of things hanging. And for ISA bus devices, there
> is no way to unregister ports.
Right, this i
On 22/07/2016 18:36, Emilio G. Cota wrote:
> So far, QHT functions assume that the passed qht has previously been
> initialized--otherwise they segfault.
>
> This patch makes an exception for qht_statistics_init, with the goal
> of simplifying calling code. For instance, qht_statistics_init is
>
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