Eric Blake writes:
> On 01/22/2016 05:18 AM, Markus Armbruster wrote:
[...]
>> Crazy thought: unboxing the implicit struct should make this interface
>> wart go away. If we commit to do that later, we can "solve" our
>> documentation problem the same way as for visit_start_union(): FIXME
>> shou
Thomas Huth, on Wed 10 Feb 2016 08:18:45 +0100, wrote:
> On 09.02.2016 22:19, Samuel Thibault wrote:
> > Thanks for your reviews so far! I have integrated the rest of comments,
> > the only remaining question for patches 1-3 is about srand() and rand().
>
> I personally don't mind whether you use
On 09.02.2016 22:19, Samuel Thibault wrote:
> Thanks for your reviews so far! I have integrated the rest of comments,
> the only remaining question for patches 1-3 is about srand() and rand().
I personally don't mind whether you use rand(), g_random_int_range() or
g_rand_int_range() here, but of
Hi Allen,
On Wed, 10 Feb 2016 03:40:54 +
"Kay, Allen M" wrote:
> > -Original Message-
> > From: Alex Williamson [mailto:alex.william...@redhat.com]
> > Sent: Tuesday, February 09, 2016 1:33 PM
> > To: Kay, Allen M
> > Cc: ehabk...@redhat.com; m...@redhat.com;
> > stefano.stabell...@
Thanks Peter.
Regarding the questions, we have hw board which has Cortex-A7, so we
thought we have to go with A7 emulation. we were not very sure A15
emulation will be almost equivalent to A7 emulation.
All we want to do is A7 emulation but now I am understanding that A15
emulation should similar
That is, global_mem registers whose base is another global_mem
register, rather than a fixed register.
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 95 ---
tcg/tcg.h | 2 ++
2 files changed, 68 insertions(+), 29 deletions(-)
diff
Via indirection off cpu_regwptr.
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 49 ++--
1 file changed, 27 insertions(+), 22 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 4be56dd..66008f7 100644
Since we've not got liveness analysis for indirect bases,
placing them at the end of the call-saved registers makes
it more likely that it'll stay live.
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 43 ---
1 file changed, 32 insertions(+), 11 deletions
Create tables for the various global registers that need allocation.
Remove one level of indirection from gregnames and fregnames.
Signed-off-by: Richard Henderson
---
target-sparc/translate.c | 157 +--
1 file changed, 70 insertions(+), 87 deletions(
The bulk of the original patch set has been reviewed and
comitted. But the actual end result is still outstanding.
r~
Richard Henderson (4):
tcg: Implement indirect memory registers
tcg: Allocate indirect_base temporaries in a different order
target-sparc: Tidy global register initializa
> -Original Message-
> From: Alex Williamson [mailto:alex.william...@redhat.com]
> Sent: Tuesday, February 09, 2016 1:33 PM
> To: Kay, Allen M
> Cc: ehabk...@redhat.com; m...@redhat.com;
> stefano.stabell...@eu.citrix.com; qemu-devel@nongnu.org;
> pbonz...@redhat.com; r...@twiddle.net; R
On 02/10/2016 08:14 AM, Lluís Vilanova wrote:
Adds the 'TCGv_env' type for pointers to 'CPUArchState' objects. The
tracing infrastructure later needs to differentiate between regular
pointers and pointers to vCPUs.
Also changes all targets to use the new 'TCGv_cpu' type instead of the
generic 'T
On Wed, Feb 03, 2016 at 10:47:29PM +, Matt Fleming wrote:
> On Thu, 28 Jan, at 09:23:10AM, Gabriel L. Somlo wrote:
> > From: "Gabriel Somlo"
> >
> > Allow access to QEMU firmware blobs, passed into the guest VM via
> > the fw_cfg device, through SysFS entries. Blob meta-data (e.g. name,
> > s
The thought was raised that it might be useful to create a "diff"
command for bitmaps that allow us to populate a dirty bitmap based on
the difference between a currently loaded disk image and some
point-in-time stored on disk (an earlier full backup, incremental
backup, etc).
I originally voiced
Hi Richard,
On Tue, Feb 09, 2016 at 04:50:52PM +, James Hogan wrote:
> > @@ -589,6 +608,50 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
> > }
> > if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {
> > tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16)
On 01/22/2016 05:18 AM, Markus Armbruster wrote:
> Please think twice before from growing the QAPI patch queue further. We
> really, really need to clear it. A TODO comment would be welcome,
> though.
Yes, especially with 2.6 soft freeze fast approaching.
+/**
+ * Prepare to visit a
Hi Richard,
On Tue, Feb 09, 2016 at 04:22:34PM +, James Hogan wrote:
> (gdb) disas/r
> Dump of assembler code for function code_gen_buffer:
>0x00fff30b0064 <+0>: f8 ff 11 8e lw s1,-8(s0)
> => 0x00fff30b0068 <+4>: 08 00 11 60 bnezalc s1,0xfff30b008c
>
Note al
The Linux kernel accesses this register early in its setup.
Signed-off-by: Christopher Covington
Signed-off-by: Alistair Francis
Reviewed-by: Peter Maydell
---
target-arm/helper.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 1778431
Signed-off-by: Aaron Lindsay
Signed-off-by: Alistair Francis
Tested-by: Nathan Rossi
Reviewed-by: Peter Maydell
---
target-arm/helper.c | 12
1 file changed, 12 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 3072aeb..1778431 100644
--- a/target-arm/he
Signed-off-by: Aaron Lindsay
Signed-off-by: Alistair Francis
Tested-by: Nathan Rossi
---
V2:
- Add the AArch32 versions of the register
- Relocate the registers
- Update the access information
target-arm/cpu-qom.h | 2 ++
target-arm/cpu.c | 2 ++
target-arm/cpu64.c | 2 ++
target-a
This patch set is based on the patch sent by Christopher Covington and
written by Aaron Lindsay which was sent as an RFC (Implement remaining
PMU functionality).
It adds a few performance monitoring related registers.
V3:
- Fixes pased on Peter Maydell's feedback
- Remove patch 2 and 5 to get t
On Tue, Feb 9, 2016 at 9:32 AM, Peter Maydell wrote:
> On 6 February 2016 at 00:55, Alistair Francis
> wrote:
>> This patch adds the following registers including read and write functions:
>> PMSELR, PMSELR_EL0, PMXEVCNTR, PMXEVCNTR_EL0, PMXEVTYPER and PMXEVTYPER_EL0.
>>
>> Signed-off-by: Aaron L
Quoting Yuriy Pudgorodskiy (2016-01-20 05:30:17)
> On 1/14/2016 5:46 PM, Daniel P. Berrange wrote:
> > On Thu, Jan 14, 2016 at 05:22:39PM +0300, Denis V. Lunev wrote:
> >> On 01/14/2016 05:18 PM, Marc-André Lureau wrote:
> >>> Hi
> >>>
> >>> On Wed, Jan 6, 2016 at 1:01 PM, Denis V. Lunev wrote:
>
On 02/08/2016 09:01 PM, Fam Zheng wrote:
> On Mon, 02/08 16:49, John Snow wrote:
>>> +def _guess_command(self):
>>> +for c in [["docker"], ["sudo", "-n", "docker"]]:
>>
>> If the sudo version fails (Say, because a password prompt shows up) we
>> get the unhelpful error "Cannot find wo
On Tue, Feb 9, 2016 at 9:19 AM, Peter Maydell wrote:
> On 6 February 2016 at 00:55, Alistair Francis
> wrote:
>> Signed-off-by: Aaron Lindsay
>> Signed-off-by: Alistair Francis
>> Tested-by: Nathan Rossi
>> ---
>>
>> target-arm/cpu-qom.h | 2 ++
>> target-arm/cpu.c | 2 ++
>> target-arm/c
On 02/04/2016 12:51 AM, Shannon Zhao wrote:
>
>
> On 2016/2/4 14:10, Wei Huang wrote:
>>
>> On 02/03/2016 07:44 PM, Shannon Zhao wrote:
>> I reversed the order of edge pulling. The state is 1 according to printk
>> inside gpio_keys driver. However the reboot still failed with two
>> reboots (
On 01/26/2016 05:38 AM, Fam Zheng wrote:
> Signed-off-by: Fam Zheng
> ---
> blockdev.c | 20
> qapi/block-core.json | 22 ++
> qmp-commands.hx | 31 +++
> 3 files changed, 73 insertions(+)
>
> diff --git a/bloc
On Tue, Feb 9, 2016 at 11:35 AM, Alistair Francis
wrote:
> On Tue, Feb 9, 2016 at 8:06 AM, Alex Bennée wrote:
>>
>> Alistair Francis writes:
>>
>>> This API provides some encapsulation of registers and factors our some
>>> common functionality to common code. Bits of device state (usually MMIO
>
Denis V. Lunev writes:
> we should call trace_init_backends() before trace_init_file() for
> CONFIG_TRACE_SIMPLE There is no difference for other cases.
>
> This problem was introduced by the commit
> commit 41fc57e44ed64cd4ab5393d83624afd897dabd4f
> Author: Paolo Bonzini
> Date:
Connect the I/O Unit System Level Control Registers device
to the ZynqMP model. Unfortunatly the GPIO links can not be
connected yet as the SD device is not yet attached to the
ZynqMP machine.
Signed-off-by: Alistair Francis
---
V2:
- Fix up device connection
hw/arm/xlnx-zynqmp.c | 13
From: Peter Crosthwaite
Add GPIO functionality to the register API. This allows association
and automatic connection of GPIOs to bits in registers. GPIO inputs
will attach to handlers that automatically set read-only bits in
registers. GPIO outputs will be updated to reflect their field value
whe
From: Peter Crosthwaite
IOU = I/O Unit
SLCR = System Level Control Registers
This IP is a misc collections of control registers that switch various
properties of system IPs. Currently the only thing implemented is the
SD_SLOTTYPE control (implemented as a GPIO output).
Signed-off-by: Peter Cros
From: Peter Crosthwaite
An API similar to the existing qdev_get_gpio_in() except gets outputs.
Useful for:
1: Implementing lightweight devices that don't want to keep pointers
to their own GPIOs. They can get their GPIO pointers at runtime from
QOM using this API.
2: testing or debugging code w
From: Peter Crosthwaite
For passing all GPIOs of all names from a contained device to a
container.
Signed-off-by: Peter Crosthwaite
Signed-off-by: Alistair Francis
---
hw/core/qdev.c | 9 +
include/hw/qdev-core.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/hw/core/
From: Peter Crosthwaite
Minimal device model for devcfg module of Zynq. DMA capabilities and
interrupt generation supported.
Signed-off-by: Peter Crosthwaite
Signed-off-by: Alistair Francis
---
default-configs/arm-softmmu.mak | 1 +
hw/dma/Makefile.objs | 1 +
hw/dma/xlnx-
From: Peter Crosthwaite
Little macro that just gives you N ones (justified to LSB).
Signed-off-by: Peter Crosthwaite
Signed-off-by: Alistair Francis
---
include/qemu/bitops.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h
index 8164225..27
From: Peter Crosthwaite
Add a helper that will scan a static RegisterAccessInfo Array
and populate a container MemoryRegion with registers as defined.
Signed-off-by: Peter Crosthwaite
Signed-off-by: Alistair Francis
---
V3:
- Fix typo
V2:
- Use memory_region_add_subregion_no_print()
hw/cor
From: Peter Crosthwaite
Add a routine to set or override the opaque data of an IRQ.
Qdev currently always initialises IRQ opaque as the device itself.
This allows you to override to a custom opaque in the case where
there is extra or different data needed.
Signed-off-by: Peter Crosthwaite
Sign
This API provides some encapsulation of registers and factors our some
common functionality to common code. Bits of device state (usually MMIO
registers), often have all sorts of access restrictions and semantics
associated with them. This API allow you to define what those
restrictions are on a bi
From: Peter Crosthwaite
Allow defining of optional address decoding information in register
definitions. This is useful for clients that want to associate
registers with specific addresses.
Signed-off-by: Peter Crosthwaite
Signed-off-by: Alistair Francis
---
V3:
- Remove unused flags option
From: Peter Crosthwaite
QOMify registers as a child of TYPE_DEVICE. This allows registers to
define GPIOs.
Define an init helper that will do QOM initialisation as well as setup
the r/w fast paths.
Signed-off-by: Peter Crosthwaite
Signed-off-by: Alistair Francis
Reviewed-by: KONRAD Frederic
From: Peter Crosthwaite
Add memory io handlers that glue the register API to the memory API.
Just translation functions at this stage. Although it does allow for
devices to be created without all-in-one mmio r/w handlers.
Signed-off-by: Peter Crosthwaite
Signed-off-by: Alistair Francis
---
h
From: Peter Crosthwaite
Define some macros that can be used for defining registers and fields.
The REG32 macro will define A_FOO, for the byte address of a register
as well as R_FOO for the uint32_t[] register number (A_FOO / 4).
The FIELD macro will define FOO_BAR_MASK, FOO_BAR_SHIFT and
FOO_B
Add a function called memory_region_add_subregion_no_print() that
creates memory subregions that won't be printed when running
the 'info mtree' command.
Signed-off-by: Alistair Francis
Reviewed-by: KONRAD Frederic
---
include/exec/memory.h | 17 +
memory.c | 10 +++
This patch series is based on Peter C's original register API. His
original cover letter is below.
I have added a new function memory_region_add_subregion_no_print() which
stops memory regions from being printed by 'info mtree'. This is used to
avoid evey register being printed when running 'info
Quoting Eric Blake (2016-02-09 15:27:16)
> Magic constants are a pain to use, especially when we run the
> risk that our choice of '1' for QGA_SEEK_CUR might differ from
> the host or guest's choice of SEEK_CUR. Better is to use an
> enum value, via a qapi alternate type for back-compatibility.
>
On 01/26/2016 05:38 AM, Fam Zheng wrote:
> When omitted it defaults to false with unchanged behavior.
>
> When set to true, the created dirty bitmap is made persistent if supported, it
> requires support from the active image format. Otherwise an error is returned.
>
> Signed-off-by: Fam Zheng
On 01/26/2016 05:38 AM, Fam Zheng wrote:
> By implementing bdrv_dirty_bitmap_set_persistent, a driver can support
> the persistent dirty bitmap feature.
>
> Once a dirty bitmap is made persistent, the driver is responsible for saving
> the dirty bitmap when appropriate, for example before close;
On Tue, Feb 9, 2016 at 9:22 AM, Alex Bennée wrote:
>
> Alistair Francis writes:
>
>> This patch series is based on Peter C's original register API. His
>> original cover letter is below.
>
> OK that's my first pass review. I seem to be missing 16/16 in my inbox
> though.
Thanks for going through
On Tue, Feb 9, 2016 at 9:08 AM, Alex Bennée wrote:
>
> Alistair Francis writes:
>
>> From: Peter Crosthwaite
>>
>> Minimal device model for devcfg module of Zynq. DMA capabilities and
>> interrupt generation supported.
>>
>> Signed-off-by: Peter Crosthwaite
>> Signed-off-by: Alistair Francis
>
On Tue, 9 Feb 2016 19:47:49 +
"Kay, Allen M" wrote:
> > -Original Message-
> > From: Alex Williamson [mailto:alex.william...@redhat.com]
> > Sent: Tuesday, February 09, 2016 9:44 AM
> > Cc: ehabk...@redhat.com; m...@redhat.com;
> > stefano.stabell...@eu.citrix.com; qemu-devel@nongnu.o
On 01/26/2016 05:38 AM, Fam Zheng wrote:
> By implementing bdrv_dirty_bitmap_set_persistent, a driver can support
> the persistent dirty bitmap feature.
>
> Once a dirty bitmap is made persistent, the driver is responsible for saving
> the dirty bitmap when appropriate, for example before close;
Magic constants are a pain to use, especially when we run the
risk that our choice of '1' for QGA_SEEK_CUR might differ from
the host or guest's choice of SEEK_CUR. Better is to use an
enum value, via a qapi alternate type for back-compatibility.
With this,
{"command":"guest-file-seek", "argumen
Thanks for your reviews so far! I have integrated the rest of comments,
the only remaining question for patches 1-3 is about srand() and rand().
Samuel
Adds the 'TCGv_env' type for pointers to 'CPUArchState' objects. The
tracing infrastructure later needs to differentiate between regular
pointers and pointers to vCPUs.
Also changes all targets to use the new 'TCGv_cpu' type instead of the
generic 'TCGv_ptr'. As of now, the change is merely cosmet
This property identifies events that trace vCPU-specific information.
It adds a "CPUState*" argument to events with the property, identifying
the vCPU raising the event. TCG translation events also have a
"TCGv_cpu" implicit argument that is later used as the "CPUState*"
argument at execution time
The current code forces the use of a chain of ".original" dereferences,
which looks odd.
Signed-off-by: Lluís Vilanova
---
scripts/tracetool/__init__.py|4 +---
scripts/tracetool/format/events_h.py |4 ++--
scripts/tracetool/format/tcg_h.py|4 ++--
3 files changed, 5 inse
NOTE: This series should complete the framework for guest code tracing. From
here on, other series can concurrently add actual events and improve the
guest code tracing features and performance (e.g., control tracing
independently on each vCPU).
This series introduces the "vcpu"
Lets the user to manage event arguments as a list, and simplifies
argument concatenation.
Signed-off-by: Lluís Vilanova
---
scripts/tracetool/__init__.py | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/scripts/tracetool/__init__.py b/scripts/tracetool/__ini
Thomas Huth, on Tue 09 Feb 2016 21:44:18 +0100, wrote:
> > + case AF_INET6:
> > + udp6_output(so, m, (struct sockaddr_in6 *) &saddr,
> > + (struct sockaddr_in6 *) &daddr);
> > + break;
> > default:
> > + g_assert_not_reached();
>
>
Lluís Vilanova writes:
> Alex Bennée writes:
>> Lluís Vilanova writes:
>>> The tracing infrastructure later needs to differentiate between regular
>>> pointers and pointers to vCPUs.
>>>
>>> Also changes all targets to use the new 'TCGv_cpu' type instead of the
>>> generic 'TCGv_ptr'. As of now
On 01/26/2016 05:38 AM, Fam Zheng wrote:
> Signed-off-by: Fam Zheng
> ---
> block/io.c| 2 +-
> include/block/block.h | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/block/io.c b/block/io.c
> index b964e7e..15e461f 100644
> --- a/block/io.c
> +++ b/block
This is used by the ARM JTAG DCC console in the Linux kernel,
but can be ignored in order to continue booting.
Co-Authored-By: Andreas Schwab
Signed-off-by: Dirk Mueller
---
target-arm/helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
inde
See C5.1.5 of the ARMv8 Reference Manual
Signed-off-by: Dirk Mueller
---
target-arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 5ea507f..954e6e8 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3682,7
On 01/26/2016 05:38 AM, Fam Zheng wrote:
> With the return value decoupled from VMDK, it can be reused by other block
> code.
>
> Signed-off-by: Fam Zheng
> ---
> block.c | 40
> block/vmdk.c | 40 -
On 09.02.2016 20:56, Samuel Thibault wrote:
> Thomas Huth, on Tue 09 Feb 2016 17:14:15 +0100, wrote:
>> A lot of these defines seem to be define in already
>> (as recommended by RFC 3542) ... would it be feasible to use that
>> standard header, instead of redefining here everything?
>
> I'm wonde
On 08.02.2016 11:28, Samuel Thibault wrote:
> From: Guillaume Subiron
>
> This adds the sin6 case in the fhost and lhost unions and related macros.
> It adds udp6_input() and udp6_output().
> It adds the IPv6 case in sorecvfrom().
> Finally, udp_input() is called by ip6_input().
>
> Signed-off-b
Thomas Huth, on Tue 09 Feb 2016 17:14:15 +0100, wrote:
> > +srand(time(NULL));
>
> That srand should maybe be done in main() instead? (Otherwise every
> subsystem might end up in repeating this all over the place)
Eric Blake added:
> >> +#define rand_a_b(a, b)\
> >> +(rand()%(int)(b-a)+a)
While starting the softmmu version of QEMU, the simple backend waits for the
writeout thread to signal a condition variable when initializing the output file
path. But since the writeout thread has not been created, it just waits forever.
Thanks,
Lluis
Thomas Huth, on Tue 09 Feb 2016 20:32:49 +0100, wrote:
> Maybe checkpatch.pl could also be silenced by putting the "==" at the
> end of the first line instead?
No, it still warns.
Samuel
Thomas Huth, on Tue 09 Feb 2016 17:14:15 +0100, wrote:
> A lot of these defines seem to be define in already
> (as recommended by RFC 3542) ... would it be feasible to use that
> standard header, instead of redefining here everything?
I'm wondering how widely available that is. On windows, for i
On Tue, Feb 9, 2016 at 8:12 AM, Alex Bennée wrote:
>
> Alistair Francis writes:
>
>> From: Peter Crosthwaite
>>
>> Add a helper that will scan a static RegisterAccessInfo Array
>> and populate a container MemoryRegion with registers as defined.
>>
>> Signed-off-by: Peter Crosthwaite
>> Signed-o
On 08.02.2016 11:28, Samuel Thibault wrote:
> From: Yann Bordenave
>
> Disambiguation : icmp_error is renamed into icmp_send_error, since it
> doesn't manage errors, but only sends ICMP Error messages.
You could maybe also put the icmp_error (for IPv4) related stuff into a
separate patch ... but
> -Original Message-
> From: Alex Williamson [mailto:alex.william...@redhat.com]
> Sent: Tuesday, February 09, 2016 9:44 AM
> Cc: ehabk...@redhat.com; m...@redhat.com;
> stefano.stabell...@eu.citrix.com; qemu-devel@nongnu.org;
> pbonz...@redhat.com; r...@twiddle.net; Kay, Allen M
>
> Sub
On Tue, Feb 9, 2016 at 8:06 AM, Alex Bennée wrote:
>
> Alistair Francis writes:
>
>> This API provides some encapsulation of registers and factors our some
>> common functionality to common code. Bits of device state (usually MMIO
>> registers), often have all sorts of access restrictions and sem
On 9 February 2016 at 15:11, Stefan Hajnoczi wrote:
> The following changes since commit ee8e8f92a730afc17ab8be6e86df6b9a23b8ebc6:
>
> Merge remote-tracking branch
> 'remotes/amit-migration/tags/migration-for-2.6-2' into staging (2016-02-05
> 14:20:46 +)
>
> are available in the git reposi
On 09.02.2016 17:31, Samuel Thibault wrote:
> Thomas Huth, on Tue 09 Feb 2016 17:14:15 +0100, wrote:
>>> +return (a.s6_addr[prefix_len / 8] >> (8 - (prefix_len % 8)))
>>> +== (b.s6_addr[prefix_len / 8] >> (8 - (prefix_len % 8)));
>>
>> checkpatch.pl complains here:
>>
>> ERROR: return i
On 02/09/2016 09:12 PM, John Snow wrote:
On 02/09/2016 11:58 AM, Denis V. Lunev wrote:
On 02/09/2016 07:49 PM, John Snow wrote:
On 02/09/2016 09:37 AM, Denis V. Lunev wrote:
On 02/09/2016 05:21 PM, Stefan Hajnoczi wrote:
On Fri, Feb 05, 2016 at 11:28:42AM +0300, Denis V. Lunev wrote:
On 02/
On 02/09/2016 03:28 PM, Alex Bennée wrote:
Denis V. Lunev writes:
On 02/08/2016 09:43 PM, Alex Bennée wrote:
Stefan Hajnoczi writes:
From: Paolo Bonzini
This is cleaner, and improves error reporting with -daemonize.
Signed-off-by: Paolo Bonzini
Signed-off-by: Denis V. Lunev
Acked-by:
On 02/09/16 11:59, Paolo Bonzini wrote:
> The "max" value is being compared with >=, but addr + width points to
> the first byte that will _not_ be copied. Subtract one like it is
> already done above for the height.
>
> Cc: Gerd Hoffmann
> Signed-off-by: Paolo Bonzini
> ---
> hw/display/cirru
On 02/10/2016 12:28 AM, Paolo Bonzini wrote:
On 09/07/2015 10:17, Richard Henderson wrote:
+/* Disallow enabling only half of MPX. */
+if ((mask ^ (mask * (XSTATE_BNDCSR / XSTATE_BNDREGS))) & XSTATE_BNDCSR) {
I'm refreshing patches 1-4 to add PKE support, and this caught my eye...
Wh
Actively redefining 'inline' is wrong for C++, where gcc has an
extension 'inline namespace' which fails to compile if the
keyword 'inline' is replaced by a macro expansion. This will
matter once we start to include "qemu/osdep.h" first from C++
files, depending also on whether the system headers
The arm_generate_debug_exceptions() function as originally implemented
assumes no EL2 or EL3. Since we now have much more of an implementation
of those now, fix this assumption.
Signed-off-by: Peter Maydell
Reviewed-by: Alex Bennée
Reviewed-by: Sergey Fedorov
Message-id: 1454506721-11843-5-git-
Fix a typo where "EL2" was written but "EL3" intended.
Signed-off-by: Peter Maydell
Reviewed-by: Alex Bennée
Reviewed-by: Edgar E. Iglesias
Reviewed-by: Sergey Fedorov
Message-id: 1454506721-11843-2-git-send-email-peter.mayd...@linaro.org
---
target-arm/cpu.h | 2 +-
1 file changed, 1 inserti
In syndrome register values, the IL bit indicates the instruction
length, and is 1 for 4-byte instructions and 0 for 2-byte
instructions. All A64 and A32 instructions are 4-byte, but
Thumb instructions may be either 2 or 4 bytes long. Unfortunately
we named the parameter to the syn_* functions for
The registers MVBAR and SCR should have the behaviour of trapping to
EL3 if accessed from Secure EL1, but we were incorrectly implementing
them to UNDEF (which would trap to EL1). Fix this by using the new
access_trap_aa32s_el1() access function.
Signed-off-by: Peter Maydell
Reviewed-by: Alex Be
On Tue, 9 Feb 2016, Richard Henderson wrote:
> > So to be correct + efficient, it should only put the nop in if the next
> > generated instruction is a CTI. I imagine that would be a bit messy /
> > fragile, but maybe doable? I haven't looked too deeply.
>
> Ouch, I didn't notice this about these
A previous patch patch changed the type of REG from int
to enum TCGReg, which provokes the following bug in clang:
https://llvm.org/bugs/show_bug.cgi?id=16154
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/tcg.c b/tcg/tc
From: Sergey Fedorov
When QEMU watchpoint matches, that is not definitely an architectural
watchpoint match yet. If it is a stop-before-access watchpoint then that
is hardly possible to ignore it after throwing a TCG exception.
A special callback is introduced to check for architectural watchpoi
On Tue, Feb 09, 2016 at 07:36:12PM +0100, Laszlo Ersek wrote:
> On 02/09/16 17:22, John Snow wrote:
> >
> >
> > On 02/09/2016 10:52 AM, Roman Kagan wrote:
> >> On Mon, Feb 08, 2016 at 03:20:47PM -0500, John Snow wrote:
> >>> On 02/08/2016 08:14 AM, Roman Kagan wrote:
> On Fri, Feb 05, 2016 a
From: Sergey Fedorov
ARM stops before access to a location covered by watchpoint. Also, QEMU
watchpoint fire is not necessarily an architectural watchpoint match.
Unfortunately, that is hardly possible to ignore a fired watchpoint in
debug exception handler. So move watchpoint check from debug ex
System registers might have access requirements which need to
be described via a CPAccessFn and which differ for reads and
writes. For this to be possible we need to pass the access
function a parameter to tell it whether the access being checked
is a read or a write.
Signed-off-by: Peter Maydell
Implement some corner cases of the behaviour of the NSACR
register on ARMv8:
* if EL3 is AArch64 then accessing the NSACR from Secure EL1
with AArch32 should trap to EL3
* if EL3 is not present or is AArch64 then reads from NS EL1 and
NS EL2 return constant 0xc00
It would in theory be poss
All Thumb Neon and VFP instructions are 32 bits, so the IL
bit in the syndrome register should be set. Pass false to the
syn_* function's is_16bit argument rather than s->thumb
so we report the correct IL bit.
Signed-off-by: Peter Maydell
Reviewed-by: Sergey Fedorov
Message-id: 1454683067-16001-
016-02-09' into
staging (2016-02-09 16:09:15 +)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20160209
for you to fetch changes up to dfe1da1c1271dff825676435ff90da92cf4f:
bcm2835_property: implement "get bo
From: Stephen Warren
Return a valid value from the BCM2835 property mailbox query "get board
revision". This query is used by U-Boot. Implementing it fixes the first
obvious difference between qemu and real HW.
The value returned is currently hard-coded to match the RPi2 I own. Other
values are
All Thumb coprocessor instructions are 32 bits, so the IL
bit in the syndrome register should be set. Pass false to the
syn_* function's is_16bit argument rather than s->thumb
so we report the correct IL bit.
Signed-off-by: Peter Maydell
Reviewed-by: Sergey Fedorov
Message-id: 1454683067-16001-3
From: Andrew Jones
mach-virt doesn't yet support hotplug, but command lines specifying
-smp ,maxcpus= don't fail. Of course specifying
bigger-num as something bigger than the machine supports, e.g. > 8
on a gicv2 machine, should fail though. This fix also makes mach-
virt's max-cpus check truly c
From: Prasad J Pandit
While processing standard SD commands, the 'req.cmd' value could
lead to OOB read when used as an index into 'sd_cmd_type' or
'sd_cmd_class' arrays. Limit 'req.cmd' value to avoid such an
access.
Reported-by: Qinghao Tang
Signed-off-by: Prasad J Pandit
Reviewed-by: Peter
Enable EL3 support for our Cortex-A53 and Cortex-A57 CPU models.
We have enough implemented now to be able to run real world code
at least to some extent (I can boot ARM Trusted Firmware to the
point where it pulls in OP-TEE and then falls over because it
doesn't have a UEFI image it can chain to).
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