Re: [Qemu-devel] reset strategy?

2015-06-27 Thread Liviu Ionescu
> On 27 Jun 2015, at 21:03, Peter Crosthwaite > wrote: > > Try this after object creation (see xlnx-zynqmp init fn): > >qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); ah, sure, I already tried this, if I set the bus, everything works as before. but probably my question was

[Qemu-devel] [PATCH] ich9: Fix naming confusion when referring to RCBA register

2015-06-27 Thread Paulo Alcantara
Looks like RCBA was confused by either RBCA (Receive Broadcast Packet, TSEC), or they were all just typos. This patch changes all incorrect namings from RBCA to RCBA. Signed-off-by: Paulo Alcantara --- hw/isa/lpc_ich9.c | 32 include/hw/i386/ich9.h | 2 +-

Re: [Qemu-devel] reset strategy?

2015-06-27 Thread Peter Crosthwaite
On Sat, Jun 27, 2015 at 1:19 AM, Liviu Ionescu wrote: > I migrated most of the qdev_* calls to object_* and device_* calls. > > however, after I switched from qdev_create() to object_new(), I noticed that > without the sysbus, there is no automated mechanism to reset the peripherals > attached t

[Qemu-devel] [PATCH v7 3/3] ich9: implement strap SPKR pin logic

2015-06-27 Thread Paulo Alcantara
If the signal is sampled high, this indicates that the system is strapped to the "No Reboot" mode (ICH9 will disable the TCO Timer system reboot feature). The status of this strap is readable via the NO_REBOOT bit (CC: offset 0x3410:bit 5). The NO_REBOOT bit is set when SPKR pin on ICH9 is sampled

[Qemu-devel] [PATCH v7 2/3] tests: add testcase for TCO watchdog emulation

2015-06-27 Thread Paulo Alcantara
This patch adds a testcase that covers the following: 1) TCO default values 2) first and second TCO timeout 3) watch and validate ticks counter through TCO_RLD register 4) maximum supported TCO timeout (0x3ff) 5) watchdog actions (pause/reset/shutdown/none) upon second TCO timeout

[Qemu-devel] [PATCH v7 1/3] ich9: add TCO interface emulation

2015-06-27 Thread Paulo Alcantara
This interface provides some registers within a 32-byte range and can be acessed through PCI-to-LPC bridge interface (PMBASE + 0x60). It's commonly used as a watchdog timer to detect system lockups through SMIs that are generated -- if TCO_EN bit is set -- on every timeout. If NO_REBOOT bit is not

[Qemu-devel] [Bug 1469342] [NEW] qemu-i386 pentium3 incorrect instruction set

2015-06-27 Thread PeteVine
Public bug reported: Running a binary containing a movsd instruction (SSE2) in 32-bit qemu-i386 -cpu pentium3 from 20150609 results in flawless execution whereas it should crash with SIGILL as P3 only had SSE. ** Affects: qemu Importance: Undecided Status: New -- You received this

[Qemu-devel] reset strategy?

2015-06-27 Thread Liviu Ionescu
I migrated most of the qdev_* calls to object_* and device_* calls. however, after I switched from qdev_create() to object_new(), I noticed that without the sysbus, there is no automated mechanism to reset the peripherals attached to the mcu. my solution was to manually propagate the reset to a