Public bug reported:
Using the instructions at
http://www.contrib.andrew.cmu.edu/~somlo/OSXKVM/ for running Mac OS X
Snow Leopard under QEMU, bridged networking is broken when using QEMU
git. The result is that Mac OS X is unable to obtain an IP address using
DHCP. It works in the latest stable re
On Thu, Jun 18, 2015 at 09:37:33PM +1000, Alexey Kardashevskiy wrote:
> sPAPR IOMMU is managing two copies of an TCE table:
> 1) a guest view of the table - this is what emulated devices use and
> this is where H_GET_TCE reads from;
> 2) a hardware TCE table - only present if there is at least one
On Thu, Jun 18, 2015 at 09:37:32PM +1000, Alexey Kardashevskiy wrote:
> sPAPRTCETable is handling 2 TCE tables already:
>
> 1) guest view of the TCE table - emulated devices use only this table;
>
> 2) hardware IOMMU table - VFIO PCI devices use it for actual work but
> it does not replace 1) and
On Thu, Jun 18, 2015 at 09:37:29PM +1000, Alexey Kardashevskiy wrote:
> sPAPRTCETable has a vfio_accel flag which is passed to
> kvmppc_create_spapr_tce() and controls whether to create a guest view
> table in KVM as this depends on the host kernel ability to accelerate
> H_PUT_TCE for VFIO devices
This patch adds 'backend_features' option for vhost-user backends.
If this option is specified, QEMU assumes vhost-user backends support
the features specified by user, and QEMU can start without vhost-user
backend.
Here are examples.
* QEMU is configured as vhost-user client.
-chardev socket,id=
The patch enables 'nowait' option for server mode, and 'reconnect'
option for client mode.
Signed-off-by: Tetsuya Mukawa
---
net/vhost-user.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/net/vhost-user.c b/net/vhost-user.c
index 8b7749a..58cd5dc 100644
--- a/net/vhost-user.c
+++ b/n
When wrong vhost-user message are passed, the connection should be shutdown.
Signed-off-by: Tetsuya Mukawa
---
hw/virtio/vhost-user.c | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/hw/virtio/vhost-user.c b/hw/virtio/vhost-user.c
index d6f2163..2215c39 100
The patch introduces qemu_chr_disconnect(). The function is used for
closing a fd accepted by listen fd. Though we already have qemu_chr_delete(),
but it closes not only accepted fd but also listen fd. This new function
is used when we still want to keep listen fd.
Signed-off-by: Tetsuya Mukawa
-
Hi guys,
Here are patches to add feature to start QEMU without vhost-user backend.
Currently, if we want to use vhost-user backend, the backend must start before
QEMU. Also, if QEMU or the backend is closed unexpectedly, there is no way to
recover without restarting both applications. Practically,
Current QEMU cannot detect vhost-user backend disconnection. The
patch adds ability to know it.
To know disconnection, add watcher to detect G_IO_HUP event. When
G_IO_HUP event is detected, the disconnected socket will be read
to cause a CHR_EVENT_CLOSED.
Signed-off-by: Tetsuya Mukawa
---
net/vh
On Thu, Jun 18, 2015 at 09:37:28PM +1000, Alexey Kardashevskiy wrote:
> Currently TCE tables are created once at start and their size never
> changes. We are going to change that by introducing a Dynamic DMA windows
> support where DMA configuration may change during the guest execution.
>
> This
On Thu, Jun 18, 2015 at 09:37:27PM +1000, Alexey Kardashevskiy wrote:
> At the moment presence of vfio-pci devices on a bus affect the way
> the guest view table is allocated. If there is no vfio-pci on a PHB
> and the host kernel supports KVM acceleration of H_PUT_TCE, a table
> is allocated in KV
On Fri, Jun 19, 2015 at 10:40:23AM +0530, Bharata B Rao wrote:
> Store memory address range information of boot memory in address
> range list of numa_info.
>
> This helps to have a common NUMA node lookup by address function that
> works for both boot time memory and hotplugged memory.
>
> Sign
On Thu, Jun 18, 2015 at 04:50:26PM +0530, Nikunj A Dadhania wrote:
> The patch series creates PCI device tree(DT) nodes in QEMU. The new
> hotplug code needs the device node creation in QEMU. While during
> boot, nodes were created in SLOF. It makes more sense to consolidate
> the code to one place
On Fri, Jun 19, 2015 at 08:49:00AM +0200, Markus Armbruster wrote:
> David Gibson writes:
>
> > On Thu, Jun 18, 2015 at 09:35:44PM +1000, Alexey Kardashevskiy wrote:
> >> On 05/05/2015 10:49 PM, David Gibson wrote:
> >> >On Sat, Apr 25, 2015 at 10:24:43PM +1000, Alexey Kardashevskiy wrote:
> >> >
This interface provides some registers within a 32-byte range and can be
acessed through PCI-to-LPC bridge interface (PMBASE + 0x60).
It's commonly used as a watchdog timer to detect system lockups through
SMIs that are generated -- if TCO_EN bit is set -- on every timeout. If
NO_REBOOT bit is not
This patch adds a testcase that covers the following:
1) TCO default values
2) first and second TCO timeout
3) watch and validate ticks counter through TCO_RLD register
4) maximum supported TCO timeout (0x3ff)
5) watchdog actions (pause/reset/shutdown/none) upon second TCO
timeout
This block is mapped into memory space, using the Root Complex Base
Address (RCBA) register of the PCI-to-LPC bridge. Accesses in this space
must be limited to 32-(DW) bit quantities. Burst accesses are not
allowed.
All Chipset Configuration Registers are located in this 16KiB space.
Signed-off-b
Hi Laurent,
On 20/06/15 05:35, Laurent Vivier wrote:
> Le 19/06/2015 15:43, g...@uclinux.org a écrit :
>> From: Greg Ungerer
>>
>> The action to potentially switch sp register is not occurring at the correct
>> point in the interrupt entry or exception exit sequences.
>>
>> For the interrupt entr
This patch adds all non-privileged instructions of the 680x0 family.
The FPU is not modified and we always use the ColdFire FPU emulation,
so some 680x0 FPU instructions are missing.
Signed-off-by: Laurent Vivier
---
cpu-exec.c |6 -
disas.c |4 +
target-m68k
Signed-off-by: Laurent Vivier
---
configure | 2 +-
fpu/softfloat-specialize.h | 48 ++-
fpu/softfloat.c| 38 +-
gdb-xml/m68k-fp.xml| 21 +
include/fpu/softfloat.h| 11 +-
target-m68k/cpu.c | 9 +
target-m68k/cpu.h | 38 +-
targe
I carry this series for several years now.
I was reluctant to merge it with the mainstream because
I was sure it was breaking Coldfire support.
But with the kernel provided by Greg Ungerer I was able
to check and correct the support of ColdFire family
in my tree.
This series allows:
- to start a
> On 21 Jun 2015, at 23:58, Peter Maydell wrote:
>
> There's lots of code that will run on QEMU but break on
> real hardware.
no doubt about it.
however, this shouldn't be the rule, if the efforts are reasonable, I see no
reasons for not improving the emulation quality and make code that brea
On 21 June 2015 at 15:42, Liviu Ionescu wrote:
>
>> On 21 Jun 2015, at 17:09, Peter Maydell wrote:
>>
>> Non-buggy guest code should not care whether
>> it is running on an r2p1 or an r2p0,
>
> probably not, but code developed on an emulated r2 might
> very well break on a physical r0.
There's l
On 2015-06-18 22:21, Eduardo Habkost wrote:
> On Sun, Jun 07, 2015 at 11:15:08AM +0200, Jan Kiszka wrote:
>> From: Jan Kiszka
>>
>> ARAT signals that the APIC timer does not stop in power saving states.
>> As our APICs are emulated, it's fine to expose this feature to guests,
>> at least when aski
A break is missing in the EXECUTE instruction, when executing the
TRANSLATE AND TEST instruction.
Reported-by: Paolo Bonzini
Signed-off-by: Aurelien Jarno
Cc: Alexander Graf
Cc: Richard Henderson
---
target-s390x/mem_helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-s390x/me
> On 21 Jun 2015, at 17:09, Peter Maydell wrote:
>
> Non-buggy guest code should not care whether
> it is running on an r2p1 or an r2p0,
probably not, but code developed on an emulated r2 might very well break on a
physical r0.
> I think these should probably be cpu object properties, ...
>
On 2015-06-20 23:06, Paolo Bonzini wrote:
>
>
> On 05/06/2015 01:41, Alexander Graf wrote:
> > From: Aurelien Jarno
> >
> > It is part of the basic zArchitecture instructions. Allow it to be call
> > from EXECUTE.
> >
> > Reviewed-by: Richard Henderson
> > Signed-off-by: Aurelien Jarno
> > S
On 21 June 2015 at 09:17, Liviu Ionescu wrote:
> while studying the details of cortex-m cores, I ran into the
> many differences between existing revisions, especially for
> cortex-m3, which are numerous and some significative, like
> stack alignment. for example for m3, the changes from r0p0 to
>
From: Alistair Francis
This code is already being run in the mb_cpu_realizefn()
function. As PVR registers are preserved on reset this
code is not required.
Signed-off-by: Alistair Francis
Reviewed-by: Edgar E. Iglesias
Reviewed-by: Peter Crosthwaite
Signed-off-by: Edgar E. Iglesias
---
tar
From: Alistair Francis
Move the hard coded register values to the init function.
This also allows the entire reset function to be deleted, as
PVR registers are now preserved on reset.
The hardcoded PVR0 values can be removed as they are setting
the endianness and stack protection, which is alrea
From: Alistair Francis
Remove the hardcoded values from the machine specific reset
function, as the same values are already set in the standard
MicroBlaze reset.
This also allows the entire reset function to be deleted, as
PVR registers are now preserved on reset.
Signed-off-by: Alistair Franci
From: Alistair Francis
Originally the pvr-full PVR bits were manually set for each machine. This
is a hassle and difficult to read, instead set them based on the CPU
properties.
Signed-off-by: Alistair Francis
Reviewed-by: Peter Crosthwaite
Signed-off-by: Edgar E. Iglesias
---
target-microbl
From: Alistair Francis
Originally the version_mask PVR bits were manually set for each
machine. This is a hassle and difficult to read, instead set them
based on the CPU properties.
Signed-off-by: Alistair Francis
Reviewed-by: Peter Crosthwaite
Signed-off-by: Edgar E. Iglesias
---
hw/microbl
From: Alistair Francis
Originally the endi PVR bits were manually set for each machine. This
is a hassle and difficult to read, instead set them based on the CPU
properties.
Signed-off-by: Alistair Francis
Reviewed-by: Edgar E. Iglesias
Reviewed-by: Peter Crosthwaite
Signed-off-by: Edgar E. I
From: Alistair Francis
Rename the usefpu variable to use_fpu.
Signed-off-by: Alistair Francis
Reviewed-by: Peter Crosthwaite
Signed-off-by: Edgar E. Iglesias
---
target-microblaze/cpu-qom.h | 2 +-
target-microblaze/cpu.c | 8
target-microblaze/translate.c | 6 +++---
3 file
From: Alistair Francis
Stack protection is not available when the MMU is enabled.
As the MMU is enabled by default, disable stack protection
by default.
Signed-off-by: Alistair Francis
Signed-off-by: Edgar E. Iglesias
---
target-microblaze/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 delet
From: Alistair Francis
Originally the use-fpu PVR bits were manually set for each machine. This
is a hassle and difficult to read, instead set them based on the CPU
properties.
Signed-off-by: Alistair Francis
Reviewed-by: Peter Crosthwaite
Signed-off-by: Edgar E. Iglesias
---
hw/microblaze/p
From: Alistair Francis
Rename the "xlnx.base-vectors" string to "base-vectors" and
move the base_vectors variable into the cfg struct.
Signed-off-by: Alistair Francis
Reviewed-by: Peter Crosthwaite
Signed-off-by: Edgar E. Iglesias
---
target-microblaze/cpu-qom.h | 3 ++-
target-microblaze/cp
From: Alistair Francis
Move the Microblaze PVR registers to the end of the CPUMBState
and preserve them during reset. This is similar to what the
QEMU ARM model does with some of it's registers.
This allows the Microblaze PVR registers to only be set once
at realise instead of constantly at rese
From: Alistair Francis
Fix up the incorrect indentation level in the helper_stackprot() function.
Signed-off-by: Alistair Francis
Reviewed-by: Peter Crosthwaite
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Edgar E. Iglesias
---
target-microblaze/op_helper.c | 10 +-
1 file changed,
From: Peter Crosthwaite
Instantiate and realise the CPU directly, rather than using
cpu_mb_init. Microblazes cpu_model argument is a dummy so remove the
default cpu_model set logic.
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Peter Crosthwaite
Signed-off-by: Edgar E. Iglesias
---
hw/microb
From: "Edgar E. Iglesias"
This is the stuff in my queue that I plan to merge soonish.
Cheers,
Edgar
Alistair Francis (15):
target-microblaze: Fix up indentation
target-microblaze: Preserve the pvr registers during reset
target-microblaze: Allow the stack protection to be disabled
target
On Thu, Jun 18, 2015 at 09:16:21PM -0700, Alistair Francis wrote:
> This patch series extends the MicroBlaze properties
> that I have been working on. It applies on top of my
> original work:
> 'Add Microblaze configuration options'.
>
> This patch series converts various MicroBlaze PVR registers
On Tue, Jun 09, 2015 at 06:40:48AM -0400, Stefan Berger wrote:
> > +
> > +if (misc->tpm_version != TPM_VERSION_UNSPEC) {
> > +dev = aml_device("ISA.TPM");
> > +aml_append(dev, aml_name_decl("_HID",
> > aml_eisaid("PNP0C31")));
> > +
On Tue, Jun 09, 2015 at 11:26:18AM +0800, Shannon Zhao wrote:
> From: Shannon Zhao
>
> The table revision is not the ACPI spec version. Fix the wrong revision
> and also some comments.
>
> Signed-off-by: Shannon Zhao
Reviewed-by: Michael S. Tsirkin
> ---
> hw/arm/virt-acpi-build.c | 11
On Sun, 21 Jun 2015 11:20:18 +0300, marcel.apfelb...@gmail.com wrote:
> Thank you for the patch, you are completely right.
> My 'Reviewed-by' tag is there, I think Michael, the PCI
> maintainer, will take it shortly.
Was already pulled ;-)
On 06/17/2015 10:17 PM, Shmulik Ladkani wrote:
Hi,
On Wed, 17 Jun 2015 12:37:18 +0300, marcel.apfelb...@gmail.com wrote:
BTW, did you notice a bug here? If yes, can you elaborate?
No, not a direct bug.
We noticed this while working on related code areas.
There's some history behind this.
I
while studying the details of cortex-m cores, I ran into the many differences
between existing revisions, especially for cortex-m3, which are numerous and
some significative, like stack alignment. for example for m3, the changes from
r0p0 to r1p0/r1p1 are one full page of details, like "
On 06/17/2015 09:46 PM, Shmulik Ladkani wrote:
Hi,
On Wed, 17 Jun 2015 12:36:14 +0300, marcel.apfelb...@gmail.com wrote:
NOTE:
Not sure if my statement regarding ommitting 'config_write' holds
for the megasas case:
It's parent is TYPE_MEGASAS_BASE whose parent is TYPE_PCI_DEVICE.
Can we assume
If neither explicit semihosting args nor -kernel are used,
make SYS_GET_CMDLINE return an empty string.
Signed-off-by: Liviu Ionescu
---
target-arm/arm-semi.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/target-arm/arm-semi.c b/target-arm/arm-semi.c
index 74a6
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