Because of the trick of process-archive-undefs, all .mo objects, even
with --enable-modules, are dependencies of executables.
This breaks CFLAGS propogation because the compiling of module object
will happen too early before building for DSO.
With GCC 5, the linking would fail because .o doesn't
> On 06 May 2015, at 17:57, Leon Alrae wrote:
>
> +static int add_semihosting_arg(const char *name, const char *val, void
> *opaque)
> +{
> +SemihostingConfig *s = opaque;
> +if (strcmp(name, "arg") == 0) {
> +s->argc++;
> +s->argv = g_realloc(s->argv, s->argc * sizeof(v
> From: Paolo Bonzini [mailto:pbonz...@redhat.com]
> On 06/05/2015 16:04, Pavel Dovgalyuk wrote:
> > This patch introduces aio_bh_call function. It is used to execute
> > bottom halves as callbacks without adding them to the queue.
> >
> > Signed-off-by: Pavel Dovgalyuk
> > ---
> > async.c
07.05.2015 09:12, Michael Tokarev wrote:
> 07.05.2015 04:11, G 3 wrote:
>> Did you boot Windows XP to the desktop? I have tested Windows 95, Windows
>> 2000, and Windows XP. All of them fail to boot to the desktop.
>
> Yes, booted to desktop and did some minimal work in there,
> installnig one up
Hello!
Why do we need 'virt2' ? I am currently working on testing your
implementation, and i try to use different approach. I see this as '-machine
virt,gicv=N' option, where N is 2 or 3. Isn't it better than duplicating the
whole virt.c code just for single different function ?
Kind regards,
P
If live migration is very fast and can be completed in 1 second,
the dirty_sync_count of MigrationState will not be updated.
Then you will see "dirty sync count: 0" in qemu monitor even if
the actual dirty sync count is not 0.
Signed-off-by: Liang Li
---
arch_init.c | 2 +-
1 file changed, 1 ins
Hello!
> Yes. qemu-system-aarch64 -cpu cortex-a15 gets you a 32-bit Cortex-A15. This is
> exactly like the x86 QEMU, where you can emulate all the 32-bit x86 CPUs in
> qemu-system-x86_64.
And what is the default in x86_64 ? I believe it's 64-bit CPU, and not i686,
isn't it ?
I agree that -cpu
John Snow writes:
> On 05/06/2015 11:19 AM, Markus Armbruster wrote:
>> John Snow writes:
>>
>>> On 05/06/2015 02:25 AM, Markus Armbruster wrote:
John Snow writes:
> Instead of letting printf and friends do this for us
> one byte at a time, fill a buffer ourselves and then
>>
07.05.2015 04:11, G 3 wrote:
> Did you boot Windows XP to the desktop? I have tested Windows 95, Windows
> 2000, and Windows XP. All of them fail to boot to the desktop.
Yes, booted to desktop and did some minimal work in there,
installnig one update or two.
> Command used:
> ./i386-softmmu/qemu
Fam Zheng writes:
> On Wed, 05/06 10:50, Luiz Capitulino wrote:
>> Markus is taking over maintership of QMP and the QAPI from
>> me. Markus has always been a great reviewer and contributor
>> to those subsystems. In the last few months he's also doing
>> pull requests that are a lot more relevant
From: Nathan Fontenot
This extends the data structures currently used to report EPOW events to
guests via the check-exception RTAS interfaces to also include event types
for hotplug/unplug events.
This is currently undocumented and being finalized for inclusion in PAPR
specification, but we impl
From: Nikunj A Dadhania
Machines types can have different requirement for default ram
size. Introduce a member in the machine class and set the current
default_ram_size to 128MB.
For QEMUMachine types override the value during the registration of
the machine and for MachineClass introduce the ge
From: Michael Roth
This interface is used to fetch an OF device-tree nodes that describes a
newly-attached device to guest. It is called multiple times to walk the
device-tree node and fetch individual properties into a 'workarea'/buffer
provided by the guest.
The device-tree is generated by QEM
From: Michael Roth
This device emulates a firmware abstraction used by pSeries guests to
manage hotplug/dynamic-reconfiguration of host-bridges, PCI devices,
memory, and CPUs. It is conceptually similar to an SHPC device,
complete with LED indicators to identify individual slots to physical
physi
From: Michael Roth
These will be used to support hotplug/unplug of PCI devices to the PCI
bus associated with a particular PHB.
We also set up device-tree properties in each PHBs initial FDT to
describe the DRCs associated with them. This advertises to guests that
each PHB is DR-capable device w
From: Michael Roth
This enables hotplug of PCI devices to a PHB. Upon hotplug we
generate the OF-nodes required by PAPR specification and
IEEE 1275-1994 "PCI Bus Binding to Open Firmware" for the
device.
We associate the corresponding FDT for these nodes with the DRC
corresponding to the slot, w
qemu currently implements the hypercalls H_LOGICAL_CI_LOAD and
H_LOGICAL_CI_STORE as PAPR extensions. These are used by the SLOF firmware
for IO, because performing cache inhibited MMIO accesses with the MMU off
(real mode) is very awkward on POWER.
This approach breaks when SLOF needs to access
From: Michael Roth
This option enables/disables PCI hotplug for a particular PHB.
Also add machine compatibility code to disable it by default for machine
types prior to pseries-2.4.
Signed-off-by: Michael Roth
Reviewed-by: David Gibson
Signed-off-by: David Gibson
---
hw/ppc/spapr.c
From: Mike Day
This interface allows a guest to control various platform/device
sensors. Initially, we only implement support necessary to control
sensors that are required for hotplug: DR connector indicators/LEDs,
resource allocation state, and resource isolation state.
See docs/specs/ppc-spap
From: Mike Day
This interface allows a guest to read various platform/device sensors.
initially, we only implement support necessary to support hotplug:
reading of the dr-entity-sense sensor, which communicates the state of
a hotplugged resource/device to the guest (EMPTY/PRESENT/UNUSABLE).
See
From: Tyrel Datwyler
We don't actually rely on this interface to surface hotplug events, and
instead rely on the similar-but-interrupt-driven check-exception RTAS
interface used for EPOW events. However, the existence of this interface
is needed to ensure guest kernels initialize the event-report
From: Nikunj A Dadhania
Signed-off-by: Nikunj A Dadhania
Reviewed-by: Igor Mammedov
Reviewed-by: Thomas Huth
Acked-by: David Gibson
Signed-off-by: David Gibson
---
hw/ppc/spapr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index f9fa53a..740b10f 10064
From: Michael Roth
We need to work with PCI BARs to generate OF properties
during PCI hotplug for sPAPR guests.
Signed-off-by: Michael Roth
Reviewed-by: David Gibson
Acked-by: Michael S. Tsirkin
Signed-off-by: David Gibson
---
hw/pci/pci.c | 2 +-
include/hw/pci/pci.h | 6 ++
2
From: Thomas Huth
The check "liobn & 0xULL" in spapr_tce_find_by_liobn()
is completely useless since liobn is only declared as an uint32_t
parameter. Fix this by using target_ulong instead (this is what most
of the callers of this function are using, too).
Signed-off-by: Thomas H
From: Tyrel Datwyler
This uses extension of existing EPOW interrupt/event mechanism
to notify userspace tools like librtas/drmgr to handle
in-guest configuration/cleanup operations in response to
device_add/device_del.
Userspace tools that don't implement this extension will need
to be run manua
From: Michael Roth
This function handles generation of ibm,drc-* array device tree
properties to describe DRC topology to guests. This will by used
by the guest to direct RTAS calls to manage any dynamic resources
we associate with a particular DR Connector as part of
hotplug/unplug.
Since gener
From: Michael Roth
This adds a general overview of hotplug/dynamic-reconfiguration
for sPAPR/pSeries guest.
As specified in PAPR+ v2.7.
Signed-off-by: Michael Roth
Reviewed-by: David Gibson
Signed-off-by: David Gibson
---
docs/specs/ppc-spapr-hotplug.txt | 287 ++
From: Michael Roth
This is similar to the existing rtas_st_buffer(), but for cases
where the guest is not expecting a length-encoded byte array.
Namely, for calls where a "work area" buffer is used to pass
around arbitrary fields/data.
Signed-off-by: Michael Roth
Reviewed-by: David Gibson
Sign
From: Alexey Kardashevskiy
Useful for debugging.
Signed-off-by: Alexey Kardashevskiy
Signed-off-by: David Gibson
---
hw/ppc/spapr_iommu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/spapr_iommu.c b/hw/ppc/spapr_iommu.c
index c17e831..a14cdc4 100644
--- a/hw/p
From: Thomas Huth
hw_error() is designed for printing CPU-related error messages
(e.g. it also prints a full CPU register dump). For error messages
that are not directly related to CPU problems, a function like
error_report() should be used instead.
Signed-off-by: Thomas Huth
Signed-off-by: Dav
From: Nathan Fontenot
These interfaces manage the power domains that guest devices are
assigned to and are used to power on/off devices. Currently we
only utilize 1 power domain, the 'live-insertion' domain, which
automates power management of plugged/unplugged devices, essentially
making these c
From: Alexey Kardashevskiy
This makes find_phb()/find_dev() public and changed its names
to spapr_pci_find_phb()/spapr_pci_find_dev() as they are going to
be used from other parts of QEMU such as VFIO DDW (dynamic DMA window)
or VFIO PCI error injection or VFIO EEH handling - in all these
cases t
From: Thomas Huth
When specifying a non-existing file with the "-bios" parameter, QEMU
complained that it "could not find LPAR rtas". That's obviously a
copy-n-paste bug from the code which loads the spapr-rtas.bin, it
should complain about a missing firmware file instead.
Additionally the error
From: Alexey Kardashevskiy
At the moment spapr_tce_find_by_liobn() is used by H_PUT_TCE/...
handlers to find an IOMMU by LIOBN.
We are going to implement Dynamic DMA windows (DDW), new code
will go to a new file and we will use spapr_tce_find_by_liobn()
there too so let's make it public.
Signed
Now that 2.4 development has opened, create a new pseries machine type
variant. For now it is identical to the pseries-2.3 machine type, but
a number of new features are coming that will need to set backwards
compatibility options.
Signed-off-by: David Gibson
---
hw/ppc/spapr.c | 24 +++
From: Alexey Kardashevskiy
This replaces object_child_foreach() and callback with existing
SPAPR_PCI_LIOBN() and spapr_tce_find_by_liobn() to make the code easier
to read.
This is a mechanical patch so no behaviour change is expected.
Signed-off-by: Alexey Kardashevskiy
Signed-off-by: David Gi
Hi Alex (et al),
Here's my current batch of -machine pseries related patches which I
think are ready to merge. Sorry this is a resend pretty close after
the last batch I sent out - I wanted to make sure I sent out the queue
because I'm going to be on vacation for the next two weeks.
This series
From: Alexey Kardashevskiy
This gets rid of a magic constant describing the default DMA window size
for an emulated PHB.
Signed-off-by: Alexey Kardashevskiy
Signed-off-by: David Gibson
---
hw/ppc/spapr_pci.c | 6 +++---
include/hw/pci-host/spapr.h | 2 ++
2 files changed, 5 insertion
From: Alexey Kardashevskiy
We are going to have multiple DMA windows per PHB and we want them to
migrate so we need a predictable way of assigning LIOBNs.
This introduces a macro which makes up a LIOBN from fixed prefix,
PHB index (unique PHB id) and window number.
This introduces a SPAPR_PCI_D
From: Alexey Kardashevskiy
This is to reduce VIO noise while debugging PCI DMA.
Signed-off-by: Alexey Kardashevskiy
Signed-off-by: David Gibson
---
hw/ppc/spapr_iommu.c | 27 ---
include/hw/ppc/spapr.h | 1 +
trace-events | 4
3 files changed, 25 ins
spapr_pci.c contains a number of expressions of the form (uval == -1) or
(uval != -1), where 'uval' is an unsigned value.
This mostly works in practice, because as long as the width of uval is
greater or equal than that of (int), the -1 will be promoted to the
unsigned type, which is the expected
From: Alexey Kardashevskiy
The existing KVM_CREATE_SPAPR_TCE ioctl only support 4G windows max as
the window size parameter to the kernel ioctl() is 32-bit so
there's no way of expressing a TCE window > 4GB.
We are going to add huge DMA windows support so this will create small
window and unexpe
From: Alexey Kardashevskiy
PAPR is defined as big endian so TCEs need an adjustment so
does this patch.
This changes code to have ldq_be_phys() in one place.
Signed-off-by: Alexey Kardashevskiy
Reviewed-by: David Gibson
Signed-off-by: David Gibson
---
hw/ppc/spapr_iommu.c | 7 +++
1 fil
From: Alexey Kardashevskiy
This introduces a macro which makes up a LIOBN from fixed prefix and
VIO device address (@reg property).
This is to keep LIOBN macros rendering consistent - the same macro for
PCI has been added by the previous patch.
Signed-off-by: Alexey Kardashevskiy
Reviewed-by:
On Thu, May 07, 2015 at 11:12:36AM +1000, David Gibson wrote:
> On Wed, May 06, 2015 at 01:53:05PM +0530, Bharata B Rao wrote:
> > On Tue, May 05, 2015 at 10:48:50AM +0200, Igor Mammedov wrote:
> > > On Fri, 24 Apr 2015 12:17:43 +0530
> > > Bharata B Rao wrote:
> > >
> > > > Initialize a hotplug
David Gibson writes:
> On Wed, May 06, 2015 at 11:44:59AM +0530, Nikunj A Dadhania wrote:
>> Thomas Huth writes:
>>
>> > On Tue, 5 May 2015 14:23:56 +0530
>> > Nikunj A Dadhania wrote:
>> >
>> >> Each hardware instance has a platform unique location code. The OF
>> >> device tree that descri
David Gibson writes:
> On Wed, May 06, 2015 at 11:11:05AM +0530, Nikunj A Dadhania wrote:
>> Thomas Huth writes:
>>
>> > On Tue, 5 May 2015 14:23:51 +0530
>> > Nikunj A Dadhania wrote:
>> >
>> >> Signed-off-by: Nikunj A Dadhania
>> >> ---
>> >> hw/ppc/spapr_pci.c | 11 ---
>> >> 1 f
On Thu, May 07, 2015 at 02:12:58PM +1000, Alexey Kardashevskiy wrote:
> On 05/07/2015 01:57 PM, David Gibson wrote:
> >The ram_limit field was imported from sPAPREnvironment where it predates
> >the machine's ram size being available generically from machine->ram_size.
> >
> >Signed-off-by: David G
On Thu, May 07, 2015 at 01:57:03PM +1000, David Gibson wrote:
> The sPAPRMachineState structure includes an entry_point field containing
> the initial PC value for starting the machine, even though this always has
> the value 0x100.
>
> I think this is a hangover from very early versions which byp
On 05/07/2015 01:57 PM, David Gibson wrote:
The ram_limit field was imported from sPAPREnvironment where it predates
the machine's ram size being available generically from machine->ram_size.
Signed-off-by: David Gibson
---
hw/ppc/spapr.c | 3 +--
hw/ppc/spapr_hcall.c | 3 ++-
inc
From: phoeagon
In reference to
b0ad5a455d7e5352d4c86ba945112011dbeadfb8~078a458e077d6b0db262c4b05fee51d01de2d1d2,
metadata writes to qcow2/cow/qcow/vpc/vmdk are all synced prior to succeeding
writes.
Only when write is successful that bdrv_flush is called.
Signed-off-by: Zhe Qiu
---
block/
The code for -machine pseries maintains a global sPAPREnvironment structure
which keeps track of general state information about the guest platform.
This predates the existence of the MachineState structure, but performs
basically the same function.
Now that we have the generic MachineState, fold
The sPAPRMachineState structure includes an entry_point field containing
the initial PC value for starting the machine, even though this always has
the value 0x100.
I think this is a hangover from very early versions which bypassed the
firmware when using -kernel. In any case it has no function n
Currently although we have an sPAPRMachineState descended from MachineState
we don't have an sPAPRMAchineClass descended from MachineClass. So far it
hasn't been needed, but several upcoming features are going to want it,
so this patch creates a stub implementation.
Signed-off-by: Michael Roth
S
This series makes some cleanups to the structures tracking overall
machine state for spapr (-machine pseries). First the old
sPAPREnvironment structure (which predates the generic MachineState
structure) is merged into a spapr specific subclass of MachineState.
Then some obsolete fields are cleane
The ram_limit field was imported from sPAPREnvironment where it predates
the machine's ram size being available generically from machine->ram_size.
Signed-off-by: David Gibson
---
hw/ppc/spapr.c | 3 +--
hw/ppc/spapr_hcall.c | 3 ++-
include/hw/ppc/spapr.h | 1 -
3 files changed, 3 ins
On Wed, 05/06 10:50, Luiz Capitulino wrote:
> Markus is taking over maintership of QMP and the QAPI from
> me. Markus has always been a great reviewer and contributor
> to those subsystems. In the last few months he's also doing
> pull requests that are a lot more relevant than the ones I
> was abl
On 05/02/2015 12:47 AM, John Snow wrote:
>
>
> On 04/03/2015 07:05 AM, Paolo Bonzini wrote:
>>
>>
>> On 03/04/2015 12:01, Wen Congyang wrote:
>>> Signed-off-by: Wen Congyang
>>> Signed-off-by: zhanghailiang
>>> Signed-off-by: Gonglei
>>> ---
>>> include/qemu/hbitmap.h | 8
>>> tes
On Wed, May 06, 2015 at 01:25:55PM +0530, Bharata B Rao wrote:
> On Tue, May 05, 2015 at 05:28:38PM +1000, David Gibson wrote:
> > On Fri, Apr 24, 2015 at 12:17:42PM +0530, Bharata B Rao wrote:
> > > Support hot removal of CPU for sPAPR guests by sending the hot unplug
> > > notification to the gue
On Wed, May 06, 2015 at 11:12:00AM +0530, Bharata B Rao wrote:
> On Tue, May 05, 2015 at 05:22:52PM +1000, David Gibson wrote:
> > On Fri, Apr 24, 2015 at 12:17:40PM +0530, Bharata B Rao wrote:
> > > When supporting CPU hot removal by parking the vCPU fd and reusing
> > > it during hotplug again, t
On Wed, May 06, 2015 at 01:57:50PM +0530, Bharata B Rao wrote:
> On Tue, May 05, 2015 at 05:40:32PM +1000, David Gibson wrote:
> > On Fri, Apr 24, 2015 at 12:17:45PM +0530, Bharata B Rao wrote:
> > > Parse ibm,architecture.vec table obtained from the guest and enable
> > > memory node configuration
On Wed, May 06, 2015 at 11:44:20AM +0530, Bharata B Rao wrote:
> On Tue, May 05, 2015 at 04:59:51PM +1000, David Gibson wrote:
> > On Fri, Apr 24, 2015 at 12:17:34PM +0530, Bharata B Rao wrote:
> > > Support CPU hotplug via device-add command. Set up device tree
> > > entries for the hotplugged CPU
On Wed, May 06, 2015 at 12:07:57PM +0530, Bharata B Rao wrote:
> On Tue, May 05, 2015 at 05:20:04PM +1000, David Gibson wrote:
> > On Fri, Apr 24, 2015 at 12:17:39PM +0530, Bharata B Rao wrote:
> > > From: Gu Zheng
> > >
> > > In order to deal well with the kvm vcpus (which can not be removed
>
On Wed, May 06, 2015 at 01:53:05PM +0530, Bharata B Rao wrote:
> On Tue, May 05, 2015 at 10:48:50AM +0200, Igor Mammedov wrote:
> > On Fri, 24 Apr 2015 12:17:43 +0530
> > Bharata B Rao wrote:
> >
> > > Initialize a hotplug memory region under which all the hotplugged
> > > memory is accommodated.
> > > > Thanks Dave, I will retry according to your suggestion.
> > >
> > > Did that work for you?
> > >
> >
> > Yes, it works.
>
> Great.
>
> > Bye the way, I found that the source guest will resume after about 15
> > minuets if there are some network errors happened during post copy. Is it
> th
Did you boot Windows XP to the desktop? I have tested Windows 95, Windows
2000, and Windows XP. All of them fail to boot to the desktop.
Command used:
./i386-softmmu/qemu-system-i386 -boot c -hda "Windows XP Hard Drive.img"
On Wed, May 6, 2015 at 2:44 PM, Programmingkid
wrote:
>
> On May 6, 201
On Wed, May 06, 2015 at 11:11:05AM +0530, Nikunj A Dadhania wrote:
> Thomas Huth writes:
>
> > On Tue, 5 May 2015 14:23:51 +0530
> > Nikunj A Dadhania wrote:
> >
> >> Signed-off-by: Nikunj A Dadhania
> >> ---
> >> hw/ppc/spapr_pci.c | 11 ---
> >> 1 file changed, 11 deletions(-)
> >>
On Wed, May 06, 2015 at 11:44:59AM +0530, Nikunj A Dadhania wrote:
> Thomas Huth writes:
>
> > On Tue, 5 May 2015 14:23:56 +0530
> > Nikunj A Dadhania wrote:
> >
> >> Each hardware instance has a platform unique location code. The OF
> >> device tree that describes a part of a hardware entity
There are 2x Cadence UARTs in Zynq MP. Add them.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Tested-by: Alistair Francis
Signed-off-by: Peter Crosthwaite
---
Changed since v4:
Remove ERR_PROP_CHECK_RETURN usage.
Changed since v1:
Fixed "UARTSs" typo
hw/arm/xlnx-zynqmp.c
On 06.05.15 15:46, Fam Zheng wrote:
> Because of the trick of process-archive-undefs, all .mo objects, even
> with --enable-modules, are dependencies of executables.
>
> This breaks CFLAGS propogation because the compiling of module object
> will happen too early before building for DSO.
>
> Wi
Cleanup some variable names in preparation for migrating the state
struct and type cast macro to a public header. The acronym "GEM" on
its own is not specific enough to be used in a more global namespace
so preface with "cadence". Fix the capitalisation of "gem" in the
state type while touching the
Zynq MPSoC supports external DDR RAM. Add a RAM at 0 to the model.
Reviewed-by: Alistair Francis
Tested-by: Alistair Francis
Signed-off-by: Peter Crosthwaite
---
changed since v4:
Use memory_region_allocate_system_memory
Change too-small warning to be qemu_log
changed since v1:
Add ram size cla
Add the GIC and connect IRQ outputs to the CPUs. The GIC regions are
under-decoded through a 64k address region so implement aliases
accordingly.
Signed-off-by: Peter Crosthwaite
---
changed since v6:
Added aliases.
changed since v5:
Make commit msg body standalone
Add reset-cbar configuration
Clean up some variable names in preparation for migrating the state struct
and type cast macro to a public header. The acronym "UART" on it's own is
not specific enough to be used in a more global namespace so preface with
"cadence". Fix the capitalisation of "uart" in the state type while touching
Rename some A57 CP register variables in preparation for support for
Cortex A53. Use "a57_a53" to describe the shareable features. Some of
the CP15 registers (such as ACTLR) are specific to implementation, but
we currently just RAZ them so continue with that as the policy for both
A57 and A53 proce
With quad Cortex-A53 CPUs.
Use SMC PSCI, with the standard policy of secondaries starting in
power-off.
Tested-by: Alistair Francis
Reviewed-by: Alistair Francis
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Peter Crosthwaite
---
changed since v4 (PMM review):
Squashed in PSCI stuffs.
Add (c)
Add a machine model for the Xilinx ZynqMP SoC EP108 board.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Reviewed-by: Edgar E. Iglesias
Tested-by: Alistair Francis
Signed-off-by: Peter Crosthwaite
---
Chaned since v1:
Change board name to ep108
hw/arm/Makefile.objs | 2 +-
hw/ar
There are 4x Cadence GEMs in ZynqMP. Add them.
Reviewed-by: Peter Maydell
Tested-by: Alistair Francis
Signed-off-by: Peter Crosthwaite
---
changed since v4:
Remove use of ERR_PROP_CHECK_RETURN
hw/arm/xlnx-zynqmp.c | 35 +++
include/hw/arm/xlnx-zynqmp.h
GIC generally uses a 4k memory region for the various subregions, such
as GICC, GICD, GICV and GICH. Macroify this number in the publicly
visible header.
Some machine model code may need to know the individual subregion size
to implement special addresses mappings (such as aliases and
under-decodi
Add the ARM cortex A53 processor definition. Similar to A57, but with
different L1 I cache policy, phys addr size and different cache
geometries. The cache sizes is implementation configurable, but use
these values (from Xilinx Zynq MPSoC) as a default until cache size
configurability is added.
Ac
Create a new header for Cadence UART to allow using the device with
modern SoC programming conventions. The state struct needs to be
visible to embed the device in SoC containers.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Reviewed-by: Edgar E. Iglesias
Tested-by: Alistair Francis
Create a new header for Cadence GEM to allow using the device with
modern SoC programming conventions. The state struct needs to be
visible to embed the device in SoC containers.
Reviewed-by: Alistair Francis
Reviewed-by: Peter Maydell
Reviewed-by: Edgar E. Iglesias
Tested-by: Alistair Francis
Connect the GPIO outputs from the individual CPUs for the timers to the
GIC.
Tested-by: Alistair Francis
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Peter Crosthwaite
---
changed since v4:
Use macro for GIC_INTERNAL
hw/arm/xlnx-zynqmp.c | 17 +
1 file changed, 17 insertions(
Add bootloader support using standard ARM bootloader.
Reviewed-by: Alistair Francis
Tested-by: Alistair Francis
Signed-off-by: Peter Crosthwaite
---
changed since v4:
Add loader_start field
Make commit message body standalone.
hw/arm/xlnx-ep108.c | 9 +
1 file changed, 9 insertions(+)
Hi Peter and all,
Xilinx's next gen SoC has been announced. This series adds a SoC and
board.
Series start with addition of ARM cortex A53 support (P1 and P2). The
Soc skeleton is then added with GIC, EMACs and UARTs added. The
pre-existing models for GEM and UART are not SoC friendly (no visible
On Mon, May 4, 2015 at 8:16 PM, Edgar E. Iglesias
wrote:
> On Fri, Apr 24, 2015 at 01:28:42PM -0700, Peter Crosthwaite wrote:
>> Add the GIC and connect IRQ outputs to the CPUs.
>
> This will not work with device-trees that place the GICC maps at the
> top of the 64K (due to the 64K address swizzl
On 6 May 2015 at 22:41, Programmingkid wrote:
> I did what you did "qemu-system-i386 -soundhw pcspk" and QEMU froze
> on me with this as the last thing printed on the screen: "Press Ctrl-B
> for the iPXE command line...".
Hmm. Mine definitely gets further than that -- it goes up to
"No bootable d
We store all struct types in an array of static size without ever
checking whether we overrun it. Of course some day someone (like me
in another, ancient ALSA enabling patch set) will run into the limit
without realizing it.
So let's make the allocation dynamic. We already know the number of
struc
On May 6, 2015, at 5:31 PM, Peter Maydell wrote:
> On 6 May 2015 at 22:19, Programmingkid wrote:
>>
>> On May 6, 2015, at 5:10 PM, Peter Maydell wrote:
Thread 8 (process 29237):
#0 tb_jmp_cache_hash_func (pc=1) at exec/exec-all.h:208
#1 0x0001c9d7 in tb_find_slow (env=0
On 6 May 2015 at 22:19, Programmingkid wrote:
>
> On May 6, 2015, at 5:10 PM, Peter Maydell wrote:
>>> Thread 8 (process 29237):
>>> #0 tb_jmp_cache_hash_func (pc=1) at exec/exec-all.h:208
>>> #1 0x0001c9d7 in tb_find_slow (env=0x103846620, pc=133133655,
>>> cs_base=133118944, flags=244
Here is the back trace of qemu-system-i386 after it has frozen. This time I
used cocoa and coreaudio.
Configuration commands: --target-list=ppc-softmmu,i386-softmmu
--disable-sdl --disable-gtk --enable-debug
Run commands: qemu-system-i386 -cdrom
-soundhw pcs
You're right, clearly that was a c/p fail. I can't for the life of me
find the bug that I was trying to refer to :(
** Description changed:
I'm running openstack 2012.1 'icehouse' which, ultimately, calls down
into qemu-system-x86 2.0.0+dfsg-2ubuntu1.10.
I primed the process by copying
On May 6, 2015, at 5:10 PM, Peter Maydell wrote:
> On 6 May 2015 at 20:41, Programmingkid wrote:
>>
>> On May 6, 2015, at 1:00 PM, Peter Maydell wrote:
>>
>>> On 6 May 2015 at 17:40, Programmingkid wrote:
(gdb) bt
#0 0x7fff824e2db6 in semaphore_wait_trap ()
#1 0x7fff8
On 6 May 2015 at 20:41, Programmingkid wrote:
>
> On May 6, 2015, at 1:00 PM, Peter Maydell wrote:
>
>> On 6 May 2015 at 17:40, Programmingkid wrote:
>>> (gdb) bt
>>> #0 0x7fff824e2db6 in semaphore_wait_trap ()
>>> #1 0x7fff824e8417 in pthread_mutex_lock ()
>>> #2 0x000100267199 in
On May 6, 2015, at 1:00 PM, Peter Maydell wrote:
> On 6 May 2015 at 17:40, Programmingkid wrote:
>> (gdb) bt
>> #0 0x7fff824e2db6 in semaphore_wait_trap ()
>> #1 0x7fff824e8417 in pthread_mutex_lock ()
>> #2 0x000100267199 in qemu_mutex_lock (mutex=> unavailable, due to optimizati
On 05/06/2015 12:37 PM, Peter Maydell wrote:
> On 6 May 2015 at 18:49, Juan Quintela wrote:
>> Hi
>>
>
> Fails to build on 32 bit, I'm afraid:
>
> /root/qemu/arch_init.c: In function ‘do_data_decompress’:
> /root/qemu/arch_init.c:1486:28: error: passing argument 2 of
> ‘uncompress’ from incompa
On 05/06/2015 11:50 AM, Juan Quintela wrote:
> From: Liang Li
>
> Add the qmp commands to tune and query the parameters used in live
> migration.
>
> Signed-off-by: Liang Li
> Signed-off-by: Yang Zhang
> Signed-off-by: Juan Quintela
> ---
> migration/migration.c | 56
On 05/06/2015 11:50 AM, Juan Quintela wrote:
> From: Liang Li
>
> Put the three parameters related to multiple thread (de)compression
> into an int array, and use an enum type to index the parameter.
>
> Signed-off-by: Liang Li
> Signed-off-by: Yang Zhang
> Signed-off-by: Juan Quintela
> ---
On 05/06/2015 11:50 AM, Juan Quintela wrote:
> From: Liang Li
>
> The multiple compression threads can be turned on/off through
> qmp and hmp interface before doing live migration.
>
> Signed-off-by: Liang Li
> Signed-off-by: Yang Zhang
> Reviewed-by: Dr.David Alan Gilbert
> Reviewed-by: Eric
On 6 May 2015 at 19:41, 浩倫 魏 wrote:
> So am I in the right path if I want to know how QEMU translates GVA to GPA?
> I have question about that if guest OS would take part in the translation
> between GCA to GPA? Or qemu-softmmu would take control everything?
Well, the guest OS is what sets up the
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