On Sun, Apr 26, 2015 at 4:35 AM, Peter Crosthwaite
wrote:
> On Sat, Apr 25, 2015 at 1:18 AM, Alistair Francis
> wrote:
>> If correctly configured allow the STM32F2xx timer to print
>> out the PWM duty cycle information.
>>
>> Signed-off-by: Alistair Francis
>> ---
>>
>> hw/timer/stm32f2xx_time
On Sun, Apr 26, 2015 at 4:32 AM, Peter Crosthwaite
wrote:
> "devices"
>
> On Sat, Apr 25, 2015 at 1:18 AM, Alistair Francis
> wrote:
>> Connect the ADC device to the STM32F205 SoC.
>>
>
> "devices"
Will fix both.
>
>> Signed-off-by: Alistair Francis
>> ---
>>
>> hw/arm/stm32f205_soc.c
On Sun, Apr 26, 2015 at 4:34 AM, Peter Crosthwaite
wrote:
> On Sat, Apr 25, 2015 at 1:18 AM, Alistair Francis
> wrote:
>> Cleanup the individual DeviceState and SysBusDevice
>> variables to re-use the same variable for each
>> device.
>>
>> Signed-off-by: Alistair Francis
>
> Reviewed-by: Peter
On Sun, Apr 26, 2015 at 4:31 AM, Peter Crosthwaite
wrote:
> On Sat, Apr 25, 2015 at 1:19 AM, Alistair Francis
> wrote:
>> Add Alistair Francis as the maintainer for the Netduino 2
>> and SMM32F205 SoC.
>>
>> Signed-off-by: Alistair Francis
>
> Reviewed-by: Peter Crosthwaite
Thanks Peter
Alis
On 4/26/15 03:30, Richard Henderson wrote:
> On 04/25/2015 05:12 AM, Chen Gang wrote:
>> Hello All:
>>
>> I want to consult an issue I met below for the latest master branch, is
>> it a qemu's bug? (it is about ctz/cnttz instruction for tilegx)
>>
>> OP:
>>ld_i32 tmp0,env,$0xfffc
On Apr 25, 2015, at 12:00 PM, qemu-discuss-requ...@nongnu.org wrote:
> Kris zhang writes:
>> On Wednesday, April 8, 2015, Programmingkid
>> wrote:
>>> It would be great if QEMU could emulate a 3D video card. We would all be
>> able to play our games in it. VirtualBox does have a GPL v2 implemen
On 04/25/2015 05:12 AM, Chen Gang wrote:
> Hello All:
>
> I want to consult an issue I met below for the latest master branch, is
> it a qemu's bug? (it is about ctz/cnttz instruction for tilegx)
>
> OP:
>ld_i32 tmp0,env,$0xfffc
>movi_i32 tmp1,$0x0
>brcond_i32 tmp0,tmp1
On Sat, Apr 25, 2015 at 1:18 AM, Alistair Francis wrote:
> Add the STM32F2xx SPI device.
>
> Signed-off-by: Alistair Francis
> ---
>
> default-configs/arm-softmmu.mak | 1 +
> hw/ssi/Makefile.objs| 1 +
> hw/ssi/stm32f2xx_spi.c | 211
> ++
On Sat, Apr 25, 2015 at 1:18 AM, Alistair Francis wrote:
> Add the STM32F2xx ADC device. This device randomly
> generates values on each read.
>
> Signed-off-by: Alistair Francis
> ---
>
> default-configs/arm-softmmu.mak | 1 +
> hw/misc/Makefile.objs | 1 +
> hw/misc/stm32f2xx_adc
On Sat, Apr 25, 2015 at 1:18 AM, Alistair Francis wrote:
> If correctly configured allow the STM32F2xx timer to print
> out the PWM duty cycle information.
>
> Signed-off-by: Alistair Francis
> ---
>
> hw/timer/stm32f2xx_timer.c | 10 ++
> 1 file changed, 10 insertions(+)
>
> diff --git
On Sat, Apr 25, 2015 at 1:18 AM, Alistair Francis wrote:
> Cleanup the individual DeviceState and SysBusDevice
> variables to re-use the same variable for each
> device.
>
> Signed-off-by: Alistair Francis
Reviewed-by: Peter Crosthwaite
> ---
>
> hw/arm/stm32f205_soc.c | 30 +++---
"devices"
On Sat, Apr 25, 2015 at 1:18 AM, Alistair Francis wrote:
> Connect the ADC device to the STM32F205 SoC.
>
"devices"
> Signed-off-by: Alistair Francis
> ---
>
> hw/arm/stm32f205_soc.c | 22 ++
> include/hw/arm/stm32f205_soc.h | 3 +++
> 2 files changed, 2
"devices"
On Sat, Apr 25, 2015 at 1:19 AM, Alistair Francis wrote:
> Connect the SPI device to the STM32F205 SoC.
>
"devices".
Curious. Are you attaching the SPI slaves on the command line using -device?
Otherwise:
Reviewed-by: Peter Crosthwaite
Regards,
Peter
> Signed-off-by: Alistair Fra
On Sat, Apr 25, 2015 at 1:19 AM, Alistair Francis wrote:
> Add Alistair Francis as the maintainer for the Netduino 2
> and SMM32F205 SoC.
>
> Signed-off-by: Alistair Francis
Reviewed-by: Peter Crosthwaite
> ---
>
> MAINTAINERS | 15 +++
> 1 file changed, 15 insertions(+)
>
> diff
On Fri, Apr 24, 2015 at 02:51:59PM -0600, Eric Blake wrote:
> On 04/24/2015 10:20 AM, Kashyap Chamarthy wrote:
> > On Fri, Apr 24, 2015 at 11:52:00AM -0400, John Snow wrote:
> >>
> >> On 04/24/2015 04:32 AM, Kashyap Chamarthy wrote:
> >
> > [. . .]
> >
> >> These:
> >>
> >>> block-dirty-bitma
Am 25.04.2015 um 17:28 schrieb Eduardo Habkost:
> The QJSON code used casts to (QJSON*) directly, instead of OBJECT_CHECK.
> There were even some functions using object_dynamic_cast() calls
> followed by assert(), which is exactly what OBJECT_CHECK does (by
> calling object_dynamic_cast_assert()).
The QJSON code used casts to (QJSON*) directly, instead of OBJECT_CHECK.
There were even some functions using object_dynamic_cast() calls
followed by assert(), which is exactly what OBJECT_CHECK does (by
calling object_dynamic_cast_assert()).
Signed-off-by: Eduardo Habkost
---
qjson.c | 10 +
Hello All:
I want to consult an issue I met below for the latest master branch, is
it a qemu's bug? (it is about ctz/cnttz instruction for tilegx)
OP:
ld_i32 tmp0,env,$0xfffc
movi_i32 tmp1,$0x0
brcond_i32 tmp0,tmp1,ne,$L0
movi_i64 tmp3,$0x0/* Initial
Kris zhang writes:
> On Wednesday, April 8, 2015, Programmingkid
> wrote:
>> It would be great if QEMU could emulate a 3D video card. We would all be
> able to play our games in it. VirtualBox does have a GPL v2 implementation
> of a 2D and 3D video card. If there any reason why we can't port the
On Sat, 25 Apr 2015 09:12:58 +0300
Michael Tokarev wrote:
> 31.03.2015 20:32, Luiz Capitulino wrote:
> > A VM supports only one balloon device, but due to several changes
> > in infrastructure the error message got messed up when trying
> > to add a second device. Fix it.
> ...
> Heh. Such a hug
On Apr 25, 2015, at 12:56 AM, Kris zhang wrote:
> I have same question too, anybody know the reason?
>
>
> On Wednesday, April 8, 2015, Programmingkid wrote:
> > It would be great if QEMU could emulate a 3D video card. We would all be
> > able to play our games in it. VirtualBox does have a G
add8aa99bfbadabee129a0b0295f7717ba100a37 already converted many of there,
however EEH was not affected. This may be squashed there.
This makes find_phb()/find_dev() public and changed its names
to spapr_pci_find_phb()/spapr_pci_find_dev() as they are going to
be used from other parts of QEMU such
This allows dynamic allocation for migrating arrays.
Already existing VMSTATE_VARRAY_UINT32 requires an array to be
pre-allocated, however there are cases when the size is not known in
advance and there is no real need to enforce it.
This defines another variant of VMSTATE_VARRAY_UINT32 with WMS_
(cut-n-paste from kernel patchset)
Each Partitionable Endpoint (IOMMU group) has an address range on a PCI bus
where devices are allowed to do DMA. These ranges are called DMA windows.
By default, there is a single DMA window, 1 or 2GB big, mapped at zero
on a PCI bus.
PAPR defines a DDW RTAS AP
This enables multiple IOMMU groups in one VFIO container which means
that multiple devices from different groups can share the same IOMMU
table (or tables if DDW).
This removes a group id from vfio_container_ioctl(). The kernel support
is required for this; if the host kernel does not have the sup
This moves SPAPR bits to a separate file to avoid pollution of x86 code.
This enables spapr-vfio on CONFIG_SOFTMMU (not CONFIG_PSERIES) as
the config options are only visible in makefiles and not in the source code
so there is no an obvious way of implementing stubs if hw/vfio/spapr.c is
not compi
This reworks finish_realize() which used to finalize DMA setup with
an assumption that it will not change later.
New callbacks supports various window parameters such as page and
windows sizes. The new callback return error code rather than Error**.
This is a mechanical change so no change in beh
Currently TCE tables are created once at start and their size never
changes. We are going to change that by introducing a Dynamic DMA windows
support where DMA configuration may change during the guest execution.
This changes spapr_tce_new_table() to create an empty stub object. Only
LIOBN is assi
This enables DDW RTAS-related ioctls in VFIO.
Signed-off-by: Alexey Kardashevskiy
---
hw/vfio/common.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/vfio/common.c b/hw/vfio/common.c
index 9e3e0b0..f915127 100644
--- a/hw/vfio/common.c
+++ b/hw/vfio/common.c
@@ -830,6 +830,8 @@ int vfi
We are going to have multiple DMA windows at different offsets on
a PCI bus. For the sake of migration, we will have as many TCE table
objects pre-created as many windows supported.
So we need a way to map windows dynamically onto a PCI bus
when migration of a table is completed but at this stage a
Since the changes are not in upstream yet, no tag or branch is specified here.
Signed-off-by: Alexey Kardashevskiy
---
linux-headers/linux/vfio.h | 88 --
1 file changed, 85 insertions(+), 3 deletions(-)
diff --git a/linux-headers/linux/vfio.h b/linux
This adds support for Dynamic DMA Windows (DDW) option defined by
the SPAPR specification which allows to have additional DMA window(s)
This implements DDW for emulated and VFIO devices. As all TCE root regions
are mapped at 0 and 64bit long (and actual tables are child regions),
this replaces mem
sPAPRTCETable is handling 2 TCE tables already:
1) guest view of the TCE table - emulated devices use only this table;
2) hardware IOMMU table - VFIO PCI devices use it for actual work but
it does not replace 1) and it is not visible to the guest.
The initialization of this table is driven by vfi
The next patch implements dynamic DMA windows and disables them by default
for older pseries machines.
Signed-off-by: Alexey Kardashevskiy
Reviewed-by: David Gibson
---
hw/ppc/spapr.c | 24 ++--
1 file changed, 22 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/spapr.c b/
On a system reset, DMA configuration has to reset too. At the moment
it clears the table content. This is enough for the single table case
but with DDW, we will also have to disable all DMA windows except
the default one. Furthermore according to sPAPR, if the guest removed
the default window and c
This makes use of the new "memory registering" feature. The idea is
to provide the userspace ability to notify the host kernel about pages
which are going to be used for DMA. Having this information, the host
kernel can pin them all once per user process, do locked pages
accounting (once) and not s
On 25 April 2015 at 02:51, Wenjie Liu wrote:
> Hi Peter,
> Does the equation which is mentioned in
> http://vm-kernel.org/blog/2009/07/10/qemu-internal-part-2-softmmu/ means
> something?
> host_virtual_address = phys_ram_base(qemu variable) + guest_physical_address
> – guest_physical_address_base(
I have same question too, anybody know the reason?
On Wednesday, April 8, 2015, Programmingkid
wrote:
> It would be great if QEMU could emulate a 3D video card. We would all be
able to play our games in it. VirtualBox does have a GPL v2 implementation
of a 2D and 3D video card. If there any reas
Hi Eric,
On 03/19/15 12:16, Eric Auger wrote:
> This patch allows the instantiation of the vfio-calxeda-xgmac device
> from the QEMU command line (-device vfio-calxeda-xgmac,host="").
>
> A specialized device tree node is created for the guest, containing
> compat, dma-coherent, reg and interrupts
Connect the SPI device to the STM32F205 SoC.
Signed-off-by: Alistair Francis
---
hw/arm/stm32f205_soc.c | 22 ++
include/hw/arm/stm32f205_soc.h | 3 +++
2 files changed, 25 insertions(+)
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
index 641ecbb..cb
Add Alistair Francis as the maintainer for the Netduino 2
and SMM32F205 SoC.
Signed-off-by: Alistair Francis
---
MAINTAINERS | 15 +++
1 file changed, 15 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d7e9ba2..ad9827a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -355,6
Add the STM32F2xx SPI device.
Signed-off-by: Alistair Francis
---
default-configs/arm-softmmu.mak | 1 +
hw/ssi/Makefile.objs| 1 +
hw/ssi/stm32f2xx_spi.c | 211
include/hw/ssi/stm32f2xx_spi.h | 74 ++
4 files chang
Connect the ADC device to the STM32F205 SoC.
Signed-off-by: Alistair Francis
---
hw/arm/stm32f205_soc.c | 22 ++
include/hw/arm/stm32f205_soc.h | 3 +++
2 files changed, 25 insertions(+)
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
index 63893f3..64
Add the STM32F2xx ADC device. This device randomly
generates values on each read.
Signed-off-by: Alistair Francis
---
default-configs/arm-softmmu.mak | 1 +
hw/misc/Makefile.objs | 1 +
hw/misc/stm32f2xx_adc.c | 332
include/hw/misc
If correctly configured allow the STM32F2xx timer to print
out the PWM duty cycle information.
Signed-off-by: Alistair Francis
---
hw/timer/stm32f2xx_timer.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/hw/timer/stm32f2xx_timer.c b/hw/timer/stm32f2xx_timer.c
index ecadf9d..6f
Cleanup the individual DeviceState and SysBusDevice
variables to re-use the same variable for each
device.
Signed-off-by: Alistair Francis
---
hw/arm/stm32f205_soc.c | 30 +++---
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/hw/arm/stm32f205_soc.c b/hw/
This patchset continues with the Netduino 2 and STM32F205 SoC
work.
This patch series makes a small change to the STM32F2xx
SoC to tidy up the code.
Next a feature is added to the STM32F2xx timer to display the
PWM duty cycle, when debugging is enabled.
Then the STM32F2xx SPI and ADC devices are
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