From: "Edgar E. Iglesias"
Reviewed-by: Peter Crosthwaite
Signed-off-by: Edgar E. Iglesias
---
target-arm/cpu.h| 2 +-
target-arm/helper.c | 5 +
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 3ccbd95..8d04385 100644
--- a/target-
From: "Edgar E. Iglesias"
Reviewed-by: Peter Crosthwaite
Signed-off-by: Edgar E. Iglesias
---
target-arm/cpu.h| 2 +-
target-arm/helper.c | 21 +
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index b14fac5..3ccbd95 1
From: "Edgar E. Iglesias"
Reviewed-by: Peter Crosthwaite
Signed-off-by: Edgar E. Iglesias
---
target-arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index cb7c964a..5a2073e 100644
--- a/target-arm/helper.c
+++ b/target-
From: "Edgar E. Iglesias"
Reviewed-by: Peter Crosthwaite
Signed-off-by: Edgar E. Iglesias
---
target-arm/internals.h | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/target-arm/internals.h b/target-arm/internals.h
index c9897c2..564b5fa 100644
--- a/target-arm/in
From: "Edgar E. Iglesias"
Suggested-by: Peter Maydell
Signed-off-by: Edgar E. Iglesias
---
target-arm/translate-a64.c | 4
1 file changed, 4 insertions(+)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index bfd139a..ec6a39d 100644
--- a/target-arm/translate-a64.c
+
From: "Edgar E. Iglesias"
Adds support for ERET to and from AArch64 EL2 and 3.
Signed-off-by: Edgar E. Iglesias
---
target-arm/op_helper.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index e95a7f4..50a4157 1006
[quoted lines by Peter Maydell on 2014/05/25 at 01:04 +0100]
>Why is this a problem only for the curses UI frontend, and not for
>any of the other UIs which might send key events?
One reason is that most UIs send key events as they receive them from the
keyboard, one at a time, whereas the curse
From: "Edgar E. Iglesias"
Reviewed-by: Peter Crosthwaite
Signed-off-by: Edgar E. Iglesias
---
target-arm/helper.c | 16
1 file changed, 16 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 81de010..cb7c964a 100644
--- a/target-arm/helper.c
+++ b/targe
From: "Edgar E. Iglesias"
Reviewed-by: Peter Crosthwaite
Signed-off-by: Edgar E. Iglesias
---
target-arm/op_helper.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index c2b4bf0..e95a7f4 100644
--- a/target-arm/op_hel
From: "Edgar E. Iglesias"
Reviewed-by: Peter Crosthwaite
Signed-off-by: Edgar E. Iglesias
---
target-arm/helper.c | 16
1 file changed, 16 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 5e2eac3..81de010 100644
--- a/target-arm/helper.c
+++ b/target
From: "Edgar E. Iglesias"
Reviewed-by: Peter Crosthwaite
Signed-off-by: Edgar E. Iglesias
---
target-arm/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 75a4ed8..b14fac5 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -634,6 +634,7 @@
From: "Edgar E. Iglesias"
Reviewed-by: Peter Crosthwaite
Signed-off-by: Edgar E. Iglesias
---
target-arm/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 5919dfd..75a4ed8 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -633,6 +633,7 @@
From: "Edgar E. Iglesias"
Add aarch64_banked_spsr_index(), used to map an Exception Level
to an index in the banked_spsr array.
Reviewed-by: Peter Crosthwaite
Signed-off-by: Edgar E. Iglesias
---
target-arm/helper-a64.c | 2 +-
target-arm/internals.h | 14 ++
target-arm/op_helpe
From: "Edgar E. Iglesias"
Reviewed-by: Peter Crosthwaite
Signed-off-by: Edgar E. Iglesias
---
target-arm/cpu.h | 4 +++-
target-arm/helper.c| 4
target-arm/machine.c | 6 +++---
target-arm/translate.c | 4 ++--
4 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/ta
From: "Edgar E. Iglesias"
Reviewed-by: Peter Crosthwaite
Signed-off-by: Edgar E. Iglesias
---
target-arm/cpu.h | 2 +-
target-arm/machine.c | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 62d85ff..ba1d495 100644
--- a/tar
From: "Edgar E. Iglesias"
Reviewed-by: Peter Crosthwaite
Signed-off-by: Edgar E. Iglesias
---
target-arm/cpu.h | 2 +-
target-arm/machine.c | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index ba1d495..60414ac 100644
--- a/tar
From: "Edgar E. Iglesias"
No functional change.
Preparation for adding EL2 and 3 versions of this reg.
Reviewed-by: Peter Crosthwaite
Signed-off-by: Edgar E. Iglesias
---
target-arm/cpu.h| 2 +-
target-arm/helper-a64.c | 2 +-
target-arm/helper.c | 6 +++---
3 files changed, 5 ins
From: "Edgar E. Iglesias"
No functional change.
Prepares for future addtion of EL2 and 3 versions of this reg.
Reviewed-by: Peter Crosthwaite
Signed-off-by: Edgar E. Iglesias
---
target-arm/cpu.h| 2 +-
target-arm/helper-a64.c | 4 ++--
target-arm/helper.c | 10 +-
3 fil
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
Message-id: 1400805738-11889-7-git-send-email-edgar.igles...@gmail.com
---
target-arm/cpu.h | 8
target-arm/translate.h | 6 +-
2 files changed, 5 insertions(+), 9 deletions(-)
diff --git a/target-arm/cpu.h b/target-
From: "Edgar E. Iglesias"
No functional change.
Prepares for future additions of the EL2 and 3 versions of this reg.
Reviewed-by: Peter Crosthwaite
Signed-off-by: Edgar E. Iglesias
---
target-arm/cpu.h| 2 +-
target-arm/helper-a64.c | 4 ++--
target-arm/helper.c | 3 ++-
target-ar
From: "Edgar E. Iglesias"
Avoid using IS_USER directly as the MMU-idx to simplify future
changes to the MMU layout.
Reviewed-by: Peter Maydell
Signed-off-by: Edgar E. Iglesias
Message-id: 1400805738-11889-6-git-send-email-edgar.igles...@gmail.com
[PMM: parts relating to LDRT/STRT moved into ea
From: Peter Maydell
The SRS instruction was using a hardcoded 0 for the memory
accesses. This happens to be OK since the SRS instruction is
UNPREDICTABLE in User and System modes, but is awkward if we
want to rearrange the MMU index uses. Switch to using
get_mem_index() like all the other accesse
From: Peter Maydell
Clean up the mmu index handling for ldrt/strt insns: instead
of a flag 'user' indicating whether to treat the store as user
mode or not, use 'memidx' to indicate the correct memory index to use.
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Peter Maydell
---
target-arm/tra
From: "Edgar E. Iglesias"
So that it can be shared with the AArch32 code.
Signed-off-by: Edgar E. Iglesias
Message-id: 1400805738-11889-5-git-send-email-edgar.igles...@gmail.com
---
target-arm/translate-a64.c | 9 -
target-arm/translate.h | 9 +
2 files changed, 9 insertion
From: "Edgar E. Iglesias"
Hi,
I've been doing some work on modeling parts of EL2 and 3 + some of
the system-wide virtualization features for ARMv8. A lot is missing
but I've got a series with enough to for example run KVM A64 guests
on top of EL3 firmware inside emulated QEMU A64 VMs.
I'm workin
It does not change the the behaviour.
With or without those options the VM qemu-system-ppc session never exits.
Regards,
John.
--
o Energy-efficiency is #1 reason data centers look to expand. --
Digital Realty Trust
o Green Data Centers spending to increase 300% worldwide by 2016. --
Pike Re
On Fri, May 23, 2014 at 04:39:21PM +0100, Peter Maydell wrote:
> On 23 May 2014 13:54, Peter Maydell wrote:
> > On 23 May 2014 01:41, Edgar E. Iglesias wrote:
> >> From: "Edgar E. Iglesias"
> >>
> >> Hi,
> >>
> >> I've been doing some work on modeling parts of EL2 and 3 + some of
> >> the system
Quoting joh...@servergy.com (joh...@servergy.com):
> qemu-system-ppc never terminates.
Assuming you are using the same scripts as in the other bugs, you are passing
-no-shutdown to qemu, asking it to not exit when the guest exits. If you
want qemu to exit when the guest is done, then please remov
qemu-system-ppc never terminates.
Regards,
John.
--
o Energy-efficiency is #1 reason data centers look to expand. --
Digital Realty Trust
o Green Data Centers spending to increase 300% worldwide by 2016. --
Pike Research
o Data Centers have become as vital to the functioning of society as
po
On 25 May 2014 00:29, Dave Mielke wrote:
> The attached patch (qemu-curses-delay-1.patch) allows the user to specify that
> he needs -display curses to insert a delay in between key events. The current
> behaviour is that it inserts key events immediately, one right after another,
> which has prov
The attached patch (qemu-curses-delay-1.patch) allows the user to specify that
he needs -display curses to insert a delay in between key events. The current
behaviour is that it inserts key events immediately, one right after another,
which has proven to be too fast for some applications. Please
What do you mean by "cannot be rebooted"? When you log into the guest
and type "reboot", nothing happens? Does init call reboot(2) and the
kernel ignores it? All of userspace is properly terminated, and kernel
hangs at the actual reboot?
** Also affects: qemu
Importance: Undecided
Sta
iotest 083 filters out debug messages from nbd, which are prefixed (and
recognized) by __FILE__. However, the current filter (/^nbd\.c…/) is
valid for in-tree builds only, as out-of-tree builds will have a path
before that filename (e.g. "/tmp/qemu/nbd.c"). Fix this by adding .*
before "nbd\.c".
W
In order to allow out-of-tree iotests, create a symlink for the check
script in the build tree.
While doing so, also write configured options relevant to the iotests to
common.env in the build tree; currently, this is the command to invoke
Python 2.
Signed-off-by: Max Reitz
---
configure | 12 +
Test 065 specified python2 to be used in its Shebang; this might not
work on systems without a python2 symlink and furthermore it is now
counter-productive, as the check script compares the Shebang to
"#!/usr/bin/env python" and only uses the Python interpreter selected by
configure on an exact mat
On 24.05.2014 23:24, Max Reitz wrote:
This series enables qemu-iotests to be run in a build tree outside of
the source tree. It also makes the tests use the command for invoking
the Python interpreter specified through configure instead of always
using "/usr/bin/env python".
v4:
- Patch 1:
Source common.env in the iotests' check script.
Signed-off-by: Max Reitz
---
tests/qemu-iotests/check | 6 ++
1 file changed, 6 insertions(+)
diff --git a/tests/qemu-iotests/check b/tests/qemu-iotests/check
index 69f328b..992b91e 100755
--- a/tests/qemu-iotests/check
+++ b/tests/qemu-iotest
Instead of invoking Python scripts directly via ./, use $PYTHON to
obtain the correct Python interpreter command.
Signed-off-by: Max Reitz
Reviewed-by: Fam Zheng
---
tests/qemu-iotests/031 | 8
tests/qemu-iotests/036 | 6 +++---
tests/qemu-iotests/039 | 18 +-
t
As out-of-tree builds are preferred for qemu, running the qemu-iotests
in that out-of-tree build should be supported as well. To do so, a
symbolic link has to be created pointing to the check script in the
source directory. That script will check whether it has been run through
a symlink, and if so
This series enables qemu-iotests to be run in a build tree outside of
the source tree. It also makes the tests use the command for invoking
the Python interpreter specified through configure instead of always
using "/usr/bin/env python".
v4:
- Patch 1:
- fixed a comment ("assume that it truly
On 23.05.2014 06:01, Fam Zheng wrote:
On Thu, 05/22 23:30, Max Reitz wrote:
Source common.env in the iotests' check script. If the one supposed to
be created by configure cannot be found, use common.env.default from the
source tree.
Signed-off-by: Max Reitz
---
tests/qemu-iotests/check | 16
On 23.05.2014 15:33, Markus Armbruster wrote:
Eric Blake writes:
On 05/23/2014 12:10 AM, Fam Zheng wrote:
On Thu, 05/22 23:30, Max Reitz wrote:
Add a default common.env in case the one supposed to be emitted by
configure cannot be found.
Signed-off-by: Max Reitz
Now we can run both from i
On 23.05.2014 05:58, Fam Zheng wrote:
On Thu, 05/22 23:30, Max Reitz wrote:
Instead of invoking Python scripts directly via ./, use $PYTHON to
obtain the correct Python interpreter command.
Signed-off-by: Max Reitz
---
tests/qemu-iotests/031 | 8
tests/qemu-iotests/036 | 6 ++
On 23.05.2014 05:47, Fam Zheng wrote:
On Thu, 05/22 23:30, Max Reitz wrote:
In order to allow out-of-tree iotests, create a symlink for the check
script in the build tree.
While doing so, also write configured options relevant to the iotests to
common.env in the build tree; currently, this is t
Since we have now semihosting on the lm32 target, this device is no longer
needed. Remove it.
Signed-off-by: Michael Walle
---
hw/misc/Makefile.objs |1 -
hw/misc/lm32_sys.c| 179 -
target-lm32/README| 10 ---
trace-events |
Intercept certain system calls if semihosting is enabled. This should
behave like the GDB simulator.
Signed-off-by: Michael Walle
---
qemu-options.hx |3 +-
target-lm32/Makefile.objs |1 +
target-lm32/README|9 ++
target-lm32/cpu.h |1 +
target-lm32/help
Instead of the lm32-sys device, use semihosting to print to the host
console and exit the test.
Signed-off-by: Michael Walle
---
tests/tcg/lm32/Makefile | 15 +-
tests/tcg/lm32/crt.S|4 +--
tests/tcg/lm32/helper.S | 65 +++
Make test cases independent from from each other. Eg. if a test case needs
a specific value in register A, don't rely on the fact that it is already
set by the preceding test case.
Signed-off-by: Michael Walle
---
tests/tcg/lm32/test_lb.S |4
tests/tcg/lm32/test_lbu.S |4
test
ranch 'remotes/qmp-unstable/queue/qmp' into staging
(2014-05-22 19:04:49 +0100)
are available in the git repository at:
git://github.com/mwalle/qemu tags/lm32-semihosting/20140524
for you to fetch changes up to 25156d10617794f9399d676ccd9a20f52e0c9f21:
lm32: remove lm32_sys (2014-05-24
Emitting a single branch instead of (up to) 3, using setcond2
to generate the composite compare.
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c | 77 +--
1 file changed, 20 insertions(+), 57 deletions(-)
dif
And use it in the opcode emission functions.
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index 54571fb..920208a 100644
-
Use the same table to fold comparisons as with setcond.
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c | 87 ---
1 file changed, 41 insertions(+), 46 deletions(-)
diff --git a/tcg/mips/tcg-target.c b/tcg/mip
Use this to reduce goto_tb by one insn.
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c | 23 ---
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index 2d2073f..5ccfb1d 100644
At the same time, tidy up the call helpers, avoiding a memory reference.
Split out several subroutines. Use TCGMemOp constants. Make endianness
selectable at runtime.
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c | 772 +-
For userland builds calls will normally be in range,
and for the exit_tb opcode the branch to the epilogue.
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c | 46 --
1 file changed, 40 insertions(+), 6 deletions(-)
Use a table to fold comparisons to less-than.
Also, move the function up in the file for futher simplifications.
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c | 125 +++---
1 file changed, 67 insertions(+), 58 d
Using tcg_unsigned_cond and tcg_high_cond.
Also, move the function up in the file for future cleanups.
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c | 95 +--
1 file changed, 31 insertions(+), 64 deletions(-
The original code results in one too many insns per zero
present in the input. And since comparing 64-bit numbers
vs zero is common...
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c | 40
1 file changed, 36 inserti
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c | 201 ++
1 file changed, 103 insertions(+), 98 deletions(-)
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index 5021dea..516c2b7 100644
--- a/tcg/m
Most opcodes fall in to one of a couple of patterns.
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c | 212 +++---
1 file changed, 98 insertions(+), 114 deletions(-)
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/
Since we must use ADDUI, we would generate incorrect code for -32768.
Leaving off subtract of +32768 makes things easier for a follow-on patch.
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c | 16 +++-
1 file changed, 11 insertions(+), 5 deleti
At the same time, tidy deposit by introducing tcg_out_opc_bf.
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c | 60 ++-
tcg/mips/tcg-target.h | 4
2 files changed, 50 insertions(+), 14 deletions(-)
diff
Use these instead of hard-coding the registers to use for temporaries.
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c | 231 +-
1 file changed, 117 insertions(+), 114 deletions(-)
diff --git a/tcg/mips/tcg-t
Now that the code_gen_buffer is constrained to not cross 256mb
regions, we are assured that we can use J to reach another TB.
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 4 ++--
tcg/mips/tcg-target.c | 11 ++-
2 files changed, 12 insertio
Use the same table to fold comparisons as with setcond.
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c | 66 +--
1 file changed, 17 insertions(+), 49 deletions(-)
diff --git a/tcg/mips/tcg-target.c b/tcg/mip
Use FP (also known as S8) as a normal call-saved register.
Include T0 in the allocation order and call-clobbered list
even though it's currently used as a TCG temporary.
Put the argument registers at the end of the allocation order.
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
-
On 24 May 2014 13:59, Paolo Bonzini wrote:
> Il 24/05/2014 10:30, Peter Maydell ha scritto:
>> Well, I'm planning to move the bodies of all the ifdefs into
>> a cpu_check_interrupts() provided by the target's cpu.h[*].
>> This x86 bit is just awkward because it means there's
>> x86 stuff both befo
In addition, fill delay slots calling the helpers and tail
call to the store helpers.
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c | 107 ++
1 file changed, 56 insertions(+), 51 deletions(-)
diff --git a/t
T0 is an argument register for the n32 and n64 abis. T9 is the call
address register for the abis, and is more directly under the control
of the backend.
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reduce insn count from 5 to either 3 or 4.
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c | 87 +--
1 file changed, 56 insertions(+), 31 deletions(-)
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c | 76 ---
tcg/mips/tcg-target.h | 2 +-
2 files changed, 25 insertions(+), 53 deletions(-)
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index f410
Thanks to Paolo for the review.
r~
The following changes since commit 178ac111bca16c08a79b2609ebdc75197bea976a:
Merge remote-tracking branch 'remotes/qmp-unstable/queue/qmp' into staging
(2014-05-22 19:04:49 +0100)
are available in the git repository at:
git://github.com/rth7680/qemu.gi
This assures us use of J for exit_tb and goto_tb, and JAL for calling
into the generated bswap helpers.
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
---
translate-all.c | 90 +
1 file changed, 85 insertions(+), 5 deletions(-
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c | 25 ++---
1 file changed, 18 insertions(+), 7 deletions(-)
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index d4236c0..2d2073f 100644
--- a/tcg/mips/tcg-target.c
+++ b/tcg/m
Choosing good addresses for them means we can use JAL for helper calls.
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
---
configure | 7 +--
translate-all.c | 13 +
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/configure b/configure
index 6
On 05/24/2014 02:55 AM, Paolo Bonzini wrote:
> Il 14/05/2014 09:17, Richard Henderson ha scritto:
>> +tcg_out_opc_imm(s, OPC_LW, TCG_REG_A0, TCG_REG_A0, add_off);
>> +tcg_out_opc_reg(s, OPC_AND, TCG_REG_T0, TCG_REG_T0, addrl);
>> +
>> +label_ptr[0] = s->code_ptr;
>> tcg_out_opc_br(
Il 24/05/2014 10:30, Peter Maydell ha scritto:
> Well, I'm planning to move the bodies of all the ifdefs into
> a cpu_check_interrupts() provided by the target's cpu.h[*].
> This x86 bit is just awkward because it means there's
> x86 stuff both before and after the generic reset code.
What about
The case statements in the CG3 read and write register routines have a maximum
value of CG3_REG_SIZE, so if a value were written to this offset then it
would overflow the register array.
Currently this cannot be exploited since the MemoryRegion restricts accesses
to the range 0 ... CG3_REG_SIZE -
Initialisation cleanup as suggested by Andreas.
Signed-off-by: Mark Cave-Ayland
CC: Andreas Färber
---
hw/display/tcx.c | 46 --
hw/sparc/sun4m.c | 10 +-
2 files changed, 33 insertions(+), 23 deletions(-)
diff --git a/hw/display/tcx.c b/
This is an intermediate step to bring TCX in line with CG3.
Signed-off-by: Mark Cave-Ayland
CC: Andreas Färber
---
hw/display/tcx.c | 26 --
1 file changed, 12 insertions(+), 14 deletions(-)
diff --git a/hw/display/tcx.c b/hw/display/tcx.c
index 2551b67..8fc4e38 10064
This patchset primarily addresses Andreas' comments with regard to cg3
init/realize. The
first patch addresses this, followed by a second patch to address a previous
comment made
by Paolo.
The last two patches then alter tcx in a similar fashion to bring it in line
with the
cg3 changes.
Signe
Initialisation cleanup as suggested by Andreas.
Signed-off-by: Mark Cave-Ayland
CC: Andreas Färber
---
hw/display/cg3.c | 23 +++
1 file changed, 15 insertions(+), 8 deletions(-)
diff --git a/hw/display/cg3.c b/hw/display/cg3.c
index f5a8299..cd9297d 100644
--- a/hw/displ
Il 23/05/2014 21:15, Richard Henderson ha scritto:
Ping?
Reviewed-by: Paolo Bonzini
Paolo
Il 14/05/2014 09:17, Richard Henderson ha scritto:
+tcg_out_opc_imm(s, OPC_LW, TCG_REG_A0, TCG_REG_A0, add_off);
+tcg_out_opc_reg(s, OPC_AND, TCG_REG_T0, TCG_REG_T0, addrl);
+
+label_ptr[0] = s->code_ptr;
tcg_out_opc_br(s, OPC_BNE, TCG_REG_T0, TCG_REG_AT);
-tcg_out_nop(s);
On 23 May 2014 19:10, Paolo Bonzini wrote:
> Il 23/05/2014 19:59, Peter Maydell ha scritto:
>
>> On 2 May 2014 15:33, Paolo Bonzini wrote:
>> I was looking at cleaning up the horrible ifdef ladder a little
>> lower in this function, and I noticed this code had been
>> added recently. Why is TARGE
24.05.2014 03:06, Peter Crosthwaite wrote:
> Ping^2!
>
> I'll try trivial queue too :)
Actually this looks like trivial material.
I'll comment in one place, for all.
>>> Peter Crosthwaite (4):
>>> net: cadence_gem: Fix Tx descriptor update
This appears to be a bugfix, but with an interestin
24.05.2014 04:16, Andrew Oates wrote:
> Without the mask, control bits are passed on in the keycode, generating
> incorrect PS/2 sequences when SHIFT, ALT, etc are held down.
While the patch itself appears to be trivial, it may have
non-trivial effect. Cc'ing Gerd for comments.
Thank you!
/mjt
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