Il 09/02/2014 01:23, Peter Maydell ha scritto:
FWIW, we have just 39 files[*] which fail to follow the "declarations at
start of block" rule out of 2566, which is pretty good compliance for a
coding style rule which isn't enforced by technical means (I expect
it's much better than we achieve for
First of all, sorry for snipping the technical parts. You made good
points, but I think the actual problem is not technical. We should
first sort out the social part.
Il 09/02/2014 02:41, Andreas Färber ha scritto:
Similarly I feel that you have given quite some destructive feedback to
my fa
Il 09/02/2014 01:18, Peter Maydell ha scritto:
Haven't checked it yet. I just don't really see what the point is
in having a huge amount of OS specific code to do something
which we already do in a portable way. It might be nice to abstract
out stashing initial-argv0 and adding a utility function
On Sun, Feb 9, 2014 at 2:38 AM, Mark Cave-Ayland
wrote:
> The CG3 framebuffer is a simple 8-bit framebuffer for use with operating
> systems such as early Solaris that do not have drivers for TCX.
>
> Signed-off-by: Mark Cave-Ayland
> CC: Blue Swirl
> CC: Anthony Liguori
> CC: Peter Maydell
>
On Sat, Feb 1, 2014 at 1:45 AM, Peter Maydell wrote:
> The read_raw_cp_reg and write_raw_cp_reg functions can now never
> fail (in fact they should never have failed previously unless
> there was a bug in a reginfo that meant no raw accessor was
> provided for a might-trap register). This allows u
On Sat, Feb 1, 2014 at 1:45 AM, Peter Maydell wrote:
> Now that cpreg read and write functions can't fail and throw an
> exception, we can remove the code from the translator that synchronises
> the guest PC in case an exception is thrown.
>
Based on my comment last patch, this may be overly rest
On Sat, Feb 1, 2014 at 1:45 AM, Peter Maydell wrote:
> All cpreg read and write functions now return 0, so we can clean up
> their prototypes:
> * write functions return void
> * read functions return the value rather than taking a pointer
>to write the value to
>
> This is a fairly mechanic
On Sat, Feb 1, 2014 at 1:45 AM, Peter Maydell wrote:
> Convert the remaining miscellaneous cases of reginfo read/write
> functions returning EXCP_UDEF to use an accessfn instead:
> TEEHBR, and the ATS address-translation operations.
>
> Signed-off-by: Peter Maydell
> ---
> target-arm/helper.c |
On Sat, Feb 1, 2014 at 1:45 AM, Peter Maydell wrote:
> Convert the reginfo structs for the generic timer registers
> to use access functions rather than returning EXCP_UDEF from
> their read handlers. In some cases this allows us to remove
> a read handler completely.
>
> Signed-off-by: Peter Mayd
On Wed, Feb 5, 2014 at 9:01 PM, Peter Maydell wrote:
> On 5 February 2014 06:59, Peter Crosthwaite
> wrote:
>> cc Alistair, this may conflict with his timer work.
>>
>> On Sat, Feb 1, 2014 at 1:45 AM, Peter Maydell
>> wrote:
>>> @@ -624,37 +606,41 @@ static const ARMCPRegInfo v7_cp_reginfo[] =
On Sat, Feb 1, 2014 at 1:45 AM, Peter Maydell wrote:
> Several of the system registers handled via the ARMCPRegInfo
> mechanism have access trap control bits controlling whether the
> registers are accessible to lower privilege levels. Replace
> the existing mechanism (allowing the read and write
On Sat, Feb 1, 2014 at 1:45 AM, Peter Maydell wrote:
> Define a dummy version of the AArch64 OSLAR_EL1 system register
> which just ignores writes. Linux will always write to this (it
> is the OS lock used for debugging), but we don't support debug.
>
> Signed-off-by: Peter Maydell
Reviewed-by:
On Sat, Feb 1, 2014 at 1:45 AM, Peter Maydell wrote:
> In AArch64 the breakpoint and watchpoint registers are mandatory, so the
> kernel always accesses them on bootup. Implement dummy versions, which
> read as written but have no actual effect.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Pete
On Sat, Feb 1, 2014 at 1:45 AM, Peter Maydell wrote:
> Implement the AArch64-specific ID and feature registers. Although
> many of these are currently not used by the architecture (and so
> always zero for all implementations), we define the full set of
> fields in the ARMCPU struct for symmetry.
On Sat, Feb 1, 2014 at 1:45 AM, Peter Maydell wrote:
> Implement the AArch64 TTBR* registers. For v7 these were already 64 bits
> to handle LPAE, but implemented as two separate uint32_t fields.
> Combine them into a single uint64_t which can be used for all purposes.
> Since this requires touchin
On Sat, Feb 1, 2014 at 1:45 AM, Peter Maydell wrote:
> Implement the AArch64 TCR_EL1, which is the 64 bit view of
> the AArch32 TTBCR. (The uses of the bits in the register are
> completely different, but in any given situation the CPU will
> always interpret them one way or the other. In fact for
On Sat, Feb 1, 2014 at 1:45 AM, Peter Maydell wrote:
> Implement the AArch64 view of the system control register SCTLR_EL1.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
> ---
> target-arm/cpu.h| 2 +-
> target-arm/helper.c | 3 ++-
> 2 files changed, 3 insertions(+), 2
On Sat, Feb 1, 2014 at 1:45 AM, Peter Maydell wrote:
> Implement the AArch64 memory attribute registers. Since QEMU doesn't
> model caches it does not need to care about memory attributes at all,
> and we can simply make these read-as-written.
>
> We did not previously implement the AArch32 versio
On Sat, Feb 1, 2014 at 1:45 AM, Peter Maydell wrote:
> We don't support letting the guest do debug, but Linux prods the
> monitor debug system control register anyway, so implement a dummy
> RAZ/WI version.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
> ---
> target-arm/hel
On Sat, Feb 1, 2014 at 1:45 AM, Peter Maydell wrote:
> Implement all the AArch64 cache invalidate and clean ops
> (which are all NOPs since QEMU doesn't emulate the cache).
> The only remaining unimplemented cache op is DC ZVA.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
>
On Sat, Feb 1, 2014 at 1:45 AM, Peter Maydell wrote:
> Implement the DAIF system register which is a view of the
> DAIF bits in PSTATE.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
> ---
> target-arm/helper.c | 25 +
> 1 file changed, 25 insertions(+
On Sat, Feb 1, 2014 at 1:45 AM, Peter Maydell wrote:
> Implement the CurrentEL sysreg.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
> ---
> target-arm/cpu.h | 3 ++-
> target-arm/helper.c| 3 +++
> target-arm/translate-a64.c | 7 +++
> 3 files changed,
On Sat, Feb 1, 2014 at 1:45 AM, Peter Maydell wrote:
> Make the cache ID system registers (CLIDR, CCSELR, CCSIDR, CTR)
> visible to AArch64. These are mostly simple 64-bit extensions of the
> existing 32 bit system registers and so can share reginfo definitions.
> CTR needs to have a split definit
Am 09.02.2014 02:29, schrieb Peter Crosthwaite:
> On Sat, Feb 1, 2014 at 12:34 AM, Andreas Färber wrote:
>> Hello,
>>
>> This series prepares for converting I2C to QOM realize.
>>
>
> Incase you are moving onto SSI next I do have a have half a start on
> this change pattern for SSI (In particular
On Sat, Feb 1, 2014 at 12:34 AM, Andreas Färber wrote:
> Use type-specific QOM cast macros instead.
>
Should be past tense - "We now use type-specific ...". The imperative
form of "use" suggests you are making the change in this patch but you
have already done it.
> Signed-off-by: Andreas Färber
On Sat, Feb 1, 2014 at 12:34 AM, Andreas Färber wrote:
> Replace usages of FROM_I2C_SLAVE() with QOM cast macro.
> Rename parent field.
"-> cast removed" &&
Reviewed-by: Peter Crosthwaite
>
> Signed-off-by: Andreas Färber
> ---
> hw/timer/twl92230.c | 35 +--
>
On Sat, Feb 1, 2014 at 12:34 AM, Andreas Färber wrote:
> Replace usages of FROM_I2C_SLAVE() with QOM cast macro.
> Rename parent field.
>
> Signed-off-by: Andreas Färber
Reviewed-by: Peter Crosthwaite
> ---
> hw/timer/ds1338.c | 21 +
> 1 file changed, 13 insertions(+), 8
On Sat, Feb 1, 2014 at 12:34 AM, Andreas Färber wrote:
> Replace usages of FROM_I2C_SLAVE() with QOM cast macro.
> Rename parent field.
Same as before, "removal of pointer casts" or something like.
Otherwise:
Reviewed-by: Peter Crosthwaite
>
> Signed-off-by: Andreas Färber
> ---
> hw/input/
On Sat, Feb 1, 2014 at 12:34 AM, Andreas Färber wrote:
> Replace FROM_I2C_SLAVE() usages with QOM cast macro.
> Rename parent field.
>
> Signed-off-by: Andreas Färber
Reviewed-by: Peter Crosthwaite
> ---
> hw/gpio/max7310.c | 23 ++-
> 1 file changed, 14 insertions(+), 9 d
On Sat, Feb 1, 2014 at 12:34 AM, Andreas Färber wrote:
> Replace usages of FROM_I2C_SLAVE() with QOM cast macro.
> Rename parent field.
>
> Signed-off-by: Andreas Färber
Reviewed-by: Peter Crosthwaite
> ---
> hw/display/ssd0303.c | 18 --
> 1 file changed, 12 insertions(+), 6
Am 09.02.2014 00:33, schrieb Paolo Bonzini:
> If you consider it a style bug, post a patch to add the
> -Wdeclaration-after-statement flag and/or to detect in checkpatch.pl.
> Until then, things are left to everyone's taste. AFAIU declarations
> after statements are discouraged but not prohibited.
On Sat, Feb 1, 2014 at 12:34 AM, Andreas Färber wrote:
> Replace usages of FROM_I2C_SLAVE() with QOM cast macro.
> Rename parent field.
A nit, but you are also "removing direct pointer derefence casts" [1] ...
>
> Signed-off-by: Andreas Färber
> ---
> hw/audio/wm8750.c | 33 +++
On Sat, Feb 1, 2014 at 12:34 AM, Andreas Färber wrote:
> Replace usages of FROM_I2C_SLAVE() with QOM cast macro.
>
> Signed-off-by: Andreas Färber
Reviewed-by: Peter Crosthwaite
> ---
> hw/arm/z2.c | 18 --
> 1 file changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/hw
On Sat, Feb 1, 2014 at 12:34 AM, Andreas Färber wrote:
> Replace usages of FROM_I2C_SLAVE() with QOM cast macro.
> Rename parent field.
>
> Signed-off-by: Andreas Färber
Reviewed-by: Peter Crosthwaite
> ---
> hw/arm/tosa.c | 16 +++-
> 1 file changed, 11 insertions(+), 5 deletions
On Sat, Feb 1, 2014 at 12:34 AM, Andreas Färber wrote:
> Replace usages of FROM_I2C_SLAVE() with QOM cast macro and rename parent
> field to assure we caught all.
>
> Signed-off-by: Andreas Färber
> ---
> hw/arm/pxa2xx.c | 38 +-
> 1 file changed, 25 insertion
On Sat, Feb 1, 2014 at 12:34 AM, Andreas Färber wrote:
> Hello,
>
> This series prepares for converting I2C to QOM realize.
>
Incase you are moving onto SSI next I do have a have half a start on
this change pattern for SSI (In particular, I think Ive removed
FROM_SSI_SLAVE for some re-org reasons
On Sat, Feb 1, 2014 at 12:34 AM, Andreas Färber wrote:
> Signed-off-by: Andreas Färber
Reviewed-by: Peter Crosthwaite
> ---
> hw/acpi/piix4.c | 6 +++---
> hw/arm/exynos4210.c | 2 +-
> hw/arm/musicpal.c | 4 ++--
> hw/arm/nseries.c| 2 +-
> hw/ar
On 9 February 2014 00:10, Peter Maydell wrote:
> On 8 February 2014 23:33, Paolo Bonzini wrote:
>> Il 08/02/2014 18:28, Andreas Färber ha scritto:
>>> Since when is it OK to declare variables in the middle of the block?
>
>> When the code looks better, it is OK since always: checkpatch.pl doesn't
On 8 February 2014 23:36, Paolo Bonzini wrote:
> Il 08/02/2014 18:46, Peter Maydell ha scritto:
>> It's not obvious why
>> the block layer should be handing argv0 around through bdrv_init
>> in order to (re-?) initialise modules.
>
> The executable directory is not found once and for all, it's rec
On 8 February 2014 23:33, Paolo Bonzini wrote:
> Il 08/02/2014 18:28, Andreas Färber ha scritto:
>> Since when is it OK to declare variables in the middle of the block?
> When the code looks better, it is OK since always: checkpatch.pl doesn't
> complain and -Wdeclaration-after-statement is not a
Il 08/02/2014 18:46, Peter Maydell ha scritto:
This adds parameter "argv0" in calling path from main() to
> module_call_init(). So that module loader knows the location of
> executable.
This patch looks kind of odd to me. Why are there so many
different places calling module_call_init() and pass
Mouse not working in WinXP with QEMU either.
But it is working with bochs (same disk image).
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Title:
lots of dma command 10, 14 not supported
S
Il 08/02/2014 18:28, Andreas Färber ha scritto:
+/* sysenter isn't supported in compatibility mode on AMD,
+ * syscall isn't supported in compatibility mode on Intel.
+ * Normally we advertise the actual CPU vendor, but you can
+ * override this using the 'vendor' property if you
Il 08/02/2014 20:58, Andreas Färber ha scritto:
Patch 03/06 makes it obvious that the header should live somewhere in
include/ for documenting the base QOM type though.
A minimally invasive alternative would be to move it from hw/char/ to
include/hw/char/ - would that be acceptable for everyone
Am 06.08.2013 10:48, schrieb Alberto Garcia:
> On Fri, Aug 02, 2013 at 11:16:55PM +0200, Andreas Färber wrote:
>
>> This series converts IndustryPack devices to QOM realize/unrealize.
>>
>> It goes on to clean up file placement, promoting IndustryPack to use
>> its own subdirectory like PCI, ISA,
i could fix it by explicitly disable xbzrle - it seems its automatically
on if i do not set the migration caps to false.
So it seems to be a xbzrle bug.
Stefan
Am 07.02.2014 21:10, schrieb Stefan Priebe:
Am 07.02.2014 21:02, schrieb Dr. David Alan Gilbert:
* Stefan Priebe (s.pri...@profihost
thank you. Will keep at it.
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https://bugs.launchpad.net/bugs/1276879
Title:
lots of dma command 10, 14 not supported
Status in QEMU:
New
Bug description:
Trying to install NeXTS
I don't know about Bochs but here's another page with resources on running
OPENSTEP on a VM:
http://www.zebpedersen.co.uk/?p=126
The VMWare drivers (both svga and mouse) should work with QEMU too but I don't
know if they are compatible with NeXTSTEP.
Now I remember there was some problem with mou
No luck with msmouse. NextStep assumes a PS/2 mouse, I believe,
which is what QEMU emulates by default. In bochs, the mouse does
work in NextStep. Do you know if bochs emulates the PS/2 mouse
by default?
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On 8 February 2014 04:40, Fam Zheng wrote:
> This adds parameter "argv0" in calling path from main() to
> module_call_init(). So that module loader knows the location of
> executable.
This patch looks kind of odd to me. Why are there so many
different places calling module_call_init() and passing
This option is now unnecessary since specifying BDRV_O_PROTOCOL as flag
will do exactly the same.
Signed-off-by: Max Reitz
---
block.c | 28
block/blkdebug.c | 2 +-
block/blkverify.c | 4 ++--
include/block/block.h | 2 +-
4 files changed,
The fail and success paths of bdrv_file_open() may be further shortened
by reusing code already existent in bdrv_open(). This includes
bdrv_file_open() not taking the reference to options which allows the
removal of QDECREF(options) in that function.
Signed-off-by: Max Reitz
---
block.c | 68 +++
Change bdrv_file_open() to take a simple pointer to an already existing
BDS instead of an indirect one. The BDS will be created in bdrv_open()
if necessary.
Signed-off-by: Max Reitz
---
block.c | 24 +---
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/block.c
Remove the reference parameter and the related handling code from
bdrv_file_open(), since it exists in bdrv_open() now as well.
Signed-off-by: Max Reitz
Reviewed-by: Benoit Canet
---
block.c | 33 +++--
1 file changed, 7 insertions(+), 26 deletions(-)
diff --git a/b
The fail paths of bdrv_file_open() and bdrv_open() naturally exhibit
similarities, thus it is possible to reuse the one from bdrv_open() and
shorten the one in bdrv_file_open() accordingly.
Also, setting bs->options in bdrv_file_open() is not necessary if it is
already done in bdrv_open().
Signed
Allow bdrv_open() to handle references to existing block devices just as
bdrv_file_open() is already capable of.
Signed-off-by: Max Reitz
---
block.c | 41 ++---
block/qcow2.c | 4 ++--
block/vmdk.c | 3 ++-
block/vvfat.c
Add the bdrv_open() option BDRV_O_PROTOCOL which results in passing the
call to bdrv_file_open(). Additionally, make bdrv_file_open() static and
therefore bdrv_open() the only way to call it.
Consequently, all existing calls to bdrv_file_open() have to be adjusted
to use bdrv_open() with the BDRV_
Make bdrv_open() take a pointer to a BDS pointer, similarly to
bdrv_file_open(). If a pointer to a NULL pointer is given, bdrv_open()
will create a new BDS with an empty name; if the BDS pointer is not
NULL, that existing BDS will be reused (in the same way as bdrv_open()
already did).
Signed-off-
bdrv_file_open() is now nearly a subset of bdrv_open(), except for the
fact that bdrv_file_open() is for protocols and bdrv_open() for block
drivers. It is possible to use bdrv_file_open() with a block driver, but
in that case that block driver must be explicitly specified.
Due to these great simi
Am 05.02.2014 15:56, schrieb Igor Mammedov:
> On Wed, 5 Feb 2014 15:30:53 +0100
> Andreas Färber wrote:
>
>> Commit 7426aa72c36c908a7d0eae3e38568bb0a70de479 (nand: Don't inherit
>> from Sysbus) changed the parent type of TYPE_NAND but continued to use
>> qdev_create(), which handled a NULL BusSt
Am 03.02.2014 17:39, schrieb Paolo Bonzini:
> From: Eduardo Habkost
>
> As we will not have a cpu_x86_find_by_name() function anymore,
> move the KVM default-vendor hack to instance_init.
>
> Unfortunately we can't move that code to class_init because it depends
> on KVM being initialized.
>
>
On 08.02.2014, at 18:16, Andreas Färber wrote:
> Am 08.02.2014 05:40, schrieb Fam Zheng:
>> This adds parameter "argv0" in calling path from main() to
>> module_call_init(). So that module loader knows the location of
>> executable.
>>
>> Suggested-by: Paolo Bonzini
>> Signed-off-by: Fam Zheng
Am 31.01.2014 15:34, schrieb Andreas Färber:
> Hello,
>
> This series prepares for converting I2C to QOM realize.
>
> Didn't finish that so far, but I'd like to apply this to qom-next before it
> starts to conflict.
>
> Regards,
> Andreas
>
> Cc: Anthony Liguori
> Cc: Peter Maydell
>
> Andre
Am 08.02.2014 05:40, schrieb Fam Zheng:
> This adds parameter "argv0" in calling path from main() to
> module_call_init(). So that module loader knows the location of
> executable.
>
> Suggested-by: Paolo Bonzini
> Signed-off-by: Fam Zheng
[...]
> diff --git a/bsd-user/main.c b/bsd-user/main.c
>
Instead of making the backing file contents visible again after a discard
request, set the zero flag if possible (i.e. on version >= 3).
Signed-off-by: Kevin Wolf
Reviewed-by: Max Reitz
---
block/qcow2-cluster.c | 22 --
1 file changed, 20 insertions(+), 2 deletions(-)
diff
In order to allow the user to choose the framebuffer for sparc-softmmu, add
-vga tcx and -vga cg3 options to the QEMU command line. If no option is
specified, the default TCX framebuffer is used.
Signed-off-by: Mark Cave-Ayland
CC: Blue Swirl
CC: Anthony Liguori
CC: Peter Maydell
CC: Bob Breue
This patchset provides QEMU with an implementation of the Sun CG3 8-bit
framebuffer. It is based upon Bob Breuer's original work which has been
rebased onto git master, and is now capable of running with an OpenBIOS CG3
FCode ROM instead of requiring copies of proprietary Sun ROMs.
The motivation
The CG3 framebuffer is a simple 8-bit framebuffer for use with operating
systems such as early Solaris that do not have drivers for TCX.
Signed-off-by: Mark Cave-Ayland
CC: Blue Swirl
CC: Anthony Liguori
CC: Peter Maydell
CC: Bob Breuer
CC: Artyom Tarasenko
---
Makefile
ository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20140208
for you to fetch changes up to 69991d7dcbcf7f3fe38274bc67fcba3cbbfda0cf:
arm/zynq: Add software system reset via SCLR (2014-02-08 14:5
We have macros for marking TCGv values as unused, checking if they
are unused and comparing them to each other. However these only exist
for TCGv_i32 and TCGv_i64; add them for TCGv_ptr as well.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
tcg/tcg.h | 3 +++
1 file changed, 3
Am 08.02.2014 um 17:17 hat Max Reitz geschrieben:
> On 08.02.2014 16:28, Kevin Wolf wrote:
> >Instead of making the backing file contents visible again after a discard
> >request, set the zero flag if possible (i.e. on version >= 3).
> >
> >Signed-off-by: Kevin Wolf
> >---
> > block/qcow2-cluster
On 08.02.2014 16:28, Kevin Wolf wrote:
Instead of making the backing file contents visible again after a discard
request, set the zero flag if possible (i.e. on version >= 3).
Signed-off-by: Kevin Wolf
---
block/qcow2-cluster.c | 22 --
1 file changed, 20 insertions(+), 2
From: Claudio Fontana
Use libvixl to implement disassembly output in debug
logs for A64, for use with both AArch64 hosts and targets.
Signed-off-by: Claudio Fontana
[PMM:
* added support for target disassembly
* switched to custom QEMUDisassembler so the output format
matches what QEMU exp
From: Will Newton
Add support for the AArch32 floating-point half-precision to double-
precision conversion VCVTB and VCVTT instructions.
Signed-off-by: Will Newton
[PMM: fixed a minor missing-braces style issue]
Signed-off-by: Peter Maydell
---
target-arm/translate.c | 83 +++
The A64 disassembler libvixl uses .cc as its suffix for
C++ source files, so add support for it (we already support
.cpp).
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
rules.mak | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/rules.mak b/rules.mak
ind
On 08.02.2014 16:28, Kevin Wolf wrote:
Instead of making the backing file contents visible again after a discard
request, set the zero flag if possible (i.e. on version >= 3).
Signed-off-by: Kevin Wolf
---
block/qcow2-cluster.c | 22 --
1 file changed, 20 insertions(+), 2
If we have a C++ compiler available, link with it, because we might be
linking some C++ files in. This allows us to include C++ object files
in the QEMU binary proper.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
rules.mak | 8 ++--
1 file changed, 6 insertions(+), 2 dele
From: Beniamino Galvani
This patch adds support for the Fast Ethernet MAC found on Allwinner
SoCs, together with a basic emulation of Realtek RTL8201CP PHY.
Since there is no public documentation of the Allwinner controller, the
implementation is based on Linux kernel driver.
Signed-off-by: Ben
Fix various minor issues with upstream libvixl so that it will compile
successfully on the platforms QEMU cares about:
* remove unused GBytes constant (it clashes with the glib headers)
* fix suffixes on constants to use 'LL' for 64 bit constants so
we can compile on 32 bit hosts
Signed-off-b
On 4 February 2014 18:58, Michael Walle wrote:
> Hi Peter,
>
> this is a pull request for various updates and fixes for the LatticeMico32
> target.
>
> Please pull.
>
> changes since v4:
> - rebased
> - incorporated all fixes suggested by Peter Maydell during v4 review.
>
> changes since v3:
>
Implement the SIMD 3-reg-same instructions where the size == 3 case
is reserved: SHADD, UHADD, SRHADD, URHADD, SHSUB, UHSUB, SMAX,
UMAX, SMIN, UMIN, SABD, UABD, SABA, UABA, MLA, MLS, MUL, PMUL,
SQRDMULH, SQDMULH. (None of these have scalar-3-same versions.)
This completes the non-pairwise integer i
From: Christoffer Dall
The existing implementation of the pending behavior in gic_set_irq,
gic_complete_irq, and the distributor pending set/clear registers does
not follow the semantics of the GICv2.0 specs, but may implement the
11MPCore support. Therefore, maintain the existing semantics for
From: Christoffer Dall
Add a binary_point field to the gic emulation structure and support
setting/getting this register now when we have it. We don't actually
support interrupt grouping yet, oh well.
Reviewed-by: Peter Maydell
Signed-off-by: Christoffer Dall
Signed-off-by: Peter Maydell
---
Implement the simple 2-register-misc operations we can share
with the scalar-two-register-misc code. (SUQADD, USQADD, SQABS,
SQNEG also fall into this category, but aren't implemented in
the scalar-2-register case yet either.)
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
targ
Add a skeleton decode for the SIMD 2-reg misc group.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 110 -
1 file changed, 109 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate-a64.c b/target
Implement the instructions in the scalar pairwise group (C3.6.8).
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 114 -
1 file changed, 113 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate-a
From: Beniamino Galvani
To improve the predictability of fifo8_pop_buf(), the fifo head is set
to the start of data buffer upon a reset so that the first call to the
function will be able to retrieve all data in the fifo.
Signed-off-by: Beniamino Galvani
Reviewed-by: Peter Crosthwaite
Signed-o
From: Beniamino Galvani
Signed-off-by: Beniamino Galvani
Reviewed-by: Peter Crosthwaite
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
hw/arm/allwinner-a10.c | 16
hw/arm/cubieboard.c| 11 +--
include/hw/arm/allwinner-a10.h | 3 +++
Implement the SIMD 3-reg-same instructions SQADD, UQADD,
SQSUB, UQSUB, SSHL, USHL, SQSHl, UQSHL, SRSHL, URSHL,
SQRSHL, UQRSHL; these are all simple calls to existing
Neon helpers. We also enable SSHL, USHL, SRSHL and URSHL
for the 3-reg-same-scalar category (but not the others
because they can have
From: Christoffer Dall
Add support for saving VMState of 2D arrays of uint32 values.
Reviewed-by: Peter Maydell
Signed-off-by: Christoffer Dall
Signed-off-by: Peter Maydell
---
include/migration/vmstate.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/migration/vmstate.h b
From: Christoffer Dall
The GICC_APRn registers are not currently supported by the ARM GIC v2.0
emulation. This patch adds the missing state.
Note that we also change the number of APRs to use a define GIC_NR_APRS
based on the maximum number of preemption levels. This patch also adds
RAZ/WI acc
Implement the simple 64 bit integer operations from the SIMD
scalar 2-register misc group (C3.6.12): the comparisons against
zero, plus ABS and NEG.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 87 +-
1
Implement the 2-reg-misc CNT, NOT and RBIT instructions.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/helper.h| 1 +
target-arm/neon_helper.c | 12
target-arm/translate-a64.c | 34 --
3 files changed, 41 inser
From: Christoffer Dall
Right now the arm gic emulation doesn't keep track of the source of an
SGI (which apparently Linux guests don't use, or they're fine with
assuming CPU 0 always).
Add the necessary matrix on the GICState structure and maintain the data
when setting and clearing the pending
Implement the pairwise integer operations in the 3-reg-same SIMD group:
ADDP, SMAXP, SMINP, UMAXP and UMINP.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 124 -
1 file changed, 123 insertions(+), 1 delet
Implement the remaining integer instructions in the scalar-three-reg-same
group: SQADD, UQADD, SQSUB, UQSUB, SQSHL, UQSHL, SQRSHL, UQRSHL,
SQDMULH, SQRDMULH.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 106 +---
From: Beniamino Galvani
The patch adds functions fifo8_push_all() and fifo8_pop_buf() which
can be used respectively to push the content of a memory buffer to the
fifo and to pop multiple bytes obtaining a pointer to the fifo backing
buffer.
In addition, it implements fifo8_num_free() and fifo8_
Add the SIMD FNEG and FABS instructions in the SIMD 2-reg-misc group.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 23 ---
1 file changed, 20 insertions(+), 3 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm/t
From: Sebastian Huber
Support software-driven system reset via the register in the SCLR.
Signed-off-by: Sebastian Huber
Reviewed-by: Peter Crosthwaite
Signed-off-by: Peter Maydell
---
hw/misc/zynq_slcr.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/hw/misc/zynq_slcr.c b/hw/misc/z
From: Alex Bennée
Add the byte-reverse operations REV64, REV32 and REV16 from the
two-reg-misc group.
Signed-off-by: Alex Bennée
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 71 +-
1 file changed, 70
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