When we disabling vnc from "./configure", the qemu can't use the vnc option.
So qtest can't use the "vnc -none ", otherwise "make check" will hang.
Signed-off-by: Kewei Yu
---
v2: Consolidate VNC macro's #ifdef'ery to one central point (tests/libqtest.c).
tests/fdc-test.c |5 +
tests/i
On Dec 28, 2013, at 2:00 AM, Artyom Tarasenko wrote:
> Actually QEMU does set variables in NVRAM (hw/sparc/sun4m.c:151), and
> afaik uses the layout of open-sourced OBP. The problem is that earlier
> versions of OBP seemed to have a different layout, or maybe just a
> magic constant is missing som
Hi,
Am 30.12.2013 09:46, schrieb Kewei Yu:
> When we disabling vnc from "./configure", the qemu can't use the vnc option.
> So qtest can't use the "vnc -none ", otherwise "make check" will hang.
>
> Signed-off-by: Kewei Yu
> ---
> tests/fdc-test.c |4
> tests/ide-test.c | 11
Hi folks,
I have been studying QCOW2 file format for a couple of days, and I am
a little bit confused about whether QCOW2 supports UNMAP or not.
As I surf through internet, some mailing list discussion had mentioned
that qemu-nbd and nbd module both support UNMAP command.
So I follow the steps bel
On Mon, Dec 30, 2013 at 12:20 AM, Peter Maydell
wrote:
> The code which decides whether to set up the ATAGS data structure on
> reset was using the wrong conditional, which meant we were creating
> an ATAGS structure when doing a device-tree boot if the dtb was
> autogenerated by the board. This i
On 12/30/2013 08:34 AM, Peter Maydell wrote:
> The A64 128 bit vector registers are stored as a pair of
> uint64_t values in the register array. This means that if
> we're directly loading or storing a value of size less than
> 64 bits we must adjust the offset appropriately to account
> for whethe
On 12/30/2013 08:34 AM, Peter Maydell wrote:
> From: Alexander Graf
>
> When dumping the current CPU state, we can also get a request
> to dump the FPU state along with the CPU's integer state.
>
> Add support to dump the VFP state when that flag is set, so that
> we can properly debug code that
The A64 128 bit vector registers are stored as a pair of
uint64_t values in the register array. This means that if
we're directly loading or storing a value of size less than
64 bits we must adjust the offset appropriately to account
for whether the host is bigendian or not. Provide utility
functio
From: Claudio Fontana
This adds decoding support for C3.6.24 FP conditional select.
Signed-off-by: Claudio Fontana
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 45 -
1 file changed, 44 insertions(+),
From: Claudio Fontana
Add decoding support for C3.6.22 Floating-point compare.
Signed-off-by: Claudio Fontana
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/helper-a64.c| 45
target-arm/helper-a64.h| 4 +++
target-arm/tran
From: Alexander Graf
This patch adds emulation for the "Floating-point data-processing (2 source)"
group of instructions.
Signed-off-by: Alexander Graf
[WN: Commit message tweak, merge single and double precision patches. Rebase
and update to new infrastructure. Incorporate FMIN/FMAX support p
From: Alexander Graf
When dumping the current CPU state, we can also get a request
to dump the FPU state along with the CPU's integer state.
Add support to dump the VFP state when that flag is set, so that
we can properly debug code that modifies floating point registers.
Signed-off-by: Alexand
From: Alexander Graf
This patch adds emulation for the "Floating-point data-processing (3 source)"
group of instructions.
Signed-off-by: Alexander Graf
[WN: Commit message tweak, merged single and double precision patches.
Implement using muladd as suggested by Richard Henderson.]
Signed-off-b
From: Claudio Fontana
This adds decoding support for C3.6.23 FP Conditional Compare.
Signed-off-by: Claudio Fontana
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 35 ++-
1 file changed, 34 insertions(+), 1 deletio
Use the VFP_BINOP macro to provide helpers for min, max, minnum
and maxnum, rather than hand-rolling them. (The float64 max
version is not used by A32 but will be needed for A64.)
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/helper.c | 29 -
From: Alexander Graf
This patch adds emulation for the fmov instruction working on scalars
with an immediate payload.
Signed-off-by: Alexander Graf
[WN: Commit message tweak, rebase and use new infrastructure.]
Signed-off-by: Will Newton
Signed-off-by: Peter Maydell
Reviewed-by: Richard Hende
FP support patchset. Changes v1->v2:
patch 1: correct format string, argument order issues
patch 2: simplify do_fp_st by always loading 64 bits from the
vfp regs entry
patches 3-10 unchanged; all have been reviewed.
This patchset sits on top of the previous one (now almost entirely
coderevie
From: Alexander Graf
When setting rounding modes we currently just hardcode the numeric values
for rounding modes in a big switch statement.
With AArch64 support coming, we will need to refer to these rounding modes
at different places throughout the code though, so let's better give them
names
On 12/30/2013 07:43 AM, Alexander Graf wrote:
> Yes you can, but we only expose 64bit capable cpus with TARGET_PPC64 defined.
> You couldn't select them with the 32bit target.
Ah, well. That answers my question then, really.
r~
> Am 30.12.2013 um 15:48 schrieb Richard Henderson :
>
>> On 12/27/2013 04:23 PM, Scott Wood wrote:
>>> On Tue, 2013-12-24 at 07:17 -0800, Richard Henderson wrote:
On 12/18/2013 12:48 PM, Tom Musta wrote:
+DEF_HELPER_3(bpermd, i64, env, i64, i64)
>>>
>>> Should be DEF_HELPER_FLAGS_2(b
On 12/30/2013 07:28 AM, Peter Maydell wrote:
> Yeah, we could do that. Will the optimiser optimise away the unnecessary
> extra load of the unused high 32 bits for the "32 bit or smaller" case on
> a 32 bit host CPU?
It should.
We do transform qemu_st_i64 to qemu_st_i32 as appropriate for 32-bit
On 12/28/2013 01:49 PM, Peter Maydell wrote:
> From: Alexander Graf
>
> When setting rounding modes we currently just hardcode the numeric values
> for rounding modes in a big switch statement.
>
> With AArch64 support coming, we will need to refer to these rounding modes
> at different places t
On 30 December 2013 15:03, Richard Henderson wrote:
> On 12/28/2013 01:49 PM, Peter Maydell wrote:
>> if (size < 4) {
>> switch (size) {
>> case 0:
>> -tcg_gen_ld8u_i64(tmp, cpu_env, freg_offs);
>> +tcg_gen_ld8u_i64(tmp, cpu_env, fp_reg_offset(srcidx,
On 12/28/2013 01:49 PM, Peter Maydell wrote:
> From: Claudio Fontana
>
> This adds decoding support for C3.6.24 FP conditional select.
>
> Signed-off-by: Claudio Fontana
> Signed-off-by: Peter Maydell
> ---
> target-arm/translate-a64.c | 45 -
> 1 f
On 12/28/2013 01:49 PM, Peter Maydell wrote:
> From: Claudio Fontana
>
> This adds decoding support for C3.6.23 FP Conditional Compare.
>
> Signed-off-by: Claudio Fontana
> Signed-off-by: Peter Maydell
> ---
> target-arm/translate-a64.c | 35 ++-
> 1 file chang
On 12/28/2013 01:49 PM, Peter Maydell wrote:
> From: Claudio Fontana
>
> Add decoding support for C3.6.22 Floating-point compare.
>
> Signed-off-by: Claudio Fontana
> Signed-off-by: Peter Maydell
> ---
> target-arm/helper-a64.c| 45
> target-arm/helper-a64
On 12/28/2013 01:49 PM, Peter Maydell wrote:
> From: Alexander Graf
>
> This patch adds emulation for the fmov instruction working on scalars
> with an immediate payload.
>
> Signed-off-by: Alexander Graf
> [WN: Commit message tweak, rebase and use new infrastructure.]
> Signed-off-by: Will New
On 30 December 2013 14:58, Richard Henderson wrote:
> On 12/28/2013 01:49 PM, Peter Maydell wrote:
>> +uint64_t vlo = float64_val(env->vfp.regs[i * 2]);
>> +uint64_t vhi = float64_val(env->vfp.regs[(i * 2) + 1]);
>> +cpu_fprintf(f, "q%02d.0=%016" PRIx64 ":%016"
On 12/30/2013 07:15 AM, Richard Henderson wrote:
> On 12/28/2013 01:49 PM, Peter Maydell wrote:
>> +/* These are fused multiply-add, and must be done as one
>> + * floating point operation with no rounding between the
>> + * multiplication and addition steps.
>> + * NB that doing th
On 12/28/2013 01:49 PM, Peter Maydell wrote:
> +/* These are fused multiply-add, and must be done as one
> + * floating point operation with no rounding between the
> + * multiplication and addition steps.
> + * NB that doing the negations here as separate steps is
> + * correct
On 12/28/2013 01:49 PM, Peter Maydell wrote:
> From: Alexander Graf
>
> This patch adds emulation for the "Floating-point data-processing (2 source)"
> group of instructions.
>
> Signed-off-by: Alexander Graf
> [WN: Commit message tweak, merge single and double precision patches. Rebase
> and
PIIX4 errata says that "immediate polling of the Host Status Register BUSY
bit may indicate that the SMBus is NOT busy."
This fixes some code which does the following steps:
(a) set parameters
(b) start command
(c) check for smbus busy bit set (to know that command started)
(d) check for smbus bus
On 12/28/2013 01:49 PM, Peter Maydell wrote:
> Use the VFP_BINOP macro to provide helpers for min, max, minnum
> and maxnum, rather than hand-rolling them. (The float64 max
> version is not used by A32 but will be needed for A64.)
>
> Signed-off-by: Peter Maydell
> ---
> target-arm/helper.c
On 12/28/2013 01:49 PM, Peter Maydell wrote:
> if (size < 4) {
> switch (size) {
> case 0:
> -tcg_gen_ld8u_i64(tmp, cpu_env, freg_offs);
> +tcg_gen_ld8u_i64(tmp, cpu_env, fp_reg_offset(srcidx, MO_8));
> break;
> case 1:
> -
On 12/28/2013 01:49 PM, Peter Maydell wrote:
> +uint64_t vlo = float64_val(env->vfp.regs[i * 2]);
> +uint64_t vhi = float64_val(env->vfp.regs[(i * 2) + 1]);
> +cpu_fprintf(f, "q%02d.0=%016" PRIx64 ":%016" PRIx64 " ",
> +i, vlo, vhi);
Why
On 12/27/2013 04:23 PM, Scott Wood wrote:
> On Tue, 2013-12-24 at 07:17 -0800, Richard Henderson wrote:
>> On 12/18/2013 12:48 PM, Tom Musta wrote:
>>> +DEF_HELPER_3(bpermd, i64, env, i64, i64)
>>
>> Should be DEF_HELPER_FLAGS_2(bpermd, TCG_CALL_NO_RWG_SE, i64, i64, i64)
>>
>>> +uint64_t helper_bpe
On 12/28/2013 08:47 AM, Peter Maydell wrote:
> Assuming the fields
> it accesses aren't also being used for TCG memory globals,
> presumably NO_RWG_SE if the field is only read, and
> NO_RWG if it's written?
Correct.
r~
On Mon, Dec 30, 2013 at 12:51 AM, Olivier Danet wrote:
> On SparcStations, the HostID field in the NVRAM is equal to the
> last three bytes of the MAC address (which is also stored in the NVRAM).
>
> This constant is used as an identification/serial number on Solaris.
>
> signed-off-by : Olivier D
When we disabling vnc from "./configure", the qemu can't use the vnc option.
So qtest can't use the "vnc -none ", otherwise "make check" will hang.
Signed-off-by: Kewei Yu
---
tests/fdc-test.c |4
tests/ide-test.c | 11 ---
2 files changed, 12 insertions(+), 3 deletions(-)
di
Fix incorrect bits of offsets in refcount table entry, l1 table
entry and l2 table entry. See REFT_OFFSET_MASK, L1E_OFFSET_MASK
and L2E_OFFSET_MASK.
Fix a typo while at the file.
Signed-off-by: Hu Tao
---
v2: update comments as well.
docs/specs/qcow2.txt | 14 +++---
1 file changed, 7
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