Public bug reported:
1.7.0 seems to have broken booting on SPARC ... at least with a Sun ROM.
Everything fails with "data access exception." 1.6.{1,2} qemu-system-sparc
binaries both boot the same images that 1.7.0 fails to boot.
Type help for more information
ok boot disk1
Boot device: /i
On Tue, Dec 17, 2013 at 12:15:15PM +, Peter Maydell wrote:
> This patchset adds support for basic AArch64 KVM VM control;
> it's based on current master. This is a quick resend with the very
> minor nits Christoffer pointed out fixed; I'm planning to put it into
> a target-arm pullreq in the ne
From: "Michael R. Hines"
As far as we can tell, all known bugs have been fixed:
1. Parallel migrations are working
2. IPv6 migration is working
3. virt-test is working
I'm not comfortable sending the revised libvirt patch
until this is accepted or review suggestions are addressed,
(including pi
On (Tue) 17 Dec 2013 [11:12:02], Gal Hammer wrote:
> On 16/12/2013 22:32, Amit Shah wrote:
> >On (Sun) 15 Dec 2013 [12:26:37], Gal Hammer wrote:
> >>Fix a bug that was introduced in commit 386a5a1e. A removal of a device
> >>set the chr handlers to NULL. However when the device is plugged back,
> >
why is QEMU TLB organized based on the modes, e.g. on x86 there are 3
modes. what i think is that there may be conflicts between virtual
addresses and physical addresses. organizing it by modes guarantees
that QEMU does not hit a physical address translation entry when in
user mode and vice versa ?
Hello, any comments? I hope to have a new year gift
> Am 17.12.2013 um 18:32 schrieb "Daniel P. Berrange" :
>
>> On Tue, Dec 17, 2013 at 10:15:25AM +0100, Peter Lieven wrote:
>> This patch adds native support for accessing images on NFS shares without
>> the requirement to actually mount the entire NFS share on the host.
>>
>> NFS Images can sim
> Am 17.12.2013 um 17:53 schrieb ronnie sahlberg :
>
> NFSTask
>
> Task is a very scsi-ish term. Maybe RPC is better ?
>
> NFSrpc ?
will change it in v3
>
>
>
>> On Tue, Dec 17, 2013 at 1:15 AM, Peter Lieven wrote:
>> This patch adds native support for accessing images on NFS shares with
> Am 17.12.2013 um 18:28 schrieb ronnie sahlberg :
>
>> On Tue, Dec 17, 2013 at 9:03 AM, Peter Lieven wrote:
>>> On 17.12.2013 17:47, Stefan Hajnoczi wrote:
>>>
>>> On Tue, Dec 17, 2013 at 10:15:25AM +0100, Peter Lieven wrote:
>
> ...
+if (nfs_pwrite_async(client->context, client->fh
Hi Anthony,
I'm thinking about converting the error reporting in assigned_initfn()
[hw/i386/kvm/pci-assign.c] from error_report() to qerror_report[_err]().
Internally I might use error propagation, but I don't intend to convert
pci-assign from qdev to QOM / true realizefn. (I intend to *re*-try
e
From: Alexander Graf
Add support for the instructions described in "C3.5.10 Logical
(shifted register)".
We store the flags in the same locations as the 32 bit decoder.
This is slightly awkward when calculating 64 bit results, but seems
a better tradeoff than having to rework the whole 32 bit de
From: Roy Franz
Rename the 'width' member of the pflash_t structure
in preparation for adding a bank_width member.
Signed-off-by: Roy Franz
Reviewed-by: Peter Maydell
Message-id: 1386279359-32286-2-git-send-email-roy.fr...@linaro.org
Signed-off-by: Peter Maydell
---
hw/block/pflash_cfi01.c |
From: Antony Pavlov
Add an ARM CPU property for the reset value of hivecs as it is a
board/SoC configurable setting.
The existence of the property is conditional on the ARM CPU not being M
class.
Signed-off-by: Antony Pavlov
Signed-off-by: Peter Crosthwaite
Message-id:
b04216c6bda4bd163f44a5
> Am 17.12.2013 um 23:51 schrieb ronnie sahlberg :
>
>> On Tue, Dec 17, 2013 at 2:36 PM, Peter Lieven wrote:
>>
>>
Am 17.12.2013 um 18:13 schrieb ronnie sahlberg :
On Tue, Dec 17, 2013 at 9:03 AM, Peter Lieven wrote:
On 17.12.2013 17:47, Stefan Hajnoczi wrote:
>>> ...
>>
This change moves host OS and arch dependent code for the sysarch
system call related to the -strace functionality into the
appropriate host OS and target arch directories.
---
bsd-user/arm/syscall.h | 36 +++
bsd-user/arm/target_arch_sysarch.h | 78 ++
bsd-
On Tue, Dec 17, 2013 at 11:42:42AM +, Peter Maydell wrote:
> On 17 December 2013 04:45, Christoffer Dall
> wrote:
> > I think this could be written slightly more clearly for the uninitiated,
> > but maybe I'm just not qemu-savy enough.
>
> It was a bit compressed; I've reworded it to:
>
Update FreeBSD system call numbers in freebsd/syscall_nr.h.
Reviewed-by: Ed Maste
---
bsd-user/freebsd/syscall_nr.h | 813 ++---
1 files changed, 445 insertions(+), 368 deletions(-)
diff --git a/bsd-user/freebsd/syscall_nr.h b/bsd-user/freebsd/syscall_nr.h
i
On Tue, 17 Dec 2013, Peter Maydell wrote:
> On 17 December 2013 17:30, Stefano Stabellini
> wrote:
> > Signed-off-by: Stefano Stabellini
> > ---
> > hw/xen/xen_backend.c | 18 ++
> > include/hw/xen/xen_backend.h |2 ++
> > 2 files changed, 20 insertions(+)
> >
> > d
This change adds HOST_VARIANT_DIR so the various BSD OS dependent
code can be seperated into its own directories rather than
using #ifdef's. This may also allow an BSD variant OS to host
another BSD variant's executible as a target.
---
Makefile.target |3 ++-
configure | 11
From: Roy Franz
This change fixes the CFI query responses to handle NOR device
widths that are different from the bank width. Support is also
added for multi-width devices in a x8 configuration. This is
typically x8/x16 devices, but the CFI specification mentions
x8/x32 devices so those should
On Tue, Dec 17, 2013 at 4:38 AM, Paolo Bonzini wrote:
> Il 17/12/2013 00:26, Anthony Liguori ha scritto:
>> Sharing hot plug code is a good thing. Making hotplug a qdev-level
>> concept seems like a bad thing to me.
>
> Can you explain what you mean?
The question is whether "hotpluggable" as a p
From: Alexander Graf
This patch adds emulation for the conditional branch (b.cond) instruction.
Signed-off-by: Alexander Graf
[claudio: adapted to new decoder structure,
reused arm infrastructure for checking the flags]
Signed-off-by: Claudio Fontana
Signed-off-by: Peter Maydell
Rev
On 12/16/2013 03:48 AM, Gerd Hoffmann wrote:
> It's missing.
>
> Signed-off-by: Gerd Hoffmann
> ---
> qapi-schema.json | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Another case worth documenting as 'since 2.0', and probably worth
backporting to stable branches.
>
> diff --git a/qap
From: Peter Crosthwaite
To allow the machine model to set device properties before CPU
realization.
Signed-off-by: Peter Crosthwaite
Reviewed-by: Peter Maydell
Message-id:
8c671e500390c8be0cc363e887e32867d1d1b0d2.1387160489.git.peter.crosthwa...@xilinx.com
Signed-off-by: Peter Maydell
---
h
From: "Mian M. Hamayun"
Add the bare minimum set of functions needed for control of an
AArch64 KVM vcpu:
* CPU initialization
* minimal get/put register functions which only handle the
basic state of the CPU
Signed-off-by: Mian M. Hamayun
Signed-off-by: Peter Maydell
Message-id: 138564560
On Tue, Dec 17, 2013 at 2:36 PM, Peter Lieven wrote:
>
>
>> Am 17.12.2013 um 18:13 schrieb ronnie sahlberg :
>>
>>> On Tue, Dec 17, 2013 at 9:03 AM, Peter Lieven wrote:
>>> On 17.12.2013 17:47, Stefan Hajnoczi wrote:
>> ...
Which NFS protocol versions are supported by current libnfs?
>>>
>>>
From: liguang
Signed-off-by: liguang
Reviewed-by: Peter Crosthwaite
Reviewed-by: Peter Maydell
Message-id: 1387159292-10436-4-git-send-email-lig.f...@cn.fujitsu.com
Signed-off-by: Peter Maydell
---
default-configs/arm-softmmu.mak | 1 +
hw/intc/Makefile.objs | 1 +
hw/i
From: Alexander Graf
Add support for the instructions described in
"C3.4.6 PC-rel. addressing" (ADR and ADRP).
Signed-off-by: Alexander Graf
[claudio: adapted to new decoder structure]
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
Signed-off-by: Peter Maydell
---
target-arm/
From: Thomas Huth
I missed to set the CC in the CHSC instruction when I refactored
the CC setting in the IO instructions with the following commit:
5d9bf1c07c1369ab3506fc82cc65a10f4415d867
s390/ioinst: Moved the CC setting to the IO instruction handlers
This patch now restores the
This change add support for extended attribute and Access
Control List (ACL) related system calls including extattrctl(),
extattr_set_file(2), extattr_delete_file(2), extattr_set_fd(2),
extattr_get_fd(2), extattr_delete_fd(2), extattr_get_link(2),
extattr_set_link(2), extattr_delete_link(2), extatt
The A32/T32 gen_intermediate_code_internal() is complicated because it
has to deal with:
* conditionally executed instructions
* Thumb IT blocks
* kernel helper page
* M profile exception-exit special casing
None of these apply to A64, so putting the "this is A64 so
call the A64 decoder" check
From: liguang
Signed-off-by: liguang
Reviewed-by: Peter Crosthwaite
Message-id: 1387159292-10436-5-git-send-email-lig.f...@cn.fujitsu.com
Signed-off-by: Peter Maydell
---
default-configs/arm-softmmu.mak | 1 +
hw/arm/Makefile.objs| 1 +
hw/arm/allwinner-a10.c | 103 ++
From: Roy Franz
Fix NOR flash manufacturer and device ID reading. This now
properly takes into account device widths and device max widths
as required. The reading of these IDs uses the same max_width
dependent addressing as CFI queries.
The old code remains for chips that don't specify a devi
This change adds support or stubs for file system (except stat)
related system calls including read(2), pread(2), readv(2),
write(2), pwrite(2), writev(2), pwritev(2), open(2), openat(2),
close(2), closefrom(2), revoke(2), access(2), eaccess(2),
faccessat(2), chdir(2), fchdir(2), rename(2), rename
On 12/17/2013 03:36 PM, Peter Lieven wrote:
>
>
>> Am 17.12.2013 um 18:13 schrieb ronnie sahlberg :
>>
>>> On Tue, Dec 17, 2013 at 9:03 AM, Peter Lieven wrote:
>>> On 17.12.2013 17:47, Stefan Hajnoczi wrote:
>> ...
Which NFS protocol versions are supported by current libnfs?
>>>
>>> Will ch
From: Roy Franz
Now that we know how wide each flash device that makes up the bank is,
return status for each device in the bank. Leave existing code
that treats 32 bit wide banks as composed of two 16 bit devices as otherwise
we may break configurations that do not set the device_width propery.
From: Alexander Graf
This patch adds emulation for the test and branch insns,
TBZ and TBNZ.
Signed-off-by: Alexander Graf
[claudio:
adapted for new decoder
always compare with 0
remove a TCG temporary
]
Signed-off-by: Claudio Fontana
Signed-off-by: Peter Maydell
Reviewed-by: Richard Hen
From: Claudio Fontana
This patch adds support for the instruction group "C3.5.6
Conditional select": CSEL, CSINC, CSINV, CSNEG.
Signed-off-by: Claudio Fontana
[PMM: Improved code generated in the nomatch case as per RTH suggestions]
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
From: Antony Pavlov
DIGIC is Canon Inc.'s name for a family of SoC
for digital cameras and camcorders.
There is no publicly available specification for
DIGIC chips. All information about DIGIC chip
internals is based on reverse engineering efforts
made by CHDK (http://chdk.wikia.com) and
Magic L
From: Alexander Graf
This patch adds support for decoding 2-src data processing insns,
and the first users, UDIV and SDIV.
Signed-off-by: Alexander Graf
[claudio: adapted to new decoder adding the 2-src decoding level,
always zero-extend result in 32bit mode]
Signed-off-by: Claudio Fo
From: Claudio Fontana
This adds support for C5.6.149 REV, C5.6.151 REV32, C5.6.150 REV16.
Signed-off-by: Claudio Fontana
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 73 +-
1 file changed, 72 insertio
From: Peter Crosthwaite
The reset value of the CP15 CBAR is a vendor (machine) configurable
property. If ARM_FEATURE_CBAR is set, add it as a property at
post_init time.
Signed-off-by: Peter Crosthwaite
Message-id:
2f1eec3f912135deea6252360e03645003d12e0a.1387160489.git.peter.crosthwa...@xilin
From: Claudio Fontana
this patch adds support for the CLS instruction.
Signed-off-by: Claudio Fontana
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/helper-a64.c| 10 ++
target-arm/helper-a64.h| 2 ++
target-arm/translate-a64.c | 20 ++
Am 17.12.2013 19:41, schrieb Jeff Cody:
> The man page for qemu-img, and the qemu-doc, did not mention VHDX
> as a supported format. This adds in reference to VHDX in those
> documents.
>
> Signed-off-by: Jeff Cody
> ---
> qemu-doc.texi | 15 +++
> qemu-img.texi | 4 ++--
> 2 files
From: Claudio Fontana
this patch introduces wrappers for the clrsb builtins,
which count the leading redundant sign bits.
Signed-off-by: Claudio Fontana
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
include/qemu/host-utils.h | 32
1 file cha
From: "Mian M. Hamayun"
This commit adds support for booting a single AArch64 CPU by setting
appropriate registers. The bootloader includes placeholders for Board-ID
that are used to implement uniform indexing across different bootloaders.
Signed-off-by: Mian M. Hamayun
Signed-off-by: Peter May
From: Claudio Fontana
This patch adds support for decoding 1-src data processing insns,
and the first user, C5.6.40 CLZ (count leading zeroes).
Signed-off-by: Claudio Fontana
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/helper-a64.c| 5 +
target-arm/hel
From: liguang
Signed-off-by: liguang
Reviewed-by: Peter Crosthwaite
Message-id: 1387159292-10436-6-git-send-email-lig.f...@cn.fujitsu.com
Signed-off-by: Peter Maydell
---
hw/arm/Makefile.objs | 2 +-
hw/arm/cubieboard.c | 69
tests/qom-te
> Am 17.12.2013 um 18:13 schrieb ronnie sahlberg :
>
>> On Tue, Dec 17, 2013 at 9:03 AM, Peter Lieven wrote:
>> On 17.12.2013 17:47, Stefan Hajnoczi wrote:
> ...
>>> Which NFS protocol versions are supported by current libnfs?
>>
>> Will check that out. Ronnie?
>
> It uses NFS v3 only.
shoul
From: Antony Pavlov
Also this patch adds initial support for Canon
PowerShot A1100 IS compact camera.
Signed-off-by: Antony Pavlov
Message-id: 1387188908-754-3-git-send-email-antonynpav...@gmail.com
Signed-off-by: Peter Maydell
---
hw/arm/Makefile.objs | 1 +
hw/arm/digic_boards.c | 84
On Tue, Dec 17, 2013 at 07:51:49PM +0100, Stefan Weil wrote:
> Am 17.12.2013 19:41, schrieb Jeff Cody:
> > The man page for qemu-img, and the qemu-doc, did not mention VHDX
> > as a supported format. This adds in reference to VHDX in those
> > documents.
> >
> > Signed-off-by: Jeff Cody
> > ---
>
Am 17.12.2013 19:05, schrieb Eric Blake:
> On 12/17/2013 08:25 AM, Juan Quintela wrote:
>> Move index and size fields from int to long. We need that for
>> migration. long is 64 bits on sane architectures, and 32bits should
>> be enough on all the 32bits architectures.
Does this also work for "
From: Alexander Graf
Implement BR, BLR and RET. This is all of the 'unconditional
branch (register)' instruction category except for ERET
and DPRS (which are system mode only).
Signed-off-by: Alexander Graf
[claudio: reimplemented on top of new decoder structure]
Signed-off-by: Claudio Fontana
From: Roy Franz
Create vexpress specific pflash registration
function which properly configures the device-width
of 16 bits (2 bytes) for the NOR flash on the
vexpress platform. This change is required for
buffered flash writes to work properly.
Signed-off-by: Roy Franz
Message-id: 1386279359-
From: Alexander Graf
This patch adds support for C3.4.4 Logical (immediate),
which include AND, ANDS, ORR, EOR.
Signed-off-by: Alexander Graf
[claudio: adapted to new decoder, function renaming,
removed a TCG temp variable]
Signed-off-by: Claudio Fontana
[PMM: cleaned up some unneces
This change adds support or stubs for memory management related
system calls including mmap(2), munmap(2), mprotect(2), msync(2),
mlock(2), munlock(2), mlockall(2), munlockall(2), madvise(2),
minherit(2), mincore(2), shm_open(2), shm_unlink(2), shmget(2),
shmctl(2), shmat(2), shmdt(2), vadvise(), s
On 17 December 2013 18:20, Stefano Stabellini
wrote:
> On Tue, 17 Dec 2013, Peter Maydell wrote:
>> Per-host-architecture ifdef ladders are kind of nasty. What's this
>> code actually trying to do ? (looks like maybe "64 bit host addresses
>> vs 32 bit host addresses" ?)
>
> Almost.
> It is trying
From: Antony Pavlov
If hivecs are being used on reset, the CPU should come out of reset at
the hivecs reset vector (0x)
Signed-off-by: Antony Pavlov
Signed-off-by: Peter Crosthwaite
Message-id:
3afc69c4f58f60aa2bbee7b91574a4eb414b1c23.1387160489.git.peter.crosthwa...@xilinx.com
[ PC C
From: Alexander Graf
This patch adds emulation for the compare and branch insns,
CBZ and CBNZ.
Signed-off-by: Alexander Graf
[claudio: adapted to new decoder,
compare with immediate 0,
introduce read_cpu_reg to get the 0 extension on (!sf)]
Signed-off-by: Claudio Fontana
Si
Add support for defining a vmstate field which is an array
of pointers to structures, and use this to define a
VMSTATE_PTIMER_ARRAY() which allows an array of ptimer_state*
to be used by devices.
Signed-off-by: Peter Maydell
Message-id: 1387159292-10436-2-git-send-email-lig.f...@cn.fujitsu.com
--
On 17 December 2013 17:45, Peter Maydell wrote:
> I'm partway through fixing this bug in an implementation of
> float*_to_uint16 which the ARM AArch64 needs. I think the
> cleanest approach to this looks like this:
>
> uint32 float64_to_uint32( float64 a STATUS_PARAM )
> {
> int64_t v;
> u
From: Alexander Graf
This adds 2-src variable shift register instructions:
C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV
Signed-off-by: Alexander Graf
[claudio: adapted to new decoder, use enums for shift types]
Signed-off-by: Claudio Fontana
Signed-off-by: Peter Maydell
Reviewed-
The env->pstate field is a little odd since it doesn't strictly
speaking represent an architectural register. However it's convenient
for QEMU to use it to hold the various PSTATE architectural bits
in the same format the architecture specifies for SPSR registers
(since this is the same format the
Am 17.12.2013 19:56, schrieb Jeff Cody:
> The man page for qemu-img, and the qemu-doc, did not mention VHDX
> as a supported format. This adds in reference to VHDX in those
> documents.
>
> Signed-off-by: Jeff Cody
> ---
> qemu-doc.texi | 15 +++
> qemu-img.texi | 4 ++--
> 2 files
From: Peter Crosthwaite
The cp15.c15 space is implementation defined. Currently there is a
dummy placeholder register RAZing it. Allow overriding of this RAZ
so implementations of specific registers can take precedence.
Signed-off-by: Peter Crosthwaite
Reviewed-by: Peter Maydell
Message-id:
e
From: Roy Franz
The width of the devices that make up the flash interface
is required to mask certain commands, in particular the
write length for buffered writes. This length will be presented
to each device on the interface by the program writing the flash,
and the flash emulation code needs t
From: Claudio Fontana
This patch implements the C3.4.2 Bitfield instructions:
SBFM, BFM, UBFM.
Signed-off-by: Claudio Fontana
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 56 --
1 file changed, 54 ins
This change adds support or stubs for socket related system calls
including accept(2), bind(2), connect(2), getpeername(2),
getsockname(2), getsockopt(2), setsockopt(2), listen(2),
recvfrom(2), recvmsg(2), sendmsg(2), sendto(2), socket(2),
socketpair(2), shutdown(2), setfib(2), sctp_peeloff(2),
sct
Split ARM KVM support code which is 32 bit specific out into its
own file, which we only compile on 32 bit hosts. This will give
us a place to add the 64 bit support code without adding lots of
ifdefs to kvm.c.
Signed-off-by: Peter Maydell
Message-id: 1385645602-18662-2-git-send-email-peter.mayd.
Enable KVM if the host and target CPU are both aarch64. Note
that host aarch64 + target arm is not valid for KVM acceleration:
the 64 bit kernel does not support the ioctl interface for
32 bit CPUs. 32 bit VMs on 64 bit hosts need to be created
using the 64 bit ioctl interface; when QEMU supports t
From: Alexander Graf
This adds support for the C5.6.147 RBIT instruction.
Signed-off-by: Alexander Graf
[claudio: adapted to new decoder, use bswap64,
make RBIT part standalone from the rest of the patch,
splitting REV into a separate patch]
Signed-off-by: Claudio Fontana
S
From: Antony Pavlov
Signed-off-by: Antony Pavlov
Reviewed-by: Peter Crosthwaite
Message-id: 1387188908-754-4-git-send-email-antonynpav...@gmail.com
Signed-off-by: Peter Maydell
---
hw/arm/digic.c | 28 +++
hw/timer/Makefile.objs | 1 +
hw/timer/digic-timer.c
Eric Blake wrote:
> On 12/17/2013 08:25 AM, Juan Quintela wrote:
>> Move index and size fields from int to long. We need that for
>> migration. long is 64 bits on sane architectures, and 32bits should
>> be enough on all the 32bits architectures.
>>
>> Signed-off-by: Juan Quintela
>> ---
>> i
From: Peter Crosthwaite
Some processors (notably A9 within Highbank) define and use the
CP15 configuration base address (CBAR). This is vendor specific
so its best implemented as a CPU property (otherwise we would need
vendor specific child classes for every ARM implementation).
This patch prepa
This change adds support or stubs for stat, directory, and file
control related system calls including stat(2), lstat(2),
fstat(2), fstatat(2), nstat(), nfstat(), nlstat(), getfh(2),
lgetfh(2), fhopen(2), fhstat(2), fhstatfs(2), statfs(2),
fstatfs(2), getfsstat(2), getdents(2), getdirentries(2), an
The man page for qemu-img, and the qemu-doc, did not mention VHDX
as a supported format. This adds in reference to VHDX in those
documents.
Signed-off-by: Jeff Cody
---
qemu-doc.texi | 15 +++
qemu-img.texi | 4 ++--
2 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/q
If the guest is running in nested mode on system reset, clearing the
feature MSR signals the kernel to leave this mode. Recent kernels
processes this properly, but leave the VCPU state undefined behind. It
is the job of userspace to bring it to a proper shape. Therefore, write
this specific MSR fir
From: Peter Crosthwaite
Fix the CBAR initialisation by using the newly defined static property.
CBAR is now set before realization, so the intended value is now
actually used.
So I have kind of tested this. I booted an ARM kernel on Highbank with
the stock Highbank DTB. It doesn't boot (and I wi
On Tue, Dec 17, 2013 at 11:07 PM, Markus Armbruster wrote:
> Peter Crosthwaite writes:
>
>> On Tue, Dec 17, 2013 at 10:24 PM, Paolo Bonzini wrote:
>>> Il 17/12/2013 12:54, Peter Crosthwaite ha scritto:
> +visit_start_struct(opts_get_visitor(ov), &dummy, NULL, NULL, 0,
> &err);
>
From: Alexander Graf
This patch adds emulation support for the EXTR instruction.
Signed-off-by: Alexander Graf
[claudio: adapted for new decoder, removed a few temporaries,
fixed the 32bit bug, added checks for more
unallocated cases]
Signed-off-by: Claudio Fontana
Signed
For AArch64 we will obviously require a different set of
primary and secondary boot loader code fragments. However currently
we hardcode the offsets into the loader code where we must write
the entrypoint and other data into arm_load_kernel(). This makes it
hard to substitute a different loader fra
From: Peter Crosthwaite
To allow the machine model to set device properties before CPU
realization.
Signed-off-by: Peter Crosthwaite
Reviewed-by: Peter Maydell
Message-id:
e57658b4506b26ab6b6fadbe6d7827f669f51895.1387160489.git.peter.crosthwa...@xilinx.com
Signed-off-by: Peter Maydell
---
h
From: Claudio Fontana
Decode the various kinds of system instructions:
hints (HINT), which include NOP, YIELD, WFE, WFI, SEV, SEL
sync instructions, which include CLREX, DSB, DMB, ISB
msr_i, which move immediate to processor state field
sys, which include all SYS and SYSL instructions
msr, w
FreeBSD has it's own AES_set_decrypt_key, etc. in libcrypto. This
change fixes these conflicts and allows statically linking BSD
user mode qemu.
---
include/qemu/aes.h |9 +
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/include/qemu/aes.h b/include/qemu/aes.h
index e7
This change adds arm-bsd-user, mips-bsd-user, mips64-bsd-user,
mips64el-bsd-user, and mipsel-bsd-user as --target-list options to configure.
---
default-configs/arm-bsd-user.mak |3 +++
default-configs/mips-bsd-user.mak |1 +
default-configs/mips64-bsd-user.mak |1 +
default
From: Roy Franz
For handling CFI and device ID reads, we need to not only know the
width that a NOR flash device is configured for, but also its maximum
width. The maximum width addressing mode is used for multi-width
parts no matter which width they are configured for. The most common
case is
://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20131217
for you to fetch changes up to 84291fe7a34f8c2d595bcdb77ff506d1d60fcd7c:
MAINTAINERS: add myself to maintain allwinner-a10 (2013-12-17 20:12:51 +
From: Peter Crosthwaite
Fix the CBAR initialisation by using the newly defined static property.
Zynq will now correctly init the CBAR to the SCU base address.
Needed to boot Linux on the xilinx_zynq machine model.
Signed-off-by: Peter Crosthwaite
Reviewed-by: Peter Maydell
Message-id:
8db7d5
The man page for qemu-img, and the qemu-doc, did not mention VHDX
as a supported format. This adds in reference to VHDX in those
documents.
Signed-off-by: Jeff Cody
---
qemu-doc.texi | 15 +++
qemu-img.texi | 4 ++--
2 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/q
Register the aarch64-fpu XML and implement the necessary
read/write handlers so we can support reading and writing
of FP registers in the gdb stub.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
configure | 2 +-
gdb-xml/aarch64-fpu.xml | 86 +
From: Antony Pavlov
Signed-off-by: Antony Pavlov
Message-id: 1387188908-754-6-git-send-email-antonynpav...@gmail.com
[PMM: don't try to load ROM blob if qtest_enabled()]
Signed-off-by: Peter Maydell
---
hw/arm/digic_boards.c | 78 +++
1 file chan
From: Alexander Graf
We will need helpers that only make sense with AArch64. Add
helper-a64.{c,h} files as stubs that we can fill with these
helpers in the following patches.
Signed-off-by: Alexander Graf
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/Makefile.obj
From: liguang
Signed-off-by: liguang
Reviewed-by: Peter Crosthwaite
Message-id: 1387159292-10436-3-git-send-email-lig.f...@cn.fujitsu.com
Signed-off-by: Peter Maydell
---
default-configs/arm-softmmu.mak | 2 +
hw/timer/Makefile.objs | 2 +
hw/timer/allwinner-a10-pit.c
From: Claudio Fontana
Provide a skeleton for a64 instruction decoding in translate-a64.c,
by dividing instructions into the classes defined by the
ARM Architecture Reference Manual(DDI0487A_a) section C3.
Signed-off-by: Claudio Fontana
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderso
From: Antony Pavlov
Signed-off-by: Antony Pavlov
Message-id: 1387188908-754-7-git-send-email-antonynpav...@gmail.com
Signed-off-by: Peter Maydell
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7f45d1d..1fce9a5 100644
--- a/MAINTAINERS
From: liguang
Signed-off-by: liguang
Message-id: 1387159292-10436-7-git-send-email-lig.f...@cn.fujitsu.com
Signed-off-by: Peter Maydell
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 1fce9a5..a5ab8f8 100644
--- a/MAINTAINERS
+++ b/MAI
[v3]
- Rebases to commit f46e720a82ccdf1a521cf459448f3f96ed895d43 (HEAD).
- Changes 'HOST_API_DIR' to 'HOST_VARIANT_DIR' for the BSD variant.
- Fixes boundry condition bug in mmap() system call handler.
- Fixes floating point support for MIPS64.
- Fixes execve() syscall handler so shell scripts ar
From: Antony Pavlov
Signed-off-by: Antony Pavlov
Reviewed-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
Message-id: 1387188908-754-5-git-send-email-antonynpav...@gmail.com
Signed-off-by: Peter Maydell
---
hw/arm/digic.c | 16
hw/char/Makefile.objs| 1 +
hw/ch
From: Alexander Graf
Implement the B and BL instructions (PC relative branches and calls).
For convenience in managing TCG temporaries which might be generated
if a source register is the zero-register XZR, we provide a simple
mechanism for creating a new temp which is automatically freed at the
From: Alexander Graf
When executing translation blocks we need to be able to recover
our program counter. Add a method to set it for AArch64 CPUs.
This covers user-mode, but for system mode emulation we will
need to check if the CPU is in an AArch32 execution state.
Signed-off-by: Alexander Graf
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