Hey,
So I've been hacking away on an Xbox target in qemu (
https://github.com/espes/xqemu). The Xbox APU contains a Motorola DSP56362
core, and there's API and tooling for applications to generate and load
custom "effects" consisting of DSP code, so a reasonable emulation of it
seems to be require
On 32-bit TCG targets, when emulating deposit_i64 with a mov_i32 +
deposit_i32, care should be taken to not overwrite the low part of
the second argument before the deposit when it is the same the
destination.
This fixes the shld instruction in qemu-system-x86_64, which in turns
fixes booting "sys
Hi Gerd,
Using qemu-upstream with pci-passthrough on xen-unstable previously worked fine.
Since commit 0f7b2864d0d0c3ef2801f9214d8c510c80a220d1 (bisected) i see what i
think are timing issues (video device is reporting buffer underruns).
Since that commit changes vnc code, i have disabled vnc (w
Spec patch already inside.
Sent from my iPad
On Apr 20, 2013, at 8:04 PM, "Michael S. Tsirkin" wrote:
> On Fri, Apr 19, 2013 at 10:10:01AM +0300, Dmitry Fleytman wrote:
>> Hello All,
>>
>> Any news regarding this patch?
>>
>> Thanks,
>> Dmitry
>
> Rusty could you comment on the spec change s
On Mon, Apr 15, 2013 at 10:59:15AM +0400, Pavel Dovgaluk wrote:
> Fixed EFLAGS corruption by ROR r8/r16 instruction located at the end of the
> TB.
>
> Signed-off-by: Pavel Dovgalyuk
> ---
> target-i386/translate.c |1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/t
Power ISA 2.05 adds support for extended mtfsf/mtfsfi form, with a new
W field to select the upper part of the FPCSR register.
For that the helper is changed to handle 64-bit input values and mask with
up to 16 bits. The mtfsf/mtfsfi instructions do not have the W bit
marked as invalid anymore. In
qemu-system-ppc64 -M pseries clamis to emulate a POWER7 CPU,
corresponding to an ISA 2.06 compliant CPU, while QEMU emulates
something like an ISA 2.04 CPU.
Given that glibc and GCC start to use some instructions like cmpb and
fcpsgn, this starts to be problematic.
This patches series improves th
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
disas.c |1 +
1 file changed, 1 insertion(+)
diff --git a/disas.c b/disas.c
index 67103e0..e51127e 100644
--- a/disas.c
+++ b/disas.c
@@ -227,6 +227,7 @@ void target_disas(FILE *out, CPUArchState *env,
target_ulong code,
fabs, fnabs and fneg are just flipping the bit sign of an FP register,
this can be implemented in TCG instead of using softfloat.
Signed-off-by: Aurelien Jarno
---
target-ppc/fpu_helper.c | 31 ---
target-ppc/helper.h |3 ---
target-ppc/translate.c | 40 +
Needed for Power ISA version 2.05 compliance. The check for odd register
pairs is done using the invalid bits.
Signed-off-by: Aurelien Jarno
---
target-ppc/translate.c | 48
1 file changed, 48 insertions(+)
diff --git a/target-ppc/translate.c b
Needed for Power ISA version 2.05 compliance.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-ppc/translate.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 977f9ef..4b1896f 100644
--- a/target-
.. and enable it on POWER7 CPU.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-ppc/cpu.h|4 +++-
target-ppc/translate_init.c |2 +-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 42c36e2..8b0b
Needed for Power ISA version 2.05 compliance.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-ppc/helper.h |1 +
target-ppc/int_helper.c | 15 +++
target-ppc/translate.c |8
3 files changed, 24 insertions(+)
diff --git a/target-ppc/he
Needed for Power ISA version 2.05 compliance.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-ppc/translate.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 4b1896f..8298e1f
Needed for Power ISA version 2.05 compliance.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-ppc/translate.c | 38 ++
1 file changed, 38 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 6bee6db..977f
Needed for Power ISA version 2.05 compliance. The check for odd register
pairs is done using the invalid bits.
Signed-off-by: Aurelien Jarno
---
target-ppc/translate.c | 48
1 file changed, 48 insertions(+)
diff --git a/target-ppc/translate.c b
On Wed, Apr 17, 2013 at 9:46 AM, Paolo Bonzini wrote:
> This uses system calls directly for Unix file descriptors, so that the
> efficient writev_buffer can be used. Pay attention to the possibility
> of partial writes in writev.
>
> Reviewed-by: Juan Quintela
> Reviewed-by: Orit Wassermann
> S
On Thu, Apr 18, 2013 at 4:47 AM, wrote:
> From: Peter Crosthwaite
>
> Configure to use the DTC submodule to build libfdt when no system libfdt
> is found. Prompt to install the DTC submodule if --enable-fdt is set but
> no DTC can be found.
>
> DTC has no out-of-tree build capability, so the con
Thanks, applied all.
On Sat, Apr 20, 2013 at 1:48 PM, Peter Maydell wrote:
> There is currently only one user of the qdev taddr (target addr,
> now hwaddr) property code, and that user is wrong anyway, since the
> property it's trying to set isn't actually a taddr property.
> Fix the erroneous u
On Fri, Apr 19, 2013 at 10:10:01AM +0300, Dmitry Fleytman wrote:
> Hello All,
>
> Any news regarding this patch?
>
> Thanks,
> Dmitry
>
Rusty could you comment on the spec change soon please?
If you pick it up I think we can include the feature in QEMU 1.5.
> On Sun, Apr 7, 2013 at 9:34 AM, Dm
On Thu, Apr 18, 2013 at 04:07:24PM -0600, Eric Blake wrote:
> On 04/17/2013 05:07 PM, mrhi...@linux.vnet.ibm.com wrote:
> > From: "Michael R. Hines"
> >
> > This capability allows you to disable dynamic chunk registration
> > for better throughput on high-performance links.
> >
> > It is enabled
On 04/20/2013 03:46 AM, Blue Swirl wrote:
On Fri, Apr 19, 2013 at 12:18 PM, Andreas Färber wrote:
Am 19.04.2013 14:11, schrieb Andreas Färber:
Hi,
Am 19.04.2013 10:27, schrieb Richard Henderson:
All targets have been converted to allocating space for temporaries
on the stack. No need to all
On 04/18/2013 10:44 PM, Amos Kong wrote:
> (qemu) sendkey a 1000
>
> Current design is that qemu only send one down event to guest,
> and delay sometime, then send one up event. In this case, only
> key can be identified by guest.
>
> This patch changed qemu to intervally send down events to gues
Friday, April 19, 2013, 7:15:59 PM, you wrote:
> Il 19/04/2013 19:11, Sander Eikelenboom ha scritto:
>> BTW, is there a relation with the "main-loop: WARNING: I/O thread spun for
>> 1000 iterations" ?
>> I'm still seeing that one popping up in the log.
> If you want to try to up the count to 10
On 2013-04-16 09:42, Gerd Hoffmann wrote:
> On 04/10/13 10:31, Jan Kiszka wrote:
>> On 2013-04-03 13:50, Gerd Hoffmann wrote:
>>> Hi,
>>>
> No, it is not, and yes, this is where the inconsistency comes
> from. We read wred+wgreen+wblue directly from the surface
> whereas depth is c
Drop all the infrastructure for taddr properties (ie ones which
are 'hwaddr' sized). These are now unused, and any further desired
use would be rather questionable since device properties shouldn't
generally depend on a type that is conceptually variable based on
the target CPU. 32 or 64 bit intege
The sysbus-ohci dma-address property is declared as a HEX64
property, not a TADDR, so use the correct setter for it.
Signed-off-by: Peter Maydell
Acked-by: Andreas Färber
Tested-by: Aurelien Jarno
---
hw/display/sm501.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/
There is currently only one user of the qdev taddr (target addr,
now hwaddr) property code, and that user is wrong anyway, since the
property it's trying to set isn't actually a taddr property.
Fix the erroneous use in sm501 and drop all the taddr property code.
The justification for dropping the
Patch does not apply, please rebase:
Applying: qdev: Drop taddr properties
error: patch failed: hw/display/sm501.c:28
error: hw/display/sm501.c: patch does not apply
error: patch failed: hw/dma/xilinx_axidma.c:26
error: hw/dma/xilinx_axidma.c: patch does not apply
Patch failed at 0002 qdev: Drop t
Thanks, pulled.
On Fri, Apr 19, 2013 at 2:57 PM, Peter Maydell wrote:
> arm-devs queue pullreq; this is just the versatile-pci
> cleanup (which has been on the list for some time now).
> Please pull.
>
> thanks
> -- PMM
>
>
> The following changes since commit 09dada400328d75daf79e3eca1e48e024fec
Thanks, pulled.
On Fri, Apr 19, 2013 at 3:06 PM, Peter Maydell wrote:
> target-arm pullreq, containing a fix for a dumb SRS bug I
> introduced, and the update to migration to use vmstate
> (both of which have been on the list since before freeze).
> Please pull.
>
> thanks
> -- PMM
>
> The follow
Thanks, pulled.
On Fri, Apr 19, 2013 at 1:59 PM, wrote:
> From: Riku Voipio
>
> The following changes since commit 09dada400328d75daf79e3eca1e48e024fec148d:
>
> configure: remove duplicate test (2013-04-18 14:12:31 +0200)
>
> are available in the git repository at:
>
> git://git.linaro.org/
On 19/04/13 16:31, Alexander Graf wrote:
Hi everyone,
Has FW_CFG_PPC_CPUFREQ been removed from QEMU for some reason? I noticed that
the value always comes back as 0 in OpenBIOS, and it looks as if the
FW_CFG_PPC_CPUFREQ constant (FW_CFG_ARCH_LOCAL + 0x4) has been removed from
hw/ppc.h?
In
On Fri, Apr 19, 2013 at 12:18 PM, Andreas Färber wrote:
> Am 19.04.2013 14:11, schrieb Andreas Färber:
>> Hi,
>>
>> Am 19.04.2013 10:27, schrieb Richard Henderson:
>>> All targets have been converted to allocating space for temporaries
>>> on the stack. No need to allocate space within the CPU_CO
On Sat, Apr 20, 2013 at 9:56 AM, Artyom Tarasenko wrote:
> On Sat, Apr 20, 2013 at 11:34 AM, Blue Swirl wrote:
>> On Sun, Apr 14, 2013 at 9:41 PM, Artyom Tarasenko
>> wrote:
>>> On Sun, Apr 14, 2013 at 10:05 AM, Hervé Poussineau
>>> wrote:
As m48t59 devices can only be created with m48t5
On Wed, Apr 17, 2013 at 2:15 AM, Rob Landley wrote:
> On 04/14/2013 04:38:23 AM, Artyom Tarasenko wrote:
>>
>> On Sat, Apr 13, 2013 at 7:03 PM, Rob Landley wrote:
>> > On 03/26/2013 02:34:50 AM, Artyom Tarasenko wrote:
>> >>
>> >> On Tue, Mar 26, 2013 at 1:52 AM, Rob Landley wrote:
>> >> > Can t
On Sat, Apr 20, 2013 at 11:34 AM, Blue Swirl wrote:
> On Sun, Apr 14, 2013 at 9:41 PM, Artyom Tarasenko wrote:
>> On Sun, Apr 14, 2013 at 10:05 AM, Hervé Poussineau
>> wrote:
>>> As m48t59 devices can only be created with m48t59_init() or
>>> m48t59_init_isa(),
>>> we know exactly which nvram
On Sun, Apr 14, 2013 at 9:41 PM, Artyom Tarasenko wrote:
> On Sun, Apr 14, 2013 at 10:05 AM, Hervé Poussineau
> wrote:
>> As m48t59 devices can only be created with m48t59_init() or
>> m48t59_init_isa(),
>> we know exactly which nvram types are required. Register only those three
>> types.
>> R
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