Not all tests pass, but at least they can be run using 'make test'.
To build individual tests:
$ cd $BUILD_PATH/tests/tcg
$ SRC_PATH=path/to/qemu make
Signed-off-by: Catalin Patulea
---
tests/tcg/Makefile| 16 ++--
tests/tcg/test-i386.c |3 ++-
tests/tcg/test_path.c | 1
On 13/07/12 08:35, Scott Wood wrote:
> On 07/12/2012 03:52 AM, Alexey Kardashevskiy wrote:
>> +/* API for POWERPC IOMMU */
>> +
>> +#define POWERPC_IOMMU 2
>> +
>> +struct tce_iommu_info {
>> +__u32 argsz;
>> +__u32 dma32_window_start;
>> +__u32 dma32_window_
Two comments below.
On 13/07/12 06:54, Blue Swirl wrote:
> On Thu, Jul 12, 2012 at 8:52 AM, Alexey Kardashevskiy wrote:
>> It literally does the following:
>>
>> 1. POWERPC IOMMU support (the kernel counterpart is required)
>>
>> 2. The patch assumes that IOAPIC calls are going to be replaced
>>
Add OpenRISC timer support.
Signed-off-by: Jia Liu
---
hw/openrisc/Makefile.objs |2 +-
hw/openrisc_timer.c | 101 +
target-openrisc/cpu.h | 22 ++
3 files changed, 124 insertions(+), 1 deletion(-)
create mode 100644 hw/openri
Add OpenRISC Programmable Interrupt Controller support.
Signed-off-by: Jia Liu
---
hw/openrisc/Makefile.objs |2 ++
hw/openrisc_pic.c | 60 +
target-openrisc/cpu.h |3 +++
3 files changed, 65 insertions(+)
create mode 100644 hw/o
Add OpenRISC float instruction helpers.
Signed-off-by: Jia Liu
---
target-openrisc/Makefile.objs |3 +-
target-openrisc/fpu_helper.c | 300 +
target-openrisc/helper.h | 33 +
3 files changed, 335 insertions(+), 1 deletion(-)
create mode 1
Add OpenRISC exception support.
Signed-off-by: Jia Liu
---
target-openrisc/Makefile.objs |4 ++--
target-openrisc/exception.c| 27 +++
target-openrisc/exception.h| 28
target-openrisc/exception_helper.c | 29
Add a IIS dummy board.
Signed-off-by: Jia Liu
---
hw/openrisc/Makefile.objs |2 +-
hw/openrisc_sim.c | 150 +
2 files changed, 151 insertions(+), 1 deletion(-)
create mode 100644 hw/openrisc_sim.c
diff --git a/hw/openrisc/Makefile.objs b
On 13/07/12 13:47, Alex Williamson wrote:
> On Thu, 2012-07-12 at 18:52 +1000, Alexey Kardashevskiy wrote:
>> It literally does the following:
>>
>> 1. POWERPC IOMMU support (the kernel counterpart is required)
>>
>> 2. The patch assumes that IOAPIC calls are going to be replaced
>> with something
Add OpenRISC instruction tanslation routines.
Signed-off-by: Jia Liu
---
target-openrisc/translate.c | 1700 +++
1 file changed, 1700 insertions(+)
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index a2b9b4f..ed25604 100644
--- a/
Add OpenRISC interrupt support.
Signed-off-by: Jia Liu
---
cpu-exec.c | 17 +++
target-openrisc/Makefile.objs |2 +-
target-openrisc/cpu.h |8 -
target-openrisc/helper.h | 25
target-openrisc/interrupt.c
Add QEMU OpenRISC linux user support.
Signed-off-by: Jia Liu
---
configure |1 +
default-configs/or32-linux-user.mak |1 +
linux-user/elfload.c| 41 +++
linux-user/main.c | 100 +++
linux-user/signal.c
Add OpenRISC linux syscall, signal and termbits.
Signed-off-by: Jia Liu
---
linux-user/openrisc/syscall.h | 24 ++
linux-user/openrisc/syscall_nr.h| 506 +++
linux-user/openrisc/target_signal.h | 26 ++
linux-user/openrisc/termbits.h | 294 +++
Add OpenRISC gdb stub support.
Signed-off-by: Jia Liu
---
gdbstub.c | 64 +
1 file changed, 64 insertions(+)
diff --git a/gdbstub.c b/gdbstub.c
index 08cf864..5d37dd9 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -1155,6 +1155,68 @@ stat
Add OpenRISC system instructions.
Signed-off-by: Jia Liu
---
target-openrisc/Makefile.objs |2 +-
target-openrisc/cpu.h |3 +
target-openrisc/helper.h |4 +
target-openrisc/sys_helper.c | 287 +
target-openrisc/translate.c |
Add OpenRISC int instruction helpers.
Signed-off-by: Jia Liu
---
target-openrisc/Makefile.objs |2 +-
target-openrisc/helper.h |5 +++
target-openrisc/int_helper.c | 87 +
3 files changed, 93 insertions(+), 1 deletion(-)
create mode 100644
Add OpenRISC MMU support.
Signed-off-by: Jia Liu
---
target-openrisc/cpu.h| 79 +++-
target-openrisc/mmu.c| 206 +-
target-openrisc/mmu_helper.c | 20
3 files changed, 303 insertions(+), 2 deletions(-)
diff --git a/ta
Add OpenRISC target stubs and cpu support.
Signed-off-by: Jia Liu
---
arch_init.c |2 +
arch_init.h |1 +
configure| 14 +-
cpu-exec.c |2 +
default-configs/or32-softmmu.mak |4 +
elf.h
This is the OpenCores OpenRISC 1200 support for QEMU.
Full implementation of the system-model and linux-user-model support.
OpenRISC 1200 is a OpenCores open source CPU,
its architecture manual can be found at
http://opencores.org/svnget,or1k?file=/trunk/docs/openrisc_arch.pdf
A OpenRISC Linux ke
Hi
I also see that qemu 0.13 has live migration in inbuilt.Does it also
uses libvirt behind the scenes to create live ram snapshot ?
On Thu, 2012-07-12 at 18:52 +1000, Alexey Kardashevskiy wrote:
> It literally does the following:
>
> 1. POWERPC IOMMU support (the kernel counterpart is required)
>
> 2. The patch assumes that IOAPIC calls are going to be replaced
> with something generic. I have something in my local git but it
Recent kernels use this to set the CP15 registers, rather than putting
them in 'struct kvm_regs'. The changed size of that struct changes the
ioctl number, so we have a temporary hack to try both.
Signed-off-by: Rusty Russell
diff --git a/linux-headers/asm-arm/kvm.h b/linux-headers/asm-arm/kvm.
This removes old kernel support for cp15 inside struct kvm_regs, and
assumes we have KVM_SET_SREGS support for setting the target.
Signed-off-by: Rusty Russell
diff --git a/linux-headers/asm-arm/kvm.h b/linux-headers/asm-arm/kvm.h
index 4842e85..8d255f2 100644
--- a/linux-headers/asm-arm/kvm.h
+
Recent kernels use this to set the cpu and features (currently, only
the A15 is supported).
Note that this causes the registers in the CPU to be initialized, so
it's important that all CPUs are created first (they are, as it turns
out).
This code ignores errors, for backwards compatibility with o
On Fri, Jul 6, 2012 at 3:00 AM, Peter Maydell wrote:
> Add support for reading device tree properties (both generic
> and single-cell ones) to QEMU's convenience wrapper layer.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Peter A. G. Crosthwaite
> ---
> device_tree.c | 30 +
On Thu, Jul 12, 2012 at 11:42 PM, Markus Armbruster wrote:
> Kevin Wolf writes:
>
>> Am 02.07.2012 11:42, schrieb Peter Crosthwaite:
>>> On Mon, Jul 2, 2012 at 7:04 PM, Kevin Wolf wrote:
Am 02.07.2012 10:57, schrieb Peter Crosthwaite:
> No conditional on the qemu_coroutine_create. So it
On 07/12/2012 03:52 AM, Alexey Kardashevskiy wrote:
> +/* API for POWERPC IOMMU */
> +
> +#define POWERPC_IOMMU 2
> +
> +struct tce_iommu_info {
> +__u32 argsz;
> +__u32 dma32_window_start;
> +__u32 dma32_window_size;
> +};
> +
> +#define POWERPC_IOMMU_GET_IN
Hi Zhi,
On Thu, 2012-07-12 at 14:59 +0800, Zhi Yong Wu wrote:
> thanks, it is applied to my vhost_scsi git tree
> git://github.com/wuzhy/qemu.git vhost-scsi
>
Thanks for picking up this patch in your vhost-scsi tree.
As mentioned off-list, I'd like to rebase to a more recent qemu.git to
include
On Thu, 2012-07-12 at 20:54 +, Blue Swirl wrote:
> On Thu, Jul 12, 2012 at 8:52 AM, Alexey Kardashevskiy wrote:
> > It literally does the following:
> >
> > 1. POWERPC IOMMU support (the kernel counterpart is required)
> >
> > 2. The patch assumes that IOAPIC calls are going to be replaced
> >
On 12 July 2012 21:28, Blue Swirl wrote:
> On Wed, Jul 11, 2012 at 12:54 PM, Kevin Wolf wrote:
>> Am 08.07.2012 14:09, schrieb Andreas Schwab:
>> Which is why such changes are probably a bad idea. Even more so if they
>> aren't scripted.
>
> Maybe your patches are perfect from day one, but all pa
Marking incomplete pending feedback. Assuming this is not fixed in12.04
I'll try again to reproduce.
** Changed in: qemu-kvm (Ubuntu)
Status: New => Incomplete
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.laun
Can you confirm whether this is still happening in 12.04 and/or 12.10?
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/882997
Title:
64-bit linux guests fail to start on oneiric running 3.0 kernel
S
On 12 July 2012 21:18, Blue Swirl wrote:
> On Tue, Jul 10, 2012 at 9:36 PM, Peter Maydell
> wrote:
>> Basically 'int' has more natural
>> behaviour for reasoning about than 'unsigned' in ranges
>> where it's usually used (ie small ones).
>
> But 'unsigned' is much more naturally suited to values
On Thu, Jul 12, 2012 at 8:52 AM, Alexey Kardashevskiy wrote:
> It literally does the following:
>
> 1. POWERPC IOMMU support (the kernel counterpart is required)
>
> 2. The patch assumes that IOAPIC calls are going to be replaced
> with something generic. I have something in my local git but it's
Hi everyone,
I am pleased to announce that the QEMU v1.1.1 stable release is now
available at:
http://wiki.qemu.org/download/qemu-1.1.1.tar.bz2
Also, the stable-1.1 repository is now available on qemu.org:
http://git.qemu.org/?p=qemu-stable-1.1.git;a=summary
The next release, v1.1.2, is tentat
On Thu, Jul 12, 2012 at 8:07 AM, Kevin Wolf wrote:
> Am 11.07.2012 18:00, schrieb Paolo Bonzini:
>> Il 15/06/2012 18:45, Eric Blake ha scritto:
>>> Pre-existing, but do we have any policy on US (canceled) vs. UK
>>> (cancelled) spelling? Obviously, our API spelling is locked into UK
>>> spelling,
On Wed, Jul 11, 2012 at 1:12 PM, 陳韋任 (Wei-Ren Chen)
wrote:
> On Wed, Jul 11, 2012 at 02:09:53PM +0100, Peter Maydell wrote:
>> On 11 July 2012 13:54, Kevin Wolf wrote:
>> > Does this patch improve anything? Last time I checked, qemu only
>> > compiled on gcc anyway.
>>
>> It would be nice to be a
On Wed, Jul 11, 2012 at 12:54 PM, Kevin Wolf wrote:
> Am 08.07.2012 14:09, schrieb Andreas Schwab:
>> blauwir...@gmail.com writes:
>>
>>> +pstrcpy(bs->backing_format, sizeof(bs->backing_format),
>>> +backing_fmt ? backing_file : "");
>>
>> s/backing_file/backing_fmt/
>
> Which is w
On Wed, Jul 11, 2012 at 12:49 PM, Kevin Wolf wrote:
> Am 08.07.2012 21:22, schrieb blauwir...@gmail.com:
>> From: Blue Swirl
>>
>> Use 'unsigned int' for bit numbers instead of 'unsigned long' or
>> 'int'. Adjust asserts.
>>
>> Signed-off-by: Blue Swirl
>
> I haven't followed the original discus
On Tue, Jul 10, 2012 at 9:36 PM, Peter Maydell wrote:
> On 10 July 2012 21:01, Blue Swirl wrote:
>> On Tue, Jul 10, 2012 at 7:37 PM, Peter Maydell
>> wrote:
>>> On 10 July 2012 20:18, Blue Swirl wrote:
On Mon, Jul 9, 2012 at 7:49 AM, Markus Armbruster
wrote:
> There is no conse
Hello,
I found a post in this mail list in 2008 that Clemens Kolbitsch made a
patch for Atheros wireless networking support:
http://lists.nongnu.org/archive/html/qemu-devel/2008-02/msg00538.html
I want to emulate wireless networking environment, e.g. interference,
collision, etc. in qemu-kvm and
On Wed, Jul 11, 2012 at 10:31 AM, Vasilis Liaskovitis
wrote:
> This is v2 of the ACPI memory hotplug prototype for x86_64 target.
I think the concept of DIMMs (what about SIMMs? SODIMMs? I liked
memslot) would be useful for most targets, but hotplugging may be
limited to x86 only. It would be nic
On Tue, Jul 10, 2012 at 06:33:48PM +0200, Alexander Graf wrote:
> Hi Mike,
>
> This is my current patch queue for s390 for 1.1. It contains an important fix
> to make virtio devices accessible via their aliases.
>
> Please pull.
Pulled into stable-1.1 (now on git.qemu.org). Will be included
in t
On Wed, Jul 11, 2012 at 10:31 AM, Vasilis Liaskovitis
wrote:
> Each hotplug-able memory slot is a SysBusDevice. A hot-add operation for a
> particular dimm creates a new MemoryRegion of the given physical address
> offset, size and node proximity, and attaches it to main system memory as a
> sub_r
On Wed, Jul 11, 2012 at 10:31 AM, Vasilis Liaskovitis
wrote:
> The numa_fw_cfg paravirt interface is extended to include SRAT information for
> all hotplug-able dimms. There are 3 words for each hotplug-able memory slot,
> denoting start address, size and node proximity. The new info is appended
On Tue, Jul 10, 2012 at 8:53 PM, Anthony Liguori wrote:
> On 07/08/2012 06:51 AM, blauwir...@gmail.com wrote:
>>
>> From: Blue Swirl
>>
>> Replace %m format with explicit call to standard strerror().
>>
>> Signed-off-by: Blue Swirl
>
>
> I would expect '%m' to be thread safe whereas strerror() isn
On Tue, Jul 10, 2012 at 8:22 PM, Eduardo Habkost wrote:
> Signed-off-by: Eduardo Habkost
> ---
> target-i386/topology.h | 138
>
> tests/.gitignore |1 +
> tests/Makefile |7 ++-
> tests/test-x86-cpuid.c | 108
On 07/12/2012 01:17 PM, siddharth srivastava wrote:
> Hi
>
> I am working on a virtualization project for which I am using
> Qemu(0.13) + KVM.
That's rather old; we're now at 1.1, and there have been some migration
bugs fixed in the meantime.
>I am trying to get an automated switch to live
> mig
On Tue, Jul 10, 2012 at 8:22 PM, Eduardo Habkost wrote:
> Signed-off-by: Eduardo Habkost
> ---
> hw/pc.c | 23 +++
> 1 file changed, 23 insertions(+)
>
> diff --git a/hw/pc.c b/hw/pc.c
> index 3b8e469..dc95fb8 100644
> --- a/hw/pc.c
> +++ b/hw/pc.c
> @@ -71,6 +71,7 @@
> #d
On Tue, Jul 10, 2012 at 8:22 PM, Eduardo Habkost wrote:
> Signed-off-by: Eduardo Habkost
Maybe the bitops functions should be renamed instead, for example
prefixed by 'qemu_'. That may be safer if one day the kernel find
their way to system headers too.
> ---
> hw/apic.c | 34 +++
Hi
I am working on a virtualization project for which I am using
Qemu(0.13) + KVM.I am trying to get an automated switch to live
migration based on certain condition.
According to [1], it is possible to start migration via Qemu Monitor.
Since I am trying to invoke this via C code, is it possible t
The changelog for 1.1.0-1 states "Pseries handles PCI, allowing for
virtio devices with -M pseries" while this bug report here still stands
as an issue I'm having where SLOF detects my virtio-block device but
QEMU does not create a virtio-pci device that the Linux kernel can
recognize. I would at l
On 07/12/2012 10:55 AM, Pavel Hrdina wrote:
> Signed-off-by: Pavel Hrdina
> ---
> +++ b/qapi-schema.json
> @@ -934,6 +934,41 @@
> { 'command': 'query-block-jobs', 'returns': ['BlockJobInfo'] }
>
> ##
> +# @SnapshotInfo:
> +#
> +# Snapshot list. This structure contains list of snapshots for v
On 07/12/2012 10:55 AM, Pavel Hrdina wrote:
> Signed-off-by: Pavel Hrdina
> ---
> hmp-commands.hx |2 +-
> hmp.c| 10 ++
> hmp.h|1 +
> qapi-schema.json | 17 +
> qmp-commands.hx | 24
> savevm.c |
On 07/12/2012 10:55 AM, Pavel Hrdina wrote:
> Signed-off-by: Pavel Hrdina
> ---
> +++ b/qapi-schema.json
> @@ -1889,4 +1889,26 @@
> #
> # Since: 1.2
> ##
> -{ 'command': 'savevm', 'data': {'*name': 'str'} }
> \ No newline at end of file
> +{ 'command': 'savevm', 'data': {'*name': 'str'} }
> +
On 07/12/2012 10:55 AM, Pavel Hrdina wrote:
> Signed-off-by: Pavel Hrdina
> ---
> +++ b/qapi-schema.json
> @@ -1868,3 +1868,25 @@
> # Since: 0.14.0
> ##
> { 'command': 'netdev_del', 'data': {'id': 'str'} }
> +
> +##
> +# @savevm:
> +#
> +# Create a snapshot of the whole virtual machine. If 'ta
Signed-off-by: Pavel Hrdina
---
hmp-commands.hx |2 +-
hmp.c| 10 ++
hmp.h|1 +
qapi-schema.json | 17 +
qmp-commands.hx | 24
savevm.c | 21 +++--
sysemu.h |1 -
7 file
Signed-off-by: Maksim Kozlov
---
hw/exynos4210_pmu.c | 40 +---
1 files changed, 33 insertions(+), 7 deletions(-)
diff --git a/hw/exynos4210_pmu.c b/hw/exynos4210_pmu.c
index 7f09c79..96588d9 100644
--- a/hw/exynos4210_pmu.c
+++ b/hw/exynos4210_pmu.c
@@ -18,
On 12 July 2012 15:27, Kevin Wolf wrote:
> valgrind tends to get confused and report false positives when you
> switch stacks and don't tell it about it.
Does the sigaltstack backend need anything similar?
-- PMM
Am 12.07.2012 18:51, schrieb Paolo Bonzini:
Il 12/07/2012 16:27, Kevin Wolf ha scritto:
Kevin Wolf (2):
coroutine-ucontext: Help valgrind understand coroutines
qemu-iotests: Valgrind support
configure| 18 ++
coroutine-ucontext.c | 21 +++
Great that you address this issue!
I have two annotations, please see below.
Am 12.07.2012 16:27, schrieb Kevin Wolf:
valgrind tends to get confused and report false positives when you
switch stacks and don't tell it about it.
Signed-off-by: Kevin Wolf
---
configure| 18 ++
Signed-off-by: Pavel Hrdina
---
hmp.c| 34 ++
hmp.h|1 +
monitor.c|2 +-
qapi-schema.json | 35 +++
qerror.c |4
qerror.h |3 +++
qmp-commands.hx | 31 +
This patch-series converts savevm, loadvm, delvm and info snapshots from HMP
into QMP as savevm, loadvm, delvm and query-snapshots.
All comments are welcome.
Pavel
Pavel Hrdina (4):
qapi: Convert savevm
qapi: Convert loadvm
qapi: Convert delvm
qapi: Convert info snapshots
hmp-commands.
This patch just introduces exynos4210_pmu_get_register_index function
to get index of the register's value in the array on its offset. And
functions _read and _write were modified accordingly.
Signed-off-by: Maksim Kozlov
---
hw/exynos4210_pmu.c | 56 ---
Signed-off-by: Pavel Hrdina
---
hmp-commands.hx |2 +-
hmp.c| 10 ++
hmp.h|1 +
monitor.c| 12
qapi-schema.json | 24 +++-
qerror.c | 16
qerror.h | 12
qmp-c
Signed-off-by: Pavel Hrdina
---
hmp-commands.hx |2 +-
hmp.c| 10 ++
hmp.h|1 +
qapi-schema.json | 22 ++
qerror.c | 24
qerror.h | 18 ++
qmp-commands.hx | 26
It make possible to set DEBUG_PMU and DEBUG_PMU_EXTEND
independently of each other
Signed-off-by: Maksim Kozlov
---
hw/exynos4210_pmu.c | 23 +--
1 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/hw/exynos4210_pmu.c b/hw/exynos4210_pmu.c
index 2be7e08..26a726f
Mainly to make 'exynos4210_pmu_regs' array more readable.
Signed-off-by: Maksim Kozlov
---
hw/exynos4210_pmu.c | 324 ++-
1 files changed, 164 insertions(+), 160 deletions(-)
diff --git a/hw/exynos4210_pmu.c b/hw/exynos4210_pmu.c
index c12d750..2
This patchset created mainly to add software reset support, but includes some
other things.
1. fix formatting of the exynos4210_pmu_regs structure
2. fix PRINT_DEBUG macro set to be able to enable extend and non-extend output
independently of each other
3. introduce new function to get register
Legacy -drive cyls=... are now ignored completely when the drive
doesn't back a hard disk device. Before, they were first checked
against a hard disk's limits, then ignored.
Signed-off-by: Markus Armbruster
---
hw/ide/qdev.c |3 ++-
hw/scsi-disk.c |3 ++-
2 files changed, 4 insertions(
Il 12/07/2012 16:27, Kevin Wolf ha scritto:
> Kevin Wolf (2):
> coroutine-ucontext: Help valgrind understand coroutines
> qemu-iotests: Valgrind support
>
> configure| 18 ++
> coroutine-ucontext.c | 21 +
> tests/qemu-iotest
I didn't delete comment in this file. This comment become irrelevant
after apply this patch. I'll send new patch set.
06.07.2012 19:49, Maksim Kozlov пишет:
Signed-off-by: Maksim Kozlov
---
hw/exynos4210_pmu.c | 34 +-
1 files changed, 33 insertions(+), 1 de
On Thu, 5 Jul 2012 20:48:44 +0800
Amos Kong wrote:
> Convert 'sendkey' to use QAPI. do_sendkey() depends on some
> variables/functions in monitor.c, so reserve qmp_sendkey()
> to monitor.c
>
> key_defs[] in console.h is the mapping of key name to keycode,
> Keys' index in the enmu and key_defs[
This patch adds a "use64" property which will make the ivshmem driver
register a 64bit memory bar when set, so you have something to play with
when testing 64bit pci bits. It also allows to have quite big shared
memory regions, like this:
[root@fedora ~]# lspci -vs1:1
01:01.0 RAM memory: Red Hat,
Add implementations of the AMAIR0 and AMAIR1 LPAE
Auxiliary Memory Attribute Indirection Registers.
These are implementation defined and we choose to
implement them as RAZ/WI, matching the Cortex-A7
and Cortex-A15.
Signed-off-by: Peter Maydell
---
target-arm/helper.c | 16
1 f
Usual target-arm pullreq. This one has a couple of bugfixes for
issues in the cp15 rework, and the LPAE patch series (including
switching to 64 bit physaddrs for ARM, and a trivial imx_avic
patch which is needed as a prerequisite for that).
thanks
-- PMM
The following changes since commit 9233685
Fix a couple of cases where cp register names were copy-and-pasted.
These are harmless since we don't use the name for anything (except
debugging convenience) but could be confusing.
Signed-off-by: Peter Maydell
Reviewed-by: Igor Mitsyanko
---
target-arm/helper.c |6 +++---
1 files changed,
Implement the actual table walk code for LPAE's long format
translation tables.
Signed-off-by: Peter Maydell
---
target-arm/helper.c | 182 +++
1 files changed, 182 insertions(+), 0 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helpe
In the implementation of get_phys_addr(), consistently use
target_phys_addr_t to hold the physical address rather than
uint32_t.
Signed-off-by: Peter Maydell
---
target-arm/helper.c | 29 +++--
1 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/target-arm/
Implement the changes to the TTBCR register required for LPAE:
* many fewer bits should be RAZ/WI
* since TTBCR changes can result in a change of ASID, we must
flush the TLB on writes to it
Signed-off-by: Peter Maydell
---
target-arm/helper.c | 15 ++-
1 files changed, 14 inse
Fix a copy-and-paste error in the register description for TTBR1
that meant it was a duplicate of TTBR0 rather than affecting the
correct bit of CPU state.
Signed-off-by: Peter Maydell
---
target-arm/helper.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/target-arm/he
Implement the privileged-execute-never (PXN) translation table bit.
It is implementation-defined whether this is implemented, so we give
it its own ARM_FEATURE_ flag. LPAE requires PXN, so add also an
LPAE feature flag and the implication logic, as a placeholder
for actually implementing LPAE at a
Alexander Graf writes:
> On 12.07.2012, at 10:17, Markus Armbruster wrote:
>
>> [Alex's illegibly long lines wrapped]
>>
>> Alexander Graf writes:
>>
>>> On 09.07.2012, at 10:50, Markus Armbruster wrote:
>>>
Alexander Graf writes:
> We've had support for creating AHCI devices
Under LPAE, the cp15 registers PAR, TTBR0 and TTBR1 are extended
to 64 bits, with a 64 bit (MRRC/MCRR) access path to read the
full width of the register. Add the state fields for the top
half and the 64 bit access path. Actual use of the top half of
the register will come with the addition of the
Fix errors in the TCG temp handling in the 64 bit coprocessor
write path: we were reusing a 32 bit temp after it had been
freed by store_reg(), and failing to free a 64 bit temp.
This bug has no visible effect at this point because there
aren't any non-NOP 64 bit registers yet; it needs to be fixe
valgrind tends to get confused and report false positives when you
switch stacks and don't tell it about it.
Signed-off-by: Kevin Wolf
---
configure| 18 ++
coroutine-ucontext.c | 21 +
2 files changed, 39 insertions(+), 0 deletions(-)
diff --
Kevin Wolf (2):
coroutine-ucontext: Help valgrind understand coroutines
qemu-iotests: Valgrind support
configure| 18 ++
coroutine-ucontext.c | 21 +
tests/qemu-iotests/common| 11 +++
tests/qemu-iotests/common.
Add a missing cast to avoid gcc complaining about format string
errors when printing an expression based on a target_phys_addr_t.
Signed-off-by: Peter Maydell
Reviewed-by: Peter Chubb
---
hw/imx_avic.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/hw/imx_avic.c b/hw/
check -valgrind wraps all qemu-io calls with valgrind. This makes it a
bit easier to debug problems that occur somewhere deep in a test case.
Signed-off-by: Kevin Wolf
---
tests/qemu-iotests/common| 11 +++
tests/qemu-iotests/common.rc | 10 ++
2 files changed, 21 inserti
LPAE extends the DBGDRAR and DBGDSAR debug registers to 64 bits; we
only implement these as dummy RAZ versions; provide dummies for
the 64 bit accesses as well.
Signed-off-by: Peter Maydell
---
target-arm/helper.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/targe
From: Paul Brook
The coprocessor register rework broke cp15 based WFI instructions.
We incorrectly fall through the normal register write case, which
incorrectly adds a forced block termination. We've already done
a special version of this (DISAS_WFI), so return immediately.
Signed-off-by: Paul
Extend feature flags to 64 bits, as we've just run out of space
in the 32 bit integer we were using for them.
Signed-off-by: Peter Maydell
---
target-arm/cpu.c |2 +-
target-arm/cpu.h |6 +++---
target-arm/machine.c |4 ++--
3 files changed, 6 insertions(+), 6 deletions(-)
d
Make target_phys_addr_t 64 bits for ARM targets, and set
TARGET_PHYS_ADDR_SPACE_BITS to 40. This should have no effect for ARM
boards where physical addresses really are 32 bits (except perhaps a
slight performance hit on 32 bit hosts for system emulation) but allows
us to implement the Large Phys
On Thu, Jul 12, 2012 at 03:51:48PM +0200, Igor Mammedov wrote:
> On 07/10/2012 10:22 PM, Eduardo Habkost wrote:
> >The hotplug case is a bit more complex: we need to either:
> > - have a mechanism to let the ACPI SSDT code know what's the APIC ID of
> >hotplugged CPUs; or
> > - make Seabios r
On 07/10/2012 10:22 PM, Eduardo Habkost wrote:
The hotplug case is a bit more complex: we need to either:
- have a mechanism to let the ACPI SSDT code know what's the APIC ID of
hotplugged CPUs; or
- make Seabios run some code in the hotplugged CPU (I am assuming that this is
simply n
Implement the different format of the PAR when long descriptor
translation tables are in use. Note that we assume that
get_phys_addr() returns a long-descriptor format DFSR value on
failure if long descriptors are in use; this added subtlety tips
the balance and makes it worth adding a comment docu
Il 15/06/2012 20:20, Eric Blake ha scritto:
>> > The second phase is indicated by the progress in "info block-jobs"
>> > reporting the current offset to be equal to the length of the file.
>> > When the job is cancelled in the second phase, QEMU will run the
>> > job until the source is clean and q
Kevin Wolf writes:
> Am 02.07.2012 11:42, schrieb Peter Crosthwaite:
>> On Mon, Jul 2, 2012 at 7:04 PM, Kevin Wolf wrote:
>>> Am 02.07.2012 10:57, schrieb Peter Crosthwaite:
No conditional on the qemu_coroutine_create. So it will always create
a new coroutine for its work which will so
On 12 July 2012 14:22, Igor Mammedov wrote:
> This patch:
> - moves decision to designate BSP from board into cpu, making cpu
> self-sufficient in this regard. Later it will allow to cleanup hw/pc.c
> and remove cpu_reset and wrappers from there.
> - stores flag that CPU is BSP in IA32_APIC_BASE
This patch adds some glue to roms/Makefile to build vgabios binaries for
qemu. It covers both the lgpl'ed vgabios implementation used by qemu
traditionally and the new seabios implementation.
The purpose of this patch is to (a) document the vgabios build process
and (b) simplify seavgabios testin
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