Am 08.01.2012 06:14, schrieb Jordan Justen:
Avi,
When using pflash_cfi01, I hit the assert(new_block) added above. It
seemed to be caused by the low bits of addr being 0x7. This seems to
be come from cpu_register_io_memory in memory_region_init_rom_device.
Would this patch be an appropriate fi
On Tue, Dec 20, 2011 at 06:05, Avi Kivity wrote:
> +void qemu_ram_set_idstr(ram_addr_t addr, const char *name, DeviceState *dev)
> {
> RAMBlock *new_block, *block;
>
> - size = TARGET_PAGE_ALIGN(size);
> - new_block = g_malloc0(sizeof(*new_block));
> + new_block = NULL;
> + QLIST_
Am 07.01.2012 18:29, schrieb Blue Swirl:
> On Thu, Jan 5, 2012 at 17:45, Andreas Färber wrote:
>> Am 15.10.2011 15:50, schrieb Blue Swirl:
>>> Remove now incorrect address base arithmetic, missed by
>>> 9936d6e42392f1440505dfa9df065eabd251cadf. Fixes Sparc64 boot.
>>
>> ...but breaks PReP boot:
>>
Am 03.01.2012 01:51, schrieb Anthony Liguori:
> Right now, DeviceInfo acts as the class for qdev. In order to switch to a
> proper ObjectClass derivative, we need to ween all of the callers off of
> interacting directly with the info pointer.
>
> Signed-off-by: Anthony Liguori
> ---
> diff --gi
Am 03.01.2012 01:52, schrieb Anthony Liguori:
> Same problem as with grackle. This code can't possibly work.
For the record, this comment was not updated for v2: It does work.
The name conflict needs to be resolved, e.g., by adding -pcihost to the
SysBus device names.
Andreas
> Signed-off-by:
Am 08.01.2012 02:46, schrieb Aurelien Jarno:
> On Mon, Jan 02, 2012 at 06:52:15PM -0600, Anthony Liguori wrote:
>> I have no idea what's going on here, but this is broken and cannot possibly
>> work because:
>>
>> 1) It's qdev name conflicts with a device that sits on SysBus
>>
>> 2) The PCI cons
[cc qemu-devel went missing]
Hi Aurélien,
Am 07.01.2012 20:43, schrieb Aurelien Jarno:
> Just a few words to tell I totally disappeared from QEMU last summer due
> to a burn-out. After successfully contributing back to some other
> projects, I am going to slowly restart my activity on QEMU.
Gla
On Mon, Jan 02, 2012 at 06:52:15PM -0600, Anthony Liguori wrote:
> I have no idea what's going on here, but this is broken and cannot possibly
> work because:
>
> 1) It's qdev name conflicts with a device that sits on SysBus
>
> 2) The PCI constructor expects a SysBus device... but's it's a PCI
On 01/07/2012 01:43 PM, Aurelien Jarno wrote:
Hi all,
Just a few words to tell I totally disappeared from QEMU last summer due
to a burn-out. After successfully contributing back to some other
projects, I am going to slowly restart my activity on QEMU.
Great to hear, welcome back!
Regards,
A
On Sat, Jan 07, 2012 at 10:24:09PM +, Blue Swirl wrote:
> In this version, I made basic AREG0 free load/store implementations
> for all targets. Only x86-64 is tested, others have probably problems,
> especially 64 bit guest (Sparc64 in this case) on 32 bit hosts.
>
> I think this should be co
On Sat, 7 Jan 2012, Gerhard Wiesinger wrote:
No NIC:
-net none
=> No iPXE ROM (correct).
but with the previously listed config no iPXE ROM should be there. Saw this
is done through paravirtualization from Seabios/QEMU or KVM. So there
must be a bug with the empty romfile options with net or dev
On Sat, Jan 07, 2012 at 11:47:29PM +0100, Gerhard Wiesinger wrote:
> On Sat, 7 Jan 2012, Kevin O'Connor wrote:
> >I downloaded 8xx_64.rom and tried the above command line.
> >Interestingly, it will register a BEV for a CD drive - which confirms
> >my suspicion that it wont use a BCV. Also interest
On Sat, 7 Jan 2012, Kevin O'Connor wrote:
On Sat, Jan 07, 2012 at 10:00:56AM +0100, Gerhard Wiesinger wrote:
On Fri, 6 Jan 2012, Kevin O'Connor wrote:
I'm not sure what a SCSI rom would do with a CD drive. My guess is
that it wouldn't map it to a BIOS visible drive id at all, as there's
no wa
On Sat, 7 Jan 2012, Kevin O'Connor wrote:
On Sat, Jan 07, 2012 at 09:35:55AM +0100, Gerhard Wiesinger wrote:
[...]
5. Legacy option rom
6. DVD/CD [ata1-0: QEMU DVD-ROM ATAPI-4 DVD/CD]
7. iPXE (PCI 00:00.0)
But there is still the iPXE ROM there (I think I didn't see iPXE
because it is last one
Adjust generation of load and store templates so that the functions
take a parameter for CPUState instead of relying on global env.
Remove wrappers. Move remaining memory helpers to ldst_helper.c.
Signed-off-by: Blue Swirl
---
Makefile.target| 12 ++-
configure |
Signed-off-by: Blue Swirl
---
def-helper.h | 26 ++
1 files changed, 26 insertions(+), 0 deletions(-)
diff --git a/def-helper.h b/def-helper.h
index 8a822c7..a13310e 100644
--- a/def-helper.h
+++ b/def-helper.h
@@ -118,6 +118,8 @@
DEF_HELPER_FLAGS_3(name, 0, ret, t
Don't use register names (or temporary registers) for call arguments
and return values directly but iargs or oargs tables. Later it will be
easier to shift the registers used.
Signed-off-by: Blue Swirl
---
tcg/sparc/tcg-target.c | 44 ++--
1 files change
Don't use register names directly but iargs or oargs tables. Later it will be
easier to shift the registers used.
Signed-off-by: Blue Swirl
---
tcg/i386/tcg-target.c | 75 +---
1 files changed, 45 insertions(+), 30 deletions(-)
diff --git a/tcg/i386
In this version, I made basic AREG0 free load/store implementations
for all targets. Only x86-64 is tested, others have probably problems,
especially 64 bit guest (Sparc64 in this case) on 32 bit hosts.
I think this should be committed as a starting point if there are no
major objections.
Blue Sw
On Thu, Jan 05, 2012 at 04:44:31PM +, Peter Maydell wrote:
> Pending target-arm patches; not very many, but seems better to
> commit them now, since there might be further trustzone related
> patches that would have to sit on top of these. Please pull.
>
> The following changes since commit c4
On Sat, Jan 07, 2012 at 08:22:53PM +, Peter Maydell wrote:
> On 7 January 2012 20:09, Aurelien Jarno wrote:
> > minpd, minps, minsd, minss and maxpd, maxps, maxsd, maxss SSE2
> > instructions have been broken when switching target-i386 to softfloat.
> > It's not possible to use comparison inst
On Tue, Jan 03, 2012 at 04:08:12PM +0100, Alexander Graf wrote:
> Hi Anthony / Aurelien / Blue,
>
> This is my current patch queue for ppc. Please pull.
>
> It includes a screendump segfault fix patch that is not PPC specific, but has
> been on the ML forever now, so I assume it's safe to pull as
On Sat, Jan 07, 2012 at 08:36:12PM +, Blue Swirl wrote:
> On Sat, Jan 7, 2012 at 20:16, Aurelien Jarno wrote:
> > Fix .rel.plt sections in the output to not only include .rel.plt
> > sections from the input but also the .rel.iplt sections and to define
> > the hidden symbols __rel_iplt_start a
On Sat, Jan 7, 2012 at 19:43, Aurelien Jarno wrote:
> Hi all,
>
> Just a few words to tell I totally disappeared from QEMU last summer due
> to a burn-out. After successfully contributing back to some other
> projects, I am going to slowly restart my activity on QEMU. I will try
> to process the p
> On 7 January 2012 20:11, Marek Vasut wrote:
> > The AMBA IDs are supposed to be at the end of 0x2000 block, which the
> > PL011 UART allocates. Current QEMU implementation puts those IDs at
> > 0x1000 offset, which is wrong. The QEMU implementation also allocates
> > only 0x1000 instead of 0x200
minpd, minps, minsd, minss and maxpd, maxps, maxsd, maxss SSE2
instructions have been broken when switching target-i386 to softfloat.
It's not possible to use comparison instructions on float types anymore
to softfloat, so use the floatXX_min anf floatXX_max functions instead.
As a bonus it implem
SSE rounding and flush to zero control has never been implemented. However
given that softfloat-native was using a single state for FPU and SSE and
given that glibc is setting both FPU and SSE state in fesetround(), this
was working correctly up to the switch to softfloat.
Fix that by adding an up
On 7 January 2012 20:11, Marek Vasut wrote:
> The AMBA IDs are supposed to be at the end of 0x2000 block, which the PL011
> UART
> allocates. Current QEMU implementation puts those IDs at 0x1000 offset, which
> is
> wrong. The QEMU implementation also allocates only 0x1000 instead of 0x2000 of
>
On Sat, Jan 7, 2012 at 20:16, Aurelien Jarno wrote:
> Fix .rel.plt sections in the output to not only include .rel.plt
> sections from the input but also the .rel.iplt sections and to define
> the hidden symbols __rel_iplt_start and __rel_iplt_end around
> .rel.iplt as otherwise we get undefined r
On Wed, Jan 04, 2012 at 10:50:09PM +0100, Stefan Weil wrote:
> color_reg is expected to hold 32 bit values, so it was too small.
>
> This bug was reported by coverity:
>
> hw/sm501.c:624:
> result_independent_of_operands:
> color_reg >> 16 is 0 regardless of the values of its operands.
> This occ
roundps and roundss SSE2 instructions have been broken when switching
target-i386 to softfloat. They use float64_round_to_int to convert a
float32, and while the implicit conversion from float32 to float64 was
correct for softfloat-native, it is not for pure softfloat. Fix that by
using the correct
On Sat, Jan 07, 2012 at 12:13:46PM +0100, Stefan Weil wrote:
> There is a regression since commit c5705a7728b4a6bc9e4f2d35911adbaf28042b25
> or some other recent change.
>
> System emulation with a flash device raises an assertion in function
> qemu_ram_set_idstr because no new_block is found at t
The helpers implemented dpps and dppd SSE instructions are not passing
the correct argument types to the softfloat functions. While they do
work anyway providing a correct behaviour, this patch fixes that.
Signed-off-by: Aurelien Jarno
---
target-i386/ops_sse.h | 28 ++-
On 7 January 2012 20:09, Aurelien Jarno wrote:
> minpd, minps, minsd, minss and maxpd, maxps, maxsd, maxss SSE2
> instructions have been broken when switching target-i386 to softfloat.
> It's not possible to use comparison instructions on float types anymore
> to softfloat, so use the floatXX_min
On 7 January 2012 20:00, Aurelien Jarno wrote:
> ARM still doesn't support 16GB buffers in 32-bit modes, replace the
> 16GB by 16MB in the comment.
>
> Signed-off-by: Aurelien Jarno
Reviewed-by: Peter Maydell
-- PMM
ocbp and ocbwb controls the writeback of a cache line to memory. They
are supposed to do nothing in case of a cache miss. Given QEMU only
partially emulate caches, it is safe to ignore these instructions.
This fixes a kernel oops when trying to access an rtl8139 NIC with
recent versions.
Signed-o
Fix .rel.plt sections in the output to not only include .rel.plt
sections from the input but also the .rel.iplt sections and to define
the hidden symbols __rel_iplt_start and __rel_iplt_end around
.rel.iplt as otherwise we get undefined references to these when
linking statically to a multiarch ena
Fix .rel.plt sections in the output to not only include .rel.plt
sections from the input but also the .rel.iplt sections and to define
the hidden symbols __rel_iplt_start and __rel_iplt_end around
.rel.iplt as otherwise we get undefined references to these when
linking statically to a multiarch ena
The AMBA IDs are supposed to be at the end of 0x2000 block, which the PL011 UART
allocates. Current QEMU implementation puts those IDs at 0x1000 offset, which is
wrong. The QEMU implementation also allocates only 0x1000 instead of 0x2000 of
space.
The fix is tested to work with Linux's PL011 drive
Since commit 347ac8e35661eff1c2b5ec74d11ee152f2a61856 which switched
target-i386 to softfloat, a few SSE instructions are not working
correctly anymore. It's especially noticeable on linux/x86-64 as SSE is
used default for floating point computation. For example GDM from Debian
Lenny is not usabl
ARM still doesn't support 16GB buffers in 32-bit modes, replace the
16GB by 16MB in the comment.
Signed-off-by: Aurelien Jarno
---
exec.c |2 +-
tcg/arm/tcg-target.c |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/exec.c b/exec.c
index b1d6602..7f9f730
On Thu, Jan 05, 2012 at 01:11:48PM +0100, Stefan Weil wrote:
> Coverity complained about right shifts of opcode (16, 18) which were
> larger than the size of opcode (16 bit).
>
> Using the correct shift values fixes this.
>
> Cc: Aurelien Jarno
> Signed-off-by: Stefan Weil
> ---
> target-sh4/t
On Tue, Nov 29, 2011 at 06:34:48AM +0100, Stefan Weil wrote:
> Commit 5632ae46d5bda798e971dae48ebb318ac2c3686a passes the address
> of i8259 to qemu_irq_proxy. i8259 is an auto variable with undefined
> value outside of mips_malta_init.
>
> This made the interrupt proxy unusable: either QEMU crash
On Sat, Jan 07, 2012 at 09:45:13AM +0100, Andreas Färber wrote:
> Hello,
>
> This series fixes endianness issues in the memory core.
> Apparently the actual byte swapping had not yet been tested.
>
> Together with the BIOS MemoryRegion patch and revert of m48t59 I/O base
> this restores the PReP
Hi all,
Just a few words to tell I totally disappeared from QEMU last summer due
to a burn-out. After successfully contributing back to some other
projects, I am going to slowly restart my activity on QEMU. I will try
to process the pending requests, but it might take some time. Don't
hesitate to
Jan Kiszka wrote:
> On 2012-01-05 18:07, Liu, Jinsong wrote:
>>> Sorry, it remains bogus to expose the tsc deadline timer feature on
>>> machines < pc-1.1. That's just like we introduced kvmclock only to
>>> pc-0.14 onward. The reason is that guest OSes so far running on
>>> qemu-1.0 or older witho
On Fri, 6 Jan 2012, Stefan Weil wrote:
Hello Avi,
latest QEMU seems to be broken when a system emulation with flash is started.
I did not run git bisect, but it looks like the problem started with this
change:
c5705a7728b4a6bc9e4f2d35911adbaf28042b25
Author: Avi Kivity 2011-12-20 14:59:12
On Wed, Jan 4, 2012 at 22:09, Anthony Liguori wrote:
> On 01/04/2012 01:50 PM, Peter Maydell wrote:
>>
>> On 4 January 2012 19:32, Avi Kivity wrote:
>>>
>>> The name 'Phys' conveys exactly the same information as
>>> 'target_phys_addr_t':
>>>
>>> - it has to be a physical address (no such thing
On Thu, Jan 5, 2012 at 17:45, Andreas Färber wrote:
> Am 15.10.2011 15:50, schrieb Blue Swirl:
>> Remove now incorrect address base arithmetic, missed by
>> 9936d6e42392f1440505dfa9df065eabd251cadf. Fixes Sparc64 boot.
>
> ...but breaks PReP boot:
>
> ERROR: BUG caught...
> BIOS execution exceptio
On Tue, Jan 3, 2012 at 15:34, Orit Wasserman wrote:
>
> Signed-off-by: Orit Wasserman
> ---
> arch_init.c | 67
> +++
> migration.c | 11 +
> migration.h | 9
> 3 files changed, 87 insertions(+), 0 deletions(-)
>
>
On Sat, Jan 07, 2012 at 10:00:56AM +0100, Gerhard Wiesinger wrote:
> On Fri, 6 Jan 2012, Kevin O'Connor wrote:
> >I'm not sure what a SCSI rom would do with a CD drive. My guess is
> >that it wouldn't map it to a BIOS visible drive id at all, as there's
> >no way to select an id with any assurance
On Sat, Jan 07, 2012 at 09:35:55AM +0100, Gerhard Wiesinger wrote:
[...]
> 5. Legacy option rom
> 6. DVD/CD [ata1-0: QEMU DVD-ROM ATAPI-4 DVD/CD]
> 7. iPXE (PCI 00:00.0)
>
> But there is still the iPXE ROM there (I think I didn't see iPXE
> because it is last one displayed and boot screen is fast
On 7 January 2012 04:40, Andreas Färber wrote:
> I noticed you're dropping a comment about tlb_flush(). Is that because
> it was dead code, or does the Memory API take care of it for us?
> (I assume the former because memory_region_set_enabled() does not take a
> CPUState* to operate on.)
Arrangi
I am investigating how LW is emulated from target-mips on x86 host.
However, i can not find where the OFFSET is passed in.
case OPC_LW:
save_cpu_state(ctx, 0);
op_ld_lw(t0, t0, ctx);
gen_store_gpr(t0, rt);
opn = "lw";
break;
||
||
\|
I have the same problem too. Anything other than each guest pixel
mapping to exactly one host pixel looks bad. There should be a way to
ensure that this is always the case (in fact, perhaps it should be the
default and there should be a command line switch to allow the
possibility of the display be
Coverity complained about right shifts of opcode (16, 18) which were
larger than the size of opcode (16 bit).
Using the correct shift values fixes this.
Cc: Aurelien Jarno
Signed-off-by: Stefan Weil
---
target-sh4/translate.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
dif
Am 06.01.2012 14:59, schrieb Gerd Hoffmann:
From: Hector Martin
Based on the implementation from Hector Martin
Hectors's implementation completely sidestepped the qemu usb system and
used libusb directly for usb device pass through. So I've ripped out
the libusb bits (or left them in disabled
Hello Avi,
latest QEMU seems to be broken when a system emulation with flash is
started.
I did not run git bisect, but it looks like the problem started with
this change:
c5705a7728b4a6bc9e4f2d35911adbaf28042b25
Author: Avi Kivity 2011-12-20 14:59:12
vmstate, memory: decouple vmstate from
There is a regression since commit c5705a7728b4a6bc9e4f2d35911adbaf28042b25
or some other recent change.
System emulation with a flash device raises an assertion in function
qemu_ram_set_idstr because no new_block is found at the requested addr.
The address of the memory region (mr->ram_addr) is
color_reg is expected to hold 32 bit values, so it was too small.
This bug was reported by coverity:
hw/sm501.c:624:
result_independent_of_operands:
color_reg >> 16 is 0 regardless of the values of its operands.
This occurs as the bitwise first operand of '&'.
Cc: Shin-ichiro Kawasaki
Signed-of
Reversing the order of the warning options and -Werror is important
when clang is used instead of gcc. It changes nothing for gcc.
Signed-off-by: Stefan Weil
---
configure |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/configure b/configure
index 640e815..93622e7 10075
Coverity complained about local variable key which was only partially
initiated. Only key.st_value was set. As this was also the only part
of key which was used in function symfind, the code could be optimized
by directly passing a pointer to orig_addr.
In bsd-user/elfload.c, fix ec822001a2f26eef8
Am 06.01.2012 17:01, schrieb Stefan Hajnoczi:
On Fri, Jan 06, 2012 at 09:19:45AM -0600, Anthony Liguori wrote:
Would folks be interested in participating in something like this?
If so, I can start organizing it.
I enjoy bug hunting and would volunteer.
Stefan
So do I.
Stefan
9634d9031c140b24c7ca0d8872632207f6ce7275 disabled unused code.
This patch removes what was left.
If do_pty is 2, the function returns immediately, so any later checks
for do_pty == 2 will always fail and can be removed together with
the code which is never executed. Then variable master is unused
Am 05.01.2012 01:24, schrieb Peter Maydell:
On 5 January 2012 00:16, Anthony Liguori wrote:
On 01/04/2012 05:33 PM, Peter Maydell wrote:
A lot of the usage of target_phys_addr_t in hw/ is actually not
handling addresses at all, but merely offsets into device IO regions
(ie as parameters to dev
Am 04.01.2012 15:47, schrieb Michael S. Tsirkin:
On Wed, Jan 04, 2012 at 04:28:42PM +0200, Avi Kivity wrote:
Commit d0ed8076cbdc261 converted the PCI config access to the memory
API, but also inadvertantly changed it to accept unaligned writes,
and corrupt the index register in the process. This
The RFBI_READ/RFBI_STATUS code incorrectly uses chip[0] when it should
be using chip[1]. Andrzej Zaborowski confirmed this
bug since I don't know this code well.
Reported-by: Dr David Alan Gilbert
Signed-off-by: Stefan Hajnoczi
---
hw/omap_dss.c |4 ++--
1 files changed, 2 insertions(+),
On Sat, Jan 7, 2012 at 3:09 AM, Peter Maydell wrote:
> On 6 January 2012 20:42, Anthony Liguori wrote:
>> On 01/06/2012 02:02 PM, Andreas Färber wrote:
>>> i) Unless it's a build fix, I propose defining a minimum review time
>>> before a patch is applied to a (sub)maintainer's queue.
>
>> I disag
Am 07.01.2012 10:55, schrieb Igor Mitsyanko:
> On 06.01.2012 11:11 PM, Andreas Färber wrote:
>> Am 06.01.2012 20:10, schrieb Igor Mitsyanko:
>>> On 01/06/2012 10:45 PM, Peter Maydell wrote:
On 6 January 2012 18:37, Igor Mitsyanko wrote:
> On 01/06/2012 12:02 AM, Mark Langsdorf wrote:
>>>
On Fri, 6 Jan 2012, Kevin O'Connor wrote:
I'm not sure what a SCSI rom would do with a CD drive. My guess is
that it wouldn't map it to a BIOS visible drive id at all, as there's
no way to select an id with any assurance that it wont conflict with
one chosen by the BIOS or another rom. If QEMU
On 06.01.2012 11:11 PM, Andreas Färber wrote:
Am 06.01.2012 20:10, schrieb Igor Mitsyanko:
On 01/06/2012 10:45 PM, Peter Maydell wrote:
On 6 January 2012 18:37, Igor Mitsyanko wrote:
On 01/06/2012 12:02 AM, Mark Langsdorf wrote:
+if (!cpu_model) {
+cpu_model = "cortex-a9";
+
Hello,
This series fixes endianness issues in the memory core.
Apparently the actual byte swapping had not yet been tested.
Together with the BIOS MemoryRegion patch and revert of m48t59 I/O base
this restores the PReP machine to previous behavior.
Regards,
Andreas
Cc: Avi Kivity
Cc: Anthony L
Commit a621f38de85598a13d8d8524d1a94fc6a1818215 (Direct dispatch
through MemoryRegion) moved byte swaps to a central function.
Add a missing break, so that long-sized byte swaps don't abort.
Signed-off-by: Andreas Färber
Cc: Avi Kivity
---
memory.c |1 +
1 files changed, 1 insertions(+), 0
Since commit be675c972088eba210e18dc125613e9f205a6bfb (memory: move
endianness compensation to memory core) it was checking for
TARGET_BIG_ENDIAN instead of TARGET_WORDS_BIGENDIAN, thereby not
swapping correctly for Big Endian targets.
Signed-off-by: Andreas Färber
Cc: Avi Kivity
---
memory.c |
On Thu, 5 Jan 2012, Kevin O'Connor wrote:
On Thu, Jan 05, 2012 at 11:20:37AM +0200, Gleb Natapov wrote:
On Thu, Jan 05, 2012 at 10:09:44AM +0100, Gerhard Wiesinger wrote:
But as far as I remember therefore the option ROM registers through
BIOS for INT 19h booting. So Seabios should know it tha
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