Re: [Qemu-devel] ARM v4t support

2009-11-28 Thread Rob Landley
On Friday 27 November 2009 05:35:26 Filip Navara wrote: > On Fri, Nov 27, 2009 at 12:17 PM, Vincent Sanders wrote: > > I appear to be unable to take a hint, your silence on this patch in > > the past probably ought to have been a clue. however this will be the > > last time I bother to try and ge

[Qemu-devel] Poking at the qemu-m68k tree.

2009-11-28 Thread Rob Landley
So I grabbed the qemu-m68k repository from git://gitorious.org/qemu-m68k/qemu-m68k.git and built it, and the m68040 emulation seems to be running busybox built for m68k rather than coldfire. (Yay!) I'd like to A) help push this upstream into mainline qemu, B) add a board emulating an Atari ST

Re: [Qemu-devel] PATCH: Building qemu on OpenSolaris 2009.06 (SPARC) host

2009-11-28 Thread Andreas Färber
Hi Palle, Am 28.11.2009 um 21:03 schrieb Palle Lyckegaard: On Fri, 27 Nov 2009, Andreas Färber wrote: I can ack the softfloat part (fixes redefinition warnings) and the tap part (fixes an unresolved symbol TFR). But what does the cpu.h part fix? the cpu.h part is an attempt to avoid warn

Re: [Qemu-devel] PATCH: Building qemu on OpenSolaris 2009.06 (SPARC) host

2009-11-28 Thread Palle Lyckegaard
On Fri, 27 Nov 2009, Andreas Färber wrote: I can ack the softfloat part (fixes redefinition warnings) and the tap part (fixes an unresolved symbol TFR). But what does the cpu.h part fix? Andreas Hi Andreas, the cpu.h part is an attempt to avoid warnings about e.g. PSR_EF being redefined

Re: [Qemu-devel] [PATCH 09/11] target-mips: add mips16 instruction decoding

2009-11-28 Thread Aurelien Jarno
On Mon, Nov 23, 2009 at 12:50:07PM -0800, Nathan Froyd wrote: > There's no good way to add this incrementally, so we do it all at once. > The only changes to shared code are in handle_delay_slot. We need to > flip ISAMode when doing a jump-and-exchange. We also need to set > ISAMode the low bit o

Re: [Qemu-devel] [PATCH 01/11] target-mips: add ISAMode bits for mips16 execution

2009-11-28 Thread Aurelien Jarno
On Mon, Nov 23, 2009 at 12:49:59PM -0800, Nathan Froyd wrote: > > Signed-off-by: Nathan Froyd > --- > target-mips/cpu.h |1 + > target-mips/translate.c |2 ++ > 2 files changed, 3 insertions(+), 0 deletions(-) > > diff --git a/target-mips/cpu.h b/target-mips/cpu.h > index 82f9a38.

Re: [Qemu-devel] [PATCH 00/11] target-mips: add mips16 support

2009-11-28 Thread Aurelien Jarno
Hi, On Mon, Nov 23, 2009 at 12:49:58PM -0800, Nathan Froyd wrote: > This patchset adds MIPS16 support to the MIPS backend. MIPS16 is a > compact encoding of a subset of the MIPS integer instructions, similar > to ARM's Thumb mode. The processor enters MIPS16 mode by executing a > special jump in

Re: [Qemu-devel] [PATCH 03/11] target-mips: change interrupt bits to be mips16-aware

2009-11-28 Thread Aurelien Jarno
On Mon, Nov 23, 2009 at 12:50:01PM -0800, Nathan Froyd wrote: > > Signed-off-by: Nathan Froyd > --- > target-mips/helper.c| 47 > ++- > target-mips/op_helper.c | 10 +++--- > 2 files changed, 33 insertions(+), 24 deletions(-) > > diff --g

Re: [Qemu-devel] [PATCH 06/11] target-mips: add gen_base_offset_addr

2009-11-28 Thread Aurelien Jarno
On Mon, Nov 23, 2009 at 12:50:04PM -0800, Nathan Froyd wrote: > This is a common pattern in existing code. We'll also use it to > implement the mips16 SAVE/RESTORE instructions. > > Signed-off-by: Nathan Froyd > --- > target-mips/translate.c | 40 > 1