Re: [Qemu-devel] MIPS COP1X (and related) instructions

2007-12-28 Thread Thiemo Seufer
Richard Sandiford wrote: > All MIPS COP1X instructions currently require the FPU to be in 64-bit > mode. My understanding is that this is too restrictive, and that the > base conditions are different for different revisions of the ISA: > > MIPS IV: > COP1X instructions are available when th

[Qemu-devel] [PATCH] sparc32: set SS-5 iommu version to turbosparc to match default cpu

2007-12-28 Thread Robert Reif
diff -p -u -r1.73 sun4m.c --- hw/sun4m.c 28 Dec 2007 20:59:23 - 1.73 +++ hw/sun4m.c 28 Dec 2007 21:25:06 - @@ -698,7 +698,7 @@ static const struct hwdef hwdefs[] = { .me_irq = 30, .cs_irq = 5, .machine_id = 0x80, -.iommu_version = 0x0400, +

[Qemu-devel] qemu Makefile.target qemu-doc.texi vl.c hw/boar...

2007-12-28 Thread Blue Swirl
CVSROOT:/cvsroot/qemu Module name:qemu Changes by: Blue Swirl 07/12/28 20:59:23 Modified files: . : Makefile.target qemu-doc.texi vl.c hw : boards.h sun4m.c sun4m.h Added files: hw : sun4c_intctl.c Log message:

[Qemu-devel] qemu Makefile.target qemu-doc.texi vl.c hw/boar...

2007-12-28 Thread Blue Swirl
CVSROOT:/cvsroot/qemu Module name:qemu Changes by: Blue Swirl 07/12/28 20:57:43 Modified files: . : Makefile.target qemu-doc.texi vl.c hw : boards.h sun4m.c sun4m.h target-sparc : op_helper.c Added files: hw

[Qemu-devel] qemu/target-sparc op_helper.c

2007-12-28 Thread Blue Swirl
CVSROOT:/cvsroot/qemu Module name:qemu Changes by: Blue Swirl 07/12/28 18:50:24 Modified files: target-sparc : op_helper.c Log message: Improved ASI debugging (Robert Reif) CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-sparc/op_helper.c?cvsroo

[Qemu-devel] qemu/hw slavio_intctl.c

2007-12-28 Thread Blue Swirl
CVSROOT:/cvsroot/qemu Module name:qemu Changes by: Blue Swirl 07/12/28 18:48:39 Modified files: hw : slavio_intctl.c Log message: Fix master interrupt register masking CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/slavio_intctl.c?cvsroot

[Qemu-devel] qemu/hw slavio_intctl.c

2007-12-28 Thread Blue Swirl
CVSROOT:/cvsroot/qemu Module name:qemu Changes by: Blue Swirl 07/12/28 18:46:01 Modified files: hw : slavio_intctl.c Log message: Fix system read address mask (Robert Reif) CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/slavio_intctl.c?cv

[Qemu-devel] [PATCH] sparc32: add asi debug info

2007-12-28 Thread Robert Reif
Add asi debug info printing. diff -p -u -r1.61 op_helper.c --- target-sparc/op_helper.c10 Dec 2007 19:58:20 - 1.61 +++ target-sparc/op_helper.c28 Dec 2007 17:23:29 - @@ -6,6 +6,7 @@ //#define DEBUG_MXCC //#define DEBUG_UNALIGNED //#define DEBUG_UNASSIGNED +//#define DEBUG_A

[Qemu-devel] [PATCH] sparc32: better unassigned memory debug message

2007-12-28 Thread Robert Reif
Pass the asi number in is_asi. This works because asi 0 is not a valid asi. Print out the type of access (read, write, exec). diff -p -u -r1.61 op_helper.c --- target-sparc/op_helper.c10 Dec 2007 19:58:20 - 1.61 +++ target-sparc/op_helper.c28 Dec 2007 17:07:49 - @@ -416,7 +41

[Qemu-devel] qemu/target-mips translate_init.c

2007-12-28 Thread Thiemo Seufer
CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer 07/12/28 12:35:05 Modified files: target-mips: translate_init.c Log message: Set FCR0.F64 for MIPS64R2-generic, by Richard Sandiford. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/t

[Qemu-devel] MIPS COP1X (and related) instructions

2007-12-28 Thread Richard Sandiford
All MIPS COP1X instructions currently require the FPU to be in 64-bit mode. My understanding is that this is too restrictive, and that the base conditions are different for different revisions of the ISA: MIPS IV: COP1X instructions are available when the XX (CU3) bit of the status regi

[Qemu-devel] Set FCR0.F64 for MIPS64R2-generic

2007-12-28 Thread Richard Sandiford
MIPS64R2-generic implements the MIPS-3D ASE, so I assume it should also have a 64-bit FPU. Please apply if OK. Richard Index: target-mips/translate_init.c === RCS file: /sources/qemu/qemu/target-mips/translate_init.c,v retrieving re