[Qemu-devel] I2C/SMBus framework

The attached patch implements an I2C/SMBus framework for qemu. It provides an API for connecting emulated I2C devices, and implements SMBus as a layer on top of that. Currently the only i2c device in CVS is the piix eeprom. I've tested this as much as I can - linux successfully reads the eeprom

[Qemu-devel] Patch: support OSS on solaris

I've recrafted my patch for supporting OpenSound System on Solaris by checking for it automatically, instead of providing an option. Also added a status flag on whether OSS is enabled or not. Ben--- qemu.ORIG/configure 2007-05-09 10:06:06.0 -0400 +++ qemu/configure 2007-05-12 13:30:31.29

[Qemu-devel] qemu cpu-exec.c

CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer 07/05/12 16:57:43 Modified files: . : cpu-exec.c Log message: Update debug output. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/cpu-exec.c?cvsroot=qemu&r1=1.103&r2=1.104

[Qemu-devel] Block driver and constant sector size

Hi, currently the block driver in qemu only handles blocks (or sectors) which are 512 bytes long, this is ideal if the device you are emulating have a block size which is a multiple of 512. Unfortunately, this is not always the case, for example an audio CD (CD-DA) or a CD in mode 2 have a se

[Qemu-devel] [PATCH][MIPS] Full MIPS64 MMU implementation

Hi all, The patch below finally adds full support for MIPS64 MMU. With it I am able to boot a 64-bit MALTA kernel up to a kernel panic, as it does not detect any devices. There is probably a bug somewhere in map_address(). Note that the long hardcoded masks are a bit ugly, but I am working on a p

[Qemu-devel] [MIPS][PATCH] Fix mfc0 and dmtc0 instructions on MIPS64

Hi all, The patch below fixes the mfc0 and dmtc0 instructions for the MIPS64 target: - The mfc0 instruction should return the 32 lowest bits of the coprocessor 0 register sign extended to 64-bit. - The mtc0 instruction should do the same as the dmtc0 instruction for 64-bit coprocessor reg

[Qemu-devel] [PATCH][MIPS] MMU code improvements

Hi all, Please find below a patch to improve the MMU code on the MIPS target. It fixes map_address() invalidate_tlb() and do_tlbp() for page sizes greater than 4kB. The VPN contained in a TLB should be masked with the page mask of the same TLB as the VPN value may not be aligned. This is explici

[Qemu-devel] qemu/hw nand.c pxa.h pxa2xx.c pxa2xx_lcd.c spitz.c

CVSROOT:/sources/qemu Module name:qemu Changes by: Andrzej Zaborowski 07/05/12 09:19:36 Modified files: hw : nand.c pxa.h pxa2xx.c pxa2xx_lcd.c spitz.c Log message: Correct NAND erase block size. Misc fixes in Spitz code. CVSWeb URLs: http://cvs