thanks
Index: hw/lsi53c895a.c
===
RCS file: /sources/qemu/qemu/hw/lsi53c895a.c,v
retrieving revision 1.4
diff -r1.4 lsi53c895a.c
1048a1049
> s->carry = op1;
Index: hw/smc91c111.c
===
hi again,
here's a patch for the changes i described before.
best regards
marcel block
--- qemu-0.9.0/hw/ne2000.c 2007-02-06 00:01:54.0 +0100
+++ ne2000.c 2007-04-02 03:02:32.0 +0200
@@ -206,7 +206,7 @@ static int ne2000_buffer_full(NE2000Stat
index = s->curpag << 8;
andrzej zaborowski wrote:
> Hi,
> I looked at how the embedding of a standard VGA in the VMware SVGA
> could be done (mainly out of curiosity) and it wasn't difficult. I had
> to make small changes in hw/vga.c but I think it's made more flexible
> now. Attached is a second version of the VMware SV
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer 07/04/02 01:10:47
Modified files:
. : Makefile.target sdl.c vl.c vl.h
hw : cirrus_vga.c pc.c vga.c vga_int.h
Added files:
hw : vmware_vga.c
Log mes
On Sunday 01 April 2007, Thiemo Seufer wrote:
> Mike Frysinger wrote:
> > obvious fixup ... getsockopt() takes a socklen_t, not an int
>
> This is incorrect. Its initial value is sizeof(val).
attached
-mike
pgpxUDF1iyg7E.pgp
Description: PGP signature
--- linux-user/syscall.c
+++ linux-user/sysc
On Sun, Apr 01, 2007 at 07:30:40PM +0200, Aurelien Jarno wrote:
> Blue Swirl a écrit :
> >> According to the SPARCv8 and SPARCv9 manuals, the jmpl, rett and return
> >> instructions should generate a mem_address_not_aligned trap if either
> >> of the low-order two bits of the target address is nonz
Blue Swirl a écrit :
> Sparc32 system emulator tests
>
For your information I recently tried to build gcc 4.1 in bootstrap mode
on both QEMU and real hardware (SparcStation 4) for C, C++, objc and
fortran. I than run the testsuite.
The testsuite gave identical results on both emulated and real h
Sparc32 system emulator tests
Tested installing with a CD image. Direct kernel means using -kernel
option.
Serial (opposite of graphical) uses -nographic option.
Colour map is slightly buggy on most installs. Bug in OpenBIOS within Forth
function 'interpose' prevents BSDs from working.
Auror
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer 07/04/01 19:01:40
Modified files:
. : block-qcow2.c
Log message:
Qcow2 corruption fix, by Juergen Keil.
CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/block-qcow2.c?cvsroot=
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer 07/04/01 18:54:44
Modified files:
. : Makefile.target configure
fpu: softfloat-native.c softfloat.h
Log message:
Solaris 9/x86 support, by Ben Taylor.
CVSWeb U
Mike Frysinger wrote:
> obvious fixup ... getsockopt() takes a socklen_t, not an int
> -mike
This is incorrect. Its initial value is sizeof(val).
Thiemo
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer 07/04/01 18:31:35
Modified files:
linux-user : syscall.c
Log message:
Conditionalize more syscall implementations, by Mike Frysinger.
CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/l
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer 07/04/01 18:26:11
Modified files:
hw : i8259.c
Log message:
Single mode for PIC i8259, by Bernhard Kauer.
CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/hw/i8259.c?cvsroot=qe
Thomas Schwinge wrote:
> [I'm not subscribed to the mailing list, so please keep me cced.]
>
>
> Hello!
>
> We kept wondering why the GNU/Hurd's `fatfs' translator (think Unix
> kernel file system driver) didn't want to ``eat'' the QEMU vvfat
> on-the-fly served floppy images (created from a dir
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer 07/04/01 17:56:37
Modified files:
. : elf_ops.h loader.c vl.h
hw : arm_boot.c mips_malta.c mips_r4k.c sun4m.c
sun4u.c
Log message:
Imp
Blue Swirl a écrit :
>> According to the SPARCv8 and SPARCv9 manuals, the jmpl, rett and return
>> instructions should generate a mem_address_not_aligned trap if either
>> of the low-order two bits of the target address is nonzero.
>
> This is true, but in that case alignment should be enforced fo
According to the SPARCv8 and SPARCv9 manuals, the jmpl, rett and return
instructions should generate a mem_address_not_aligned trap if either
of the low-order two bits of the target address is nonzero.
This is true, but in that case alignment should be enforced for loads ands
stores as well. Th
Hi all,
According to the SPARCv8 and SPARCv9 manuals, the jmpl, rett and return
instructions should generate a mem_address_not_aligned trap if either
of the low-order two bits of the target address is nonzero.
The patch below implements that.
Bye,
Aurelien
Index: target-sparc/cpu.h
===
When the program counter is at the very start of a memory block
amd there is no page allocated before this block, QEMU may fail
with a fatal error ("Trying to execute code outside RAM or ROM").
In my case, a MIPS system had code in flash starting at 0xb000.
I had a remote debugger attached to
On Sun, Apr 01, 2007 at 06:24:34PM +0200, Blue Swirl wrote:
> CVSROOT: /cvsroot/qemu
> Module name: qemu
> Changes by: Blue Swirl 07/04/01 16:23:36
>
> Modified files:
> target-sparc : translate.c
>
> Log message:
> Fix off-by-one error
>
Looking at the code of this comm
CVSROOT:/cvsroot/qemu
Module name:qemu
Changes by: Blue Swirl 07/04/01 16:23:36
Modified files:
target-sparc : translate.c
Log message:
Fix off-by-one error
CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/target-sparc/translate.c?cvsroot=qemu&r1=1.43&
CVSROOT:/cvsroot/qemu
Module name:qemu
Changes by: Blue Swirl 07/04/01 16:05:41
Modified files:
. : vl.h
hw : slavio_intctl.c slavio_misc.c slavio_serial.c
slavio_timer.c sun4m.c
Log message:
Change Spa
CVSROOT:/cvsroot/qemu
Module name:qemu
Changes by: Blue Swirl 07/04/01 15:55:29
Modified files:
. : vl.c vl.h
hw : slavio_intctl.c sun4m.c
target-sparc : translate.c
Log message:
Add SparcStation-10 machine
CVSWeb UR
CVSROOT:/cvsroot/qemu
Module name:qemu
Changes by: Blue Swirl 07/04/01 15:44:43
Modified files:
. : vl.c vl.h
hw : sun4m.c
Log message:
Reorganise Sun4m to allow other machine types
CVSWeb URLs:
http://cvs.savannah.gnu.org/vie
CVSROOT:/cvsroot/qemu
Module name:qemu
Changes by: Blue Swirl 07/04/01 15:38:17
Modified files:
target-sparc : op.c translate.c
Log message:
Fix Sparc shift ops (Aurelien Jarno)
CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/target-sparc/op.c?cvsroot
CVSROOT:/cvsroot/qemu
Module name:qemu
Changes by: Blue Swirl 07/04/01 15:15:36
Modified files:
target-sparc : cpu.h op_helper.c translate.c
Log message:
Fix Sparc lda/ldda/sta/stda asi handling, fault on misaligned register
ldd/std
and illegal cwp on wrpsr (Aure
CVSROOT:/cvsroot/qemu
Module name:qemu
Changes by: Blue Swirl 07/04/01 15:08:21
Modified files:
target-sparc : cpu.h translate.c
Log message:
Fix Sparc co-processor ops (Aurelien Jarno)
CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/target-sparc/cpu.
CVSROOT:/cvsroot/qemu
Module name:qemu
Changes by: Blue Swirl 07/04/01 15:05:09
Modified files:
target-sparc : translate.c
Log message:
Fix Sparc ASR handling (Aurelien Jarno)
CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/target-sparc/translate.c?cv
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer 07/04/01 12:36:18
Modified files:
hw : mips_malta.c mips_r4k.c
target-mips: exec.h mips-defs.h op.c op_helper.c
op_helper_mem.c op_mem.c translate.c
On 3/31/07, James Jacobs <[EMAIL PROTECTED]> wrote:
> Using the start.bat file included with the QEMU package (except changing
> cd-rom and hard disk image filenames as appropriate).
> I haven't adjusted any audio settings, I'm using whatever the defaults
are.
which package ?
you mentionned a
On Sun, Apr 01, 2007 at 11:32:06AM +0200, Blue Swirl wrote:
> >The shift instructions on the SPARC target currently take into account
> >the whole register as the shift count. According to the SPARC v8 and v9
> >manuals, only the lower 5 bits should be taken into account for 32-bit
> >instructions
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer 07/04/01 11:16:48
Modified files:
. : .cvsignore Makefile Makefile.target configure
target-mips: op_helper.c
Log message:
MIPS64 configurations.
CVSWeb URLs:
http://cv
The shift instructions on the SPARC target currently take into account
the whole register as the shift count. According to the SPARC v8 and v9
manuals, only the lower 5 bits should be taken into account for 32-bit
instructions (SLL, SRL, SRA), and only the lower 6 bits for 64-bit
instructions (SLL
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