I'm not on the list, so any replies should be CC'ed to me personally.
I have attached a very small patch to implement TSD flag checking when
the RDTSC instruction is executed on the x86 guest architecture. A GPF
is supposed to be raised if the CPL is not 0 and the TSD flag in the
CR4 register is e
The attached patch implements m68k disassembly in qemu. It's mainly just
importing the relevant files from upstream binutils/gdb, like the existing
disassembly code.
I realise mainline qemu doesn't have a m68k target support (yet!), but it does
[nominally] support m68k hosts so this isn't total
Following is the list of some easy to reproduce bugs in QEMU,
perhaps someone will have motivation to fix them:
Preliminary:
cvs -d :ext:[EMAIL PROTECTED]:/cvsroot/qemu login
cvs -d :ext:[EMAIL PROTECTED]:/cvsroot/qemu co qemu
cd qemu
./configure --target-list=i386-softmmu
make
I have implemented .qvm as a test in Q.
Here is a sample configuration.plist and some additions to my initial
proposal:
"http://www.apple.com/DTDs/PropertyList-1.0.dtd";>
About
Author
Q
Copyright
none
Date
2005-08-07T19:25:41Z
Descrip
The patch below makes the Arm CPU debugging dumps show the Thumb state bit
symbolically.
Paul
Index: target-arm/translate.c
===
RCS file: /cvsroot/qemu/qemu/target-arm/translate.c,v
retrieving revision 1.26
diff -u -p -r1.26 transla
The attached patch adds partial support for ARM NPTL binaries.
It implements the following things:
- The Arm magic kernel code page. This is used on recent Arm kernels to
provide efficient access to kernel/CPU features. For example atomic
operations, and reading the TLS register (which may or m
