[PATCH 2/2] hw/ide/core.c: Implement ATA INITIALIZE_DEVICE_PARAMETERS command

CHS-based disk utilities and operating systems may adjust the logical geometry of a hard drive to cope with the expectations or limitations of software using the ATA INITIALIZE_DEVICE_PARAMETERS command. Prior to this patch, INITIALIZE_DEVICE_PARAMETERS was a nop that always returned success, rais

[PATCH 1/2] qpci_device_enable: Allow for command bits hardwired to 0

. Signed-off-by: Lev Kujawski --- tests/qtest/ide-test.c | 1 + tests/qtest/libqos/pci.c | 13 +++-- tests/qtest/libqos/pci.h | 1 + 3 files changed, 9 insertions(+), 6 deletions(-) diff --git a/tests/qtest/ide-test.c b/tests/qtest/ide-test.c index 5bcb75a7e5..85a3967063 100644 --- a

[PATCH v2 1/7] piix_ide_reset: Use pci_set_* functions instead of direct access

Eliminate the remaining TODOs in hw/ide/piix.c by: * Using pci_set_{size} functions to write the PIIX PCI configuration space instead of manipulating it directly as an array; and * Documenting the default register values by reference to the controlling specification. Signed-off-by: Lev

[PATCH v2 3/7] hw/ide/core: Clear LBA and drive bits for EXECUTE DEVICE DIAGNOSTIC

ed to zero" for EXECUTE DEVICE DIAGNOSTIC. This deviation was uncovered by the ATACT Device Testing Program written by Hale Landis. Signed-off-by: Lev Kujawski --- hw/ide/core.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/hw/ide/core.c b/hw/ide/core.c index 7cbc0a54a7..b747191

[PATCH v2 2/7] tests/qtest/ide-test.c: Create disk image for use as a secondary

Change 'tmp_path' into an array of two members to accommodate another disk image of size TEST_IMAGE_SIZE. This facilitates testing ATA protocol aspects peculiar to secondary devices on the same controller. Signed-off-by: Lev Kujawski --- tests/qtest/ide-t

[PATCH v2 4/7] tests/qtest/ide-test: Verify that DIAGNOSTIC clears DEV to zero

Verify correction of EXECUTE DEVICE DIAGNOSTIC introduced in commit 72423831c3 (hw/ide/core: Clear LBA and drive bits for EXECUTE DEVICE DIAGNOSTIC, 2022-05-28). Signed-off-by: Lev Kujawski --- tests/qtest/ide-test.c | 33 + 1 file changed, 33 insertions(+) diff

[PATCH v2 5/7] qpci_device_enable: Allow for command bits hardwired to 0

the command_disabled word to indicate bits hardwired to 0. * tests/qtest/libqos/pci.c: Verify that hardwired bits are actually hardwired. Signed-off-by: Lev Kujawski --- tests/qtest/libqos/pci.c | 13 +++-- tests/qtest/libqos/pci.h | 1 + 2 files changed, 8 insertions(+), 6

[PATCH v2 6/7] hw/ide/piix: Ignore writes of hardwired PCI command register bits

PCI_COMMAND_MEMORY is hardwired in the PIIX3/4 IDE controller. Signed-off-by: Lev Kujawski --- hw/ide/piix.c | 15 +++ tests/qtest/ide-test.c | 1 + 2 files changed, 16 insertions(+) diff --git a/hw/ide/piix.c b/hw/ide/piix.c index de1f4f0efb..64620c5778 100644 --- a/hw/ide

[PATCH v2 7/7] hw/ide/core.c: Implement ATA INITIALIZE_DEVICE_PARAMETERS command

geometry of the hard disk within the new field 'reset_reverts'. Signed-off-by: Lev Kujawski --- hw/ide/core.c | 29 ++--- include/hw/ide/internal.h | 3 +++ 2 files changed, 29 insertions(+), 3 deletions(-) diff --git a/hw/ide/core.c b/hw/ide/core.c

[PATCH] hw/block/hd-geometry: Do not override specified bios-chs-trans

e translation (*ptrans) in the trace rather than what was guessed. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/56 Buglink: https://bugs.launchpad.net/qemu/+bug/1745312 Signed-off-by: Lev Kujawski --- hw/block/hd-geometry.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) di

[PATCH v3 2/2] hw/ide/piix: Ignore writes of hardwired PCI command register bits

testing model to indicate that PCI_COMMAND_MEMORY is hardwired in the PIIX3/4 IDE controller. Signed-off-by: Lev Kujawski --- (v2) Use QEMU's built-in PCI bit-masking support rather than attempting to manually filter writes. Thanks to Philippe Mathieu-Daude and Michael S. Tsirki

[PATCH v3 1/2] qpci_device_enable: Allow for command bits hardwired to 0

the command_disabled word to indicate bits hardwired to 0. * tests/qtest/libqos/pci.c: Verify that hardwired bits are actually hardwired. Signed-off-by: Lev Kujawski --- tests/qtest/libqos/pci.c | 13 +++-- tests/qtest/libqos/pci.h | 1 + 2 files changed, 8 insertions(+), 6

[PATCH v3 0/2] Re: hw/ide/piix: Ignore writes of hardwired PCI command register bits

> On Tue, Sep 06, 2022 at 10:23:57AM -0400, Michael S. Tsirkin wrote: > > On Thu, Jun 02, 2022 at 08:47:31PM +0000, Lev Kujawski wrote: > > > --- > > > This revised patch uses QEMU's built-in PCI bit-masking support rather > > > than attempting to ma

[PATCH 2/2] tests/qtest/ide-test: Verify READ NATIVE MAX ADDRESS is not limited

Verify that the ATA command READ NATIVE MAX ADDRESS returns the last valid CHS tuple for the native device rather than any limit established by INITIALIZE DEVICE PARAMETERS. Signed-off-by: Lev Kujawski --- tests/qtest/ide-test.c | 47 +- 1 file changed

[PATCH 1/2] hw/ide/core.c (cmd_read_native_max): Avoid limited device parameters

the prior behavior was that setting zero sectors per track could lead to an FPE within ide_set_sector(). Thanks to Alexander Bulekov for reporting this issue. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1243 Signed-off-by: Lev Kujawski --- hw/ide/core.c | 21 + 1 fi

[PATCH 2/2] hw/ide/piix: Ignore writes of hardwired PCI command register bits

, because the PIIX IDE controllers do not define their own state. * tests/qtest/ide-test.c Use the command_disabled field of the QPCIDevice testing model to indicate that PCI_COMMAND_MEMORY is hardwired within PIIX 3/4 IDE controllers. Signed-off-by: Lev Kujawski --- hw/core/machine.c

Re: [PATCH v3 2/2] hw/ide/piix: Ignore writes of hardwired PCI command register bits

e PIIX 3/4 IDE registers for hardwired bits (only what I encountered testing proprietary firmware - PCICMD), and I do not have access to my PIIX 3 system at the moment. Kind regards, Lev Kujawski Lev Kujawski (2): qpci_device_enable: Allow for command bits hardwired to 0 hw/ide/piix: Ignore wri

[PATCH 1/2] qpci_device_enable: Allow for command bits hardwired to 0

the command_disabled word to indicate bits hardwired to 0. * tests/qtest/libqos/pci.c: Verify that hardwired bits are actually hardwired. Signed-off-by: Lev Kujawski --- tests/qtest/libqos/pci.c | 13 +++-- tests/qtest/libqos/pci.h | 1 + 2 files changed, 8 insertions(+), 6

Re: [PATCH v3 1/2] qpci_device_enable: Allow for command bits hardwired to 0

Michael S. Tsirkin writes: > On Sun, Sep 25, 2022 at 09:37:58AM +0000, Lev Kujawski wrote: >> Devices like the PIIX3/4 IDE controller do not support certain modes >> of operation, such as memory space accesses, and indicate this lack of >> support by hardwiring the ap

Re: [PATCH 1/2] hw/ide/core.c (cmd_read_native_max): Avoid limited device parameters

John Snow writes: > On Mon, Oct 10, 2022 at 4:52 AM Lev Kujawski wrote: >> >> Always use the native CHS device parameters for the ATA commands READ >> NATIVE MAX ADDRESS and READ NATIVE MAX ADDRESS EXT, not those limited >> by the ATA command INITIALIZE_DEVICE_PARA

[PATCH] ide_ioport_read: Return lower octet of data register instead of 0xFF

y ATA device, such as an optical drive. Resolves: * [Bug 1639394] Unable to boot Solaris 8/9 x86 under Fedora 24 Signed-off-by: Lev Kujawski --- hw/ide/core.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/ide/core.c b/hw/ide/core.c index 3a5afff5d7..c2caa54285 100644

[PATCH 1/4] hw/ide/atapi.c: Correct typos (CD-CDROM -> CD-ROM)

Signed-off-by: Lev Kujawski --- hw/ide/atapi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/ide/atapi.c b/hw/ide/atapi.c index b626199e3d..88b2890faf 100644 --- a/hw/ide/atapi.c +++ b/hw/ide/atapi.c @@ -318,7 +318,7 @@ static void ide_atapi_cmd_reply(IDEState *s

[PATCH 2/4] hw/ide/core: Clear LBA and drive bits for EXECUTE DEVICE DIAGNOSTIC

ed to zero" for EXECUTE DEVICE DIAGNOSTIC. This deviation was uncovered by the ATACT Device Testing Program written by Hale Landis. Signed-off-by: Lev Kujawski --- hw/ide/core.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/hw/ide/core.c b/hw/ide/core.c index c2caa54285..5a24547

[PATCH 3/4] piix_ide_reset: Use pci_set_* functions instead of direct access

Eliminates the remaining TODOs in hw/ide/piix.c by: - Using pci_set_{size} functions to write the PIIX PCI configuration space instead of manipulating it directly as an array; and - Documenting default register values by reference to the controlling specification. Signed-off-by: Lev Kujawski

[PATCH 4/4] hw/ide/piix: Ignore writes of hardwired PCI command register bits

register would be left in an unspecified state without this patch. Signed-off-by: Lev Kujawski --- hw/ide/piix.c | 25 + 1 file changed, 25 insertions(+) diff --git a/hw/ide/piix.c b/hw/ide/piix.c index 76ea8fd9f6..f1d1168ecd 100644 --- a/hw/ide/piix.c +++ b/hw/ide/piix.c

[PATCH v2] hw/ide/piix: Ignore writes of hardwired PCI command register bits

register would be left in an unspecified state without this patch. Signed-off-by: Lev Kujawski --- This revised patch uses QEMU's built-in PCI bit-masking support rather than attempting to manually filter writes. Thanks to Philippe Mathieu- Daude and Michael S. Tsirkin for review and the pointer.

[PATCH 1/1] hw/ide/core: Accumulate PIO output within io_buffer prior to pwritev

sectors are transferred. Up to a 50% increase in PIO throughput can be achieved thanks to the reduction in system call overhead and writing larger blocks (up to 128 KiB, with the size limited by IDE_DMA_BUF_SECTORS). Signed-off-by: Lev Kujawski --- hw/ide/core.c | 62