[PATCH v2 2/5] hw/net:ftgmac100: support 64 bits dma dram address for AST2700

2024-07-03 Thread Jamin Lin via
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35) And the base address of dram is "0x4 " which is 64bits address. It have "Normal Priority Transmit Ring Base Address Register High(0x17C)", "High Priority Transmit Ring Base Address Register High(0x184)" and "Receive Ring Base Addr

[PATCH v2 3/5] aspeed/soc: update to ftgmac100_high model for AST2700

2024-07-03 Thread Jamin Lin via
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35) And the base address of dram is "0x4 " which is 64bits address. Update its network model to ftgmac100_high to support 64bits dram address DMA. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast27x0.c | 3 ++- 1 file changed, 2 inse

[PATCH v2 4/5] hw/block: m25p80: support quad mode for w25q01jvq

2024-07-03 Thread Jamin Lin via
According to the w25q01jv datasheet at page 16, it is required to set QE bit in "Status Register 2". Besides, users are able to utilize "Write Status Register 1(0x01)" command to set QE bit in "Status Register 2" and utilize "Read Status Register 2(0x35)" command to get the QE bit status. To suppo

[PATCH v2 1/5] hw/net:ftgmac100: update memory region size to 0x200

2024-07-03 Thread Jamin Lin via
According to the datasheet of ASPEED SOCs, one MAC controller owns 128KB of register space for AST2500. However, one MAC controller only owns 64KB of register space for AST2600 and AST2700. It set the memory region size 128KB and it occupied another controllers Address Spaces. Currently, the ftg

[PATCH v2 0/5] support AST2700 network

2024-07-03 Thread Jamin Lin via
change from v1: - ftgmac100 - fix coding style - support 64 bits dma dram address for AST2700 change from v2: - ftgmac100: update memory region size to 0x200. - ftgmac100: introduce a new class(ftgmac100_high), class attribute and memop handlers, for FTGMAC100_*_HIGH regs read/write. - aspee

[PATCH v2 5/5] test/avocado/machine_aspeed.py: update to test network for AST2700

2024-07-03 Thread Jamin Lin via
Update a test case to test network connection via ssh and changes to test Aspeed OpenBMC SDK v09.02 for AST2700. ASPEED fixed TX mask issue from linux/drivers/ftgmac100.c. It is required to use ASPEED SDK image since v09.02 for AST2700 QEMU network testing. A test image is downloaded from the ASP

[PATCH v3 3/8] hw/net:ftgmac100: introduce TX and RX ring base address high registers to support 64 bits

2024-07-04 Thread Jamin Lin via
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35) And the base address of dram is "0x4 " which is 64bits address. It have "Normal Priority Transmit Ring Base Address Register High(0x17C)", "High Priority Transmit Ring Base Address Register High(0x184)" and "Receive Ring Base Addr

[PATCH v3 0/8] support AST2700 network

2024-07-04 Thread Jamin Lin via
change from v1: - ftgmac100 - fix coding style - support 64 bits dma dram address for AST2700 change from v2: - ftgmac100: update memory region size to 0x200. - ftgmac100: introduce a new class(ftgmac100_high), class attribute and memop handlers, for FTGMAC100_*_HIGH regs read/write. - aspee

[PATCH v3 2/8] hw/net:ftgmac100: update ring base address to 64 bits

2024-07-04 Thread Jamin Lin via
Update TX and RX ring base address data type to uint64_t for 64 bits dram address DMA support. Both "Normal Priority Transmit Ring Base Address Register(0x20)" and "Receive Ring Base Address Register (0x24)" are used for saving the low part physical address of descriptor manager. Therefore, chang

[PATCH v3 1/8] hw/net:ftgmac100: update memory region size to 64KB

2024-07-04 Thread Jamin Lin via
According to the datasheet of ASPEED SOCs, one MAC controller owns 128KB of register space for AST2500. However, one MAC controller only owns 64KB of register space for AST2600 and AST2700. It set the memory region size 128KB and it occupied another controllers Address Spaces. Update one MAC contr

[PATCH v3 7/8] machine_aspeed.py: update to test ASPEED OpenBMC SDK v09.02 for AST2700

2024-07-04 Thread Jamin Lin via
Update test case to test ASPEED OpenBMC SDK v09.02 for AST2700. ASPEED fixed TX mask issue from linux/drivers/ftgmac100.c. It is required to use ASPEED OpenBMC SDK since v09.02 for AST2700 QEMU network testing. A test image is downloaded from the ASPEED Forked OpenBMC GitHub release repository :

[PATCH v3 4/8] hw/net:ftgmac100: update TX and RX packet buffers address to 64 bits

2024-07-04 Thread Jamin Lin via
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35) And the base address of dram is "0x4 " which is 64bits address. It have "TXDES 2" and "RXDES 2" to save the high part physical address of packet buffer. Ex: TX packet buffer address [34:0] The "TXDES 2" bits [18:16] which correspo

[PATCH v3 6/8] hw/block: m25p80: support quad mode for w25q01jvq

2024-07-04 Thread Jamin Lin via
According to the w25q01jv datasheet at page 16, it is required to set QE bit in "Status Register 2". Besides, users are able to utilize "Write Status Register 1(0x01)" command to set QE bit in "Status Register 2" and utilize "Read Status Register 2(0x35)" command to get the QE bit status. To suppo

[PATCH v3 8/8] machine_aspeed.py: update to test network for AST2700

2024-07-04 Thread Jamin Lin via
Update test case to test network connection via SSH. Test command: ``` cd build pyvenv/bin/avocado run ../qemu/tests/avocado/machine_aspeed.py:AST2x00MachineSDK.test_aarch64_ast2700_evb_sdk_v09_02 ``` Signed-off-by: Jamin Lin --- tests/avocado/machine_aspeed.py | 6 -- 1 file changed, 4 in

[PATCH v3 5/8] aspeed/soc: set dma64 property for AST2700 ftgmac100

2024-07-04 Thread Jamin Lin via
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35) And the base address of dram is "0x4 " which is 64bits address. Set dma64 property for ftgmac100 model to support 64bits dram address DMA. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast27x0.c | 3 +++ 1 file changed, 3 insertio

[PATCH v1 08/16] test/qtest/aspeed_smc-test: Move testcases to test_palmetto_bmc function

2024-10-17 Thread Jamin Lin via
So far, the test cases are used for testing SMC model with AST2400 BMC. However, AST2400 is end off live and ASPEED is no longer support this SOC. To test SMC model for AST2500, AST2600 and AST1030, move the test cases from main to test_palmetto_bmc function. Signed-off-by: Jamin Lin --- tests/q

[PATCH v1 06/16] hw/arm/aspeed: Correct fmc_model w25q80bl for ast1030-a1 EVB

2024-10-17 Thread Jamin Lin via
Currently, the default fmc_model was "sst25vf032b" whose size was 4MB for ast1030-a1 EVB. However, according to the schematic of ast1030-a1 EVB, ASPEED shipped default flash of fmc_cs0 and fmc_cs1 were "w25q80bl" and "w25q256", respectively. The size of w25q80bl is 1MB and the size of w25q256 is 32

[PATCH v1 12/16] test/qtest/aspeed_smc-test: Support to test AST2500

2024-10-17 Thread Jamin Lin via
Add test_ast2500_evb function and reused testcases for AST2500 testing. The spi base address, flash base address and ce index of fmc_cs0 are 0x1E62, 0x2000 and 0, respectively. The default flash model of fmc_cs0 is "mx25l25635e" whose size is 32MB, so set jedec_id 0xc22019. Signed-off-by:

[PATCH v1 09/16] test/qtest/aspeed_smc-test: Introduce a new TestData to test different BMC SOCs

2024-10-17 Thread Jamin Lin via
Currently, these test cases are only used for testing fmc_cs0 for AST2400. To test others BMC SOCs, introduces a new TestData structure. Users can set the spi base address, flash base address, jedesc id and so on for different BMC SOCs and flash model testing. Introduce new helper functions to mak

[PATCH v1 14/16] test/qtest/aspeed_smc-test: Support to test AST1030

2024-10-17 Thread Jamin Lin via
Add test_ast1030_evb function and reused testcases for AST1030 testing. The base address, flash base address and ce index of fmc_cs0 are 0x7E62, 0x8000 and 0, respectively. The default flash model of fmc_cs0 is "w25q80bl" whose size is 1MB, so set jedec_id 0xef4014. Signed-off-by: Jamin Li

[PATCH v1 10/16] test/qtest/aspeed_smc-test: Support to test all CE pins

2024-10-17 Thread Jamin Lin via
Currently, these test cases only support to test CE0. To test all CE pins, introduces new ce and node members in TestData structure. The ce member is used for saving the ce index and node member is used for saving the node path, respectively. Signed-off-by: Jamin Lin --- tests/qtest/aspeed_smc-t

[PATCH v1 05/16] hw/arm/aspeed: Correct spi_model w25q256 for ast1030-a1 EVB.

2024-10-17 Thread Jamin Lin via
Currently, the default spi_model was "sst25vf032b" whose size was 4MB for ast1030-a1 EVB. However, according to the schematic of ast1030-a1 EVB, ASPEED shipped default flash of spi1 and spi2 were w25q256 whose size was 32MB. Correct spi_model default flash to w25q256 for ast1030-a1 EVB. Signed-of

[PATCH v1 13/16] test/qtest/aspeed_smc-test: Support to test AST2600

2024-10-17 Thread Jamin Lin via
Add test_ast2600_evb function and reused testcases for AST2600 testing. The spi base address, flash base address and ce index of fmc_cs0 are 0x1E62, 0x2000 and 0, respectively. The default flash model of fmc_cs0 is "mx66u51235f" whose size is 64MB, so set jedec_id 0xc2253a. Signed-off-by:

[PATCH v1 01/16] aspeed/smc: Fix write incorrect data into flash in user mode

2024-10-17 Thread Jamin Lin via
According to the design of ASPEED SPI controllers user mode, users write the data to flash, the SPI drivers set the Control Register(0x10) bit 0 and 1 enter user mode. Then, SPI drivers send flash commands for writing data. Finally, SPI drivers set the Control Register (0x10) bit 2 to stop active c

[PATCH v1 03/16] hw/block:m25p80: Support write status register 2 command (0x31) for w25q01jvq

2024-10-17 Thread Jamin Lin via
According to the w25q01jv datasheet at page 16, it is required to set QE bit in "Status Register 2" to enable quad mode. Currently, m25p80 support users utilize "Write Status Register 1(0x01)" command to set QE bit in "Status Register 2" and utilize "Read Status Register 2(0x35)" command to get th

[PATCH v1 02/16] hw/block:m25p80: Fix coding style

2024-10-17 Thread Jamin Lin via
Fix coding style issues from checkpatch.pl Signed-off-by: Jamin Lin --- hw/block/m25p80.c | 22 ++ 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index f7123f9e68..3f55b8f385 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m

[PATCH v1 11/16] test/qtest/aspeed_smc-test: Support to test all flash models

2024-10-17 Thread Jamin Lin via
Currently, these test cases used the hardcode offset 0x140 (0x14000 * 256) which was beyond the 16MB flash size for flash page read/write command testing. However, the default fmc flash model of ast1030-a1 EVB is "w25q80bl" whose size is 1MB. To test all flash models, introduces a new page_addr

[PATCH v1 04/16] hw/block/m25p80: Add SFDP table for w25q80bl flash

2024-10-17 Thread Jamin Lin via
Add the SFDP table for the Windbond w25q80bl flash. Signed-off-by: Jamin Lin --- hw/block/m25p80.c | 3 ++- hw/block/m25p80_sfdp.c | 36 hw/block/m25p80_sfdp.h | 2 +- 3 files changed, 39 insertions(+), 2 deletions(-) diff --git a/hw/block/m25p80.c b/

[PATCH v1 00/16] Fix write incorrect data into flash in user mode

2024-10-17 Thread Jamin Lin via
change from v1: 1. Fix write incorrect data into flash in user mode. 2. Refactor aspeed smc qtest testcases to support AST2600, AST2500 and AST1030. 3. Add ast2700 smc qtest testcase to support AST2700. QEMU version: https://github.com/qemu/qemu/commit/95a16ee753d6da651fce8df876333bf7fcf134d9

[PATCH v1 07/16] test/qtest/aspeed_smc-test: Fix coding style

2024-10-17 Thread Jamin Lin via
Fix coding style issues from checkpatch.pl Signed-off-by: Jamin Lin --- tests/qtest/aspeed_smc-test.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c index c713a3700b..4673371d95 100644 --- a/tests/qtest/aspe

[PATCH v1 16/16] test/qtest/ast2700-smc-test: Support to test AST2700

2024-10-17 Thread Jamin Lin via
Add test_ast2700_evb function and reused testcases which are from aspeed_smc-test.c for AST2700 testing. The base address, flash base address and ce index of fmc_cs0 are 0x1400, 0x1 and 0, respectively. The default flash model of fmc_cs0 is "w25q01jvq" whose size is 128MB, so set jedec_

[PATCH v1 15/16] test/qtest/aspeed_smc-test: Support write page command with QPI mode

2024-10-17 Thread Jamin Lin via
Add a new testcase for write page command with QPI mode testing. Currently, only run this testcase for AST2500, AST2600 and AST1030. Signed-off-by: Jamin Lin --- tests/qtest/aspeed_smc-test.c | 74 +++ 1 file changed, 74 insertions(+) diff --git a/tests/qtest/asp

[PATCH v2 10/18] test/qtest/aspeed_smc-test: Introduce a new TestData to test different BMC SOCs

2024-10-22 Thread Jamin Lin via
Currently, these test cases are only used for testing fmc_cs0 for AST2400. To test others BMC SOCs, introduces a new TestData structure. Users can set the spi base address, flash base address, jedesc id and so on for different BMC SOCs and flash model testing. Introduce new helper functions to mak

[PATCH v2 14/18] test/qtest/aspeed_smc-test: Support to test AST2600

2024-10-22 Thread Jamin Lin via
Add test_ast2600_evb function and reused testcases for AST2600 testing. The spi base address, flash base address and ce index of fmc_cs0 are 0x1E62, 0x2000 and 0, respectively. The default flash model of fmc_cs0 is "mx66u51235f" whose size is 64MB, so set jedec_id 0xc2253a. Signed-off-by:

[PATCH v2 16/18] test/qtest/aspeed_smc-test: Support write page command with QPI mode

2024-10-22 Thread Jamin Lin via
Add a new testcase for write page command with QPI mode testing. Currently, only run this testcase for AST2500, AST2600 and AST1030. Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater --- tests/qtest/aspeed_smc-test.c | 74 +++ 1 file changed, 74 insertions(+

[PATCH v2 03/18] hw/block:m25p80: Support write status register 2 command (0x31) for w25q01jvq

2024-10-22 Thread Jamin Lin via
According to the w25q01jv datasheet at page 16, it is required to set QE bit in "Status Register 2" to enable quad mode. Currently, m25p80 support users utilize "Write Status Register 1(0x01)" command to set QE bit in "Status Register 2" and utilize "Read Status Register 2(0x35)" command to get th

[PATCH v2 11/18] test/qtest/aspeed_smc-test: Support to test all CE pins

2024-10-22 Thread Jamin Lin via
Currently, these test cases only support to test CE0. To test all CE pins, introduces new ce and node members in TestData structure. The ce member is used for saving the ce index and node member is used for saving the node path, respectively. Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater

[PATCH v2 13/18] test/qtest/aspeed_smc-test: Support to test AST2500

2024-10-22 Thread Jamin Lin via
Add test_ast2500_evb function and reused testcases for AST2500 testing. The spi base address, flash base address and ce index of fmc_cs0 are 0x1E62, 0x2000 and 0, respectively. The default flash model of fmc_cs0 is "mx25l25635e" whose size is 32MB, so set jedec_id 0xc22019. Signed-off-by:

[PATCH v2 15/18] test/qtest/aspeed_smc-test: Support to test AST1030

2024-10-22 Thread Jamin Lin via
Add test_ast1030_evb function and reused testcases for AST1030 testing. The base address, flash base address and ce index of fmc_cs0 are 0x7E62, 0x8000 and 0, respectively. The default flash model of fmc_cs0 is "w25q80bl" whose size is 1MB, so set jedec_id 0xef4014. Signed-off-by: Jamin Li

[PATCH v2 18/18] test/qtest/ast2700-smc-test: Support to test AST2700

2024-10-22 Thread Jamin Lin via
Add test_ast2700_evb function and reused testcases which are from aspeed_smc-test.c for AST2700 testing. The base address, flash base address and ce index of fmc_cs0 are 0x1400, 0x1 and 0, respectively. The default flash model of fmc_cs0 is "w25q01jvq" whose size is 128MB, so set jedec_

[PATCH v2 12/18] test/qtest/aspeed_smc-test: Introducing a "page_addr" data field

2024-10-22 Thread Jamin Lin via
Currently, these test cases used the hardcode offset 0x140 (0x14000 * 256) which was beyond the 16MB flash size for flash page read/write command testing. However, the default fmc flash model of ast1030-a1 EVB is "w25q80bl" whose size is 1MB. To test all flash models, introduces a new page_addr

[PATCH v2 00/18] Fix write incorrect data into flash in user mode

2024-10-22 Thread Jamin Lin via
change from v1: 1. Fix write incorrect data into flash in user mode. 2. Refactor aspeed smc qtest testcases to support AST2600, AST2500 and AST1030. 3. Add ast2700 smc qtest testcase to support AST2700. change from v2: 1. Introduce a new aspeed-smc-utils.c to place common testcases. 2. Fix hard

[PATCH v2 09/18] test/qtest/aspeed_smc-test: Move testcases to test_palmetto_bmc function

2024-10-22 Thread Jamin Lin via
So far, the test cases are used for testing SMC model with AST2400 BMC. However, AST2400 is end off live and ASPEED is no longer support this SOC. To test SMC model for AST2500, AST2600 and AST1030, move the test cases from main to test_palmetto_bmc function. Signed-off-by: Jamin Lin Reviewed-by:

[PATCH v2 07/18] aspeed: Fix hardcode attach flash model of spi controllers

2024-10-22 Thread Jamin Lin via
It only attached flash model of fmc and spi[0] in aspeed_machine_init function. However, AST2500 and AST2600 have one fmc and two spi(spi1 and spi2) controllers; AST2700 have one fmc and 3 spi(spi0, spi1 and spi2) controllers. Besides, it used hardcode to attach flash model of fmc, spi[0] and spi[

[PATCH v2 06/18] hw/arm/aspeed: Correct fmc_model w25q80bl for ast1030-a1 EVB

2024-10-22 Thread Jamin Lin via
Currently, the default fmc_model was "sst25vf032b" whose size was 4MB for ast1030-a1 EVB. However, according to the schematic of ast1030-a1 EVB, ASPEED shipped default flash of fmc_cs0 and fmc_cs1 were "w25q80bl" and "w25q256", respectively. The size of w25q80bl is 1MB and the size of w25q256 is 32

[PATCH v2 01/18] aspeed/smc: Fix write incorrect data into flash in user mode

2024-10-22 Thread Jamin Lin via
According to the design of ASPEED SPI controllers user mode, users write the data to flash, the SPI drivers set the Control Register(0x10) bit 0 and 1 enter user mode. Then, SPI drivers send flash commands for writing data. Finally, SPI drivers set the Control Register (0x10) bit 2 to stop active c

[PATCH v2 17/18] test/qtest: Introduce a new aspeed-smc-utils.c to place common testcases

2024-10-22 Thread Jamin Lin via
The testcases for ASPEED SMC model were placed in aspeed_smc-test.c. However, this test file only supports for ARM32. To support all ASPEED SOCs such as AST2700 whose CPU architecture is aarch64, introduces a new aspeed-smc-utils source file and move all common APIs and testcases from aspeed_smc-te

[PATCH v2 02/18] hw/block:m25p80: Fix coding style

2024-10-22 Thread Jamin Lin via
Fix coding style issues from checkpatch.pl Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater --- hw/block/m25p80.c | 22 ++ 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index f7123f9e68..3f55b8f385 100644 --- a/hw/

[PATCH v2 08/18] test/qtest/aspeed_smc-test: Fix coding style

2024-10-22 Thread Jamin Lin via
Fix coding style issues from checkpatch.pl Signed-off-by: Jamin Lin Reviewed-by: Thomas Huth Reviewed-by: Cédric Le Goater --- tests/qtest/aspeed_smc-test.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c i

[PATCH v2 05/18] hw/arm/aspeed: Correct spi_model w25q256 for ast1030-a1 EVB.

2024-10-22 Thread Jamin Lin via
Currently, the default spi_model was "sst25vf032b" whose size was 4MB for ast1030-a1 EVB. However, according to the schematic of ast1030-a1 EVB, ASPEED shipped default flash of spi1 and spi2 were w25q256 whose size was 32MB. Correct spi_model default flash to w25q256 for ast1030-a1 EVB. Signed-of

[PATCH v2 04/18] hw/block/m25p80: Add SFDP table for w25q80bl flash

2024-10-22 Thread Jamin Lin via
Add the SFDP table for the Windbond w25q80bl flash. Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater --- hw/block/m25p80.c | 3 ++- hw/block/m25p80_sfdp.c | 36 hw/block/m25p80_sfdp.h | 2 +- 3 files changed, 39 insertions(+), 2 deletions(-) di

[PATCH v1 0/8] Support RTC for AST2700

2024-10-29 Thread Jamin Lin via
change from v1: 1. Support RTC for AST2700. 2. Support SDHCI write protected pin inverted for AST2500 and AST2600. 3. Introduce Capabilities Register 2 for SD slot 0 and 1. 4. Support create flash devices via command line for AST1030. Jamin Lin (8): aspeed/soc: Support RTC for AST2700 hw/timer

[PATCH v1 5/8] hw/sd/sdhci: Introduce a new Write Protected pin inverted property

2024-10-29 Thread Jamin Lin via
The Write Protect pin of SDHCI model is default active low to match the SDHCI spec. So, write enable the bit 19 should be 1 and write protected the bit 19 should be 0 at the Present State Register (0x24). However, some board are design Write Protected pin active high. In other words, write enable t

[PATCH v1 7/8] hw/arm/aspeed: Invert sdhci write protected pin for AST2600 and AST2500 EVBs

2024-10-29 Thread Jamin Lin via
The Write Protect pin of SDHCI model is default active low to match the SDHCI spec. So, write enable the bit 19 should be 1 and write protected the bit 19 should be 0 at the Present State Register (0x24). According to the design of AST2500 and AST2600 EVBs, the Write Protected pin is active high b

[PATCH v1 4/8] hw/sd/sdhci: Fix coding style

2024-10-29 Thread Jamin Lin via
Fix coding style issues from checkpatch.pl Signed-off-by: Jamin Lin --- hw/sd/sdhci.c | 64 +-- 1 file changed, 42 insertions(+), 22 deletions(-) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index ed01499391..db7d547156 100644 --- a/hw/sd/sdhci.c ++

[PATCH v1 3/8] hw/timer/aspeed: Fix interrupt status does not be cleared for AST2600

2024-10-29 Thread Jamin Lin via
According to the datasheet of AST2600 description, interrupt status set by HW and clear to "0" by software writing "1" on the specific bit. Therefore, if firmware set the specific bit "1" in the interrupt status register(0x34), the specific bit of "s->irq_sts" should be cleared 0. Signed-off-by:

[PATCH v1 1/8] aspeed/soc: Support RTC for AST2700

2024-10-29 Thread Jamin Lin via
The RTC controller between AST2600 and AST2700 are identical. Add RTC model for AST2700 RTC support. The RTC controller registers base address is start at 0x12C0_F000 and its alarm interrupt is connected to GICINT13. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast27x0.c | 11 +++ 1 file c

[PATCH v1 2/8] hw/timer/aspeed: Fix coding style

2024-10-29 Thread Jamin Lin via
Fix coding style issues from checkpatch.pl Signed-off-by: Jamin Lin --- hw/timer/aspeed_timer.c | 13 - 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c index b1f860ecfb..5af268ea9e 100644 --- a/hw/timer/aspeed_timer.c ++

[PATCH v1 6/8] hw/sd/aspeed_sdhci: Introduce Capabilities Register 2 for SD slot 0 and 1

2024-10-29 Thread Jamin Lin via
The size of SDHCI capabilities register is 64bits, so introduces new Capabilities Register 2 for SD slot 0 (0x144) and SD slot1 (0x244). Signed-off-by: Jamin Lin --- hw/sd/aspeed_sdhci.c | 40 +--- 1 file changed, 29 insertions(+), 11 deletions(-) diff --git

[PATCH v1 8/8] aspeed: Support create flash devices via command line for AST1030

2024-10-29 Thread Jamin Lin via
Add a "if-statement" in aspeed_minibmc_machine_init function. If users add "-nodefaults" in command line, the flash devices should be created by users setting. Otherwise, the flash devices are created at machine init. Signed-off-by: Jamin Lin --- hw/arm/aspeed.c | 22 -- 1 fi

[PATCH v2 0/3] Introduce a new Write Protected pin inverted property

2024-11-03 Thread Jamin Lin via
change from v1: 1. Support RTC for AST2700. 2. Support SDHCI write protected pin inverted for AST2500 and AST2600. 3. Introduce Capabilities Register 2 for SD slot 0 and 1. 4. Support create flash devices via command line for AST1030. change from v2: replace wp-invert with wp-inverted and fix revi

[PATCH v2 1/3] hw/sd/sdhci: Fix coding style

2024-11-03 Thread Jamin Lin via
Fix coding style issues from checkpatch.pl Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater --- hw/sd/sdhci.c | 64 +-- 1 file changed, 42 insertions(+), 22 deletions(-) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index ed01499391..db7d54715

[PATCH v2 2/3] hw/sd/sdhci: Introduce a new Write Protected pin inverted property

2024-11-03 Thread Jamin Lin via
The Write Protect pin of SDHCI model is default active low to match the SDHCI spec. So, write enable the bit 19 should be 1 and write protected the bit 19 should be 0 at the Present State Register (0x24). However, some boards are design Write Protected pin active high. In other words, write enable

[PATCH v2 3/3] hw/arm/aspeed: Invert sdhci write protected pin for AST2600 and AST2500 EVBs

2024-11-03 Thread Jamin Lin via
The Write Protect pin of SDHCI model is default active low to match the SDHCI spec. So, write enable the bit 19 should be 1 and write protected the bit 19 should be 0 at the Present State Register (0x24). According to the design of AST2500 and AST2600 EVBs, the Write Protected pin is active high b

[PATCH v3 0/3] Introduce a new Write Protected pin inverted property

2024-11-14 Thread Jamin Lin via
change from v1: 1. Support RTC for AST2700. 2. Support SDHCI write protected pin inverted for AST2500 and AST2600. 3. Introduce Capabilities Register 2 for SD slot 0 and 1. 4. Support create flash devices via command line for AST1030. change from v2: replace wp-invert with wp-inverted and fix revi

[PATCH v3 1/3] hw/sd/sdhci: Fix coding style

2024-11-14 Thread Jamin Lin via
Fix coding style issues from checkpatch.pl Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater --- hw/sd/sdhci.c | 64 +-- 1 file changed, 42 insertions(+), 22 deletions(-) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index dbe5c2340c..37875c02c

[PATCH v3 2/3] hw/sd/sdhci: Introduce a new Write Protected pin inverted property

2024-11-14 Thread Jamin Lin via
The Write Protect pin of SDHCI model is default active low to match the SDHCI spec. So, write enable the bit 19 should be 1 and write protected the bit 19 should be 0 at the Present State Register (0x24). However, some boards are design Write Protected pin active high. In other words, write enable

[PATCH v3 3/3] hw/arm/aspeed: Invert sdhci write protected pin for AST2600 EVB

2024-11-14 Thread Jamin Lin via
The Write Protect pin of SDHCI model is default active low to match the SDHCI spec. So, write enable the bit 19 should be 1 and write protected the bit 19 should be 0 at the Present State Register (0x24). According to the design of AST2600 EVB, the Write Protected pin is active high by default. To

[RFC.PATCH v1 0/2] sd:sdhci Fix data transfer did not complete

2024-12-11 Thread Jamin Lin via
v1: 1. Fix boundary_count overflow 2. Fix data transfer did not complete if data size is bigger then SDMA Buffer Boundary Jamin Lin (2): RFC:sd:sdhci: Fix boundary_count overflow in sdhci_sdma_transfer_multi_blocks RFC:sd:sdhci: Fix data transfer did not complete if data size is bigge

[RFC.PATCH v1 2/2] sd:sdhci: Fix data transfer did not complete if data size is bigger then SDMA Buffer Boundary

2024-12-11 Thread Jamin Lin via
According to the design of sdhci_sdma_transfer_multi_blocks, if the "s->blkcnt * 512" was bigger than the SDMA Buffer boundary, it breaked the while loop of data transfer and set SDHC_NISEN_DMA in the normal interreupt status to notify the firmware that this SDMA boundary buffer Transfer Complete a

[RFC.PATCH v1 1/2] sd:sdhci: Fix boundary_count overflow in sdhci_sdma_transfer_multi_blocks

2024-12-11 Thread Jamin Lin via
How to reproduce it: 1. The value of "s->blksie" was 0x7200. The bits[14:12] was "111", so the buffer boundary was 0x8.(512Kbytes). This SDMA buffer boundary the same as u-boot default value. The bit[11:0] is "0010", so the block size is 0x200.(512bytes) 2. The SDMA address was

[PATCH v2 2/2] hw/sd/sdhci: Fix data transfer did not complete if data size is bigger than SDMA Buffer Boundary

2024-12-12 Thread Jamin Lin via
According to the design of sdhci_sdma_transfer_multi_blocks, if the "s->blkcnt * 512" was bigger than the SDMA Buffer boundary, it break the while loop of data transfer and set SDHC_NISEN_DMA in the normal interrupt status to notify the firmware that this SDMA boundary buffer Transfer Complete and

[PATCH v2 0/2] sd:sdhci Fix data transfer did not complete

2024-12-12 Thread Jamin Lin via
v1: 1. Fix boundary_count overflow 2. Fix data transfer did not complete if data size is bigger then SDMA Buffer Boundary v2: 1. fix typo 2. update to none RFC patch 3. check the most upper byte of SDMA System Address Register (0x00) is written, then restarts SDMA data transfer. Jamin Lin (2)

[PATCH v2 1/2] hw/sd/sdhci: Fix boundary_count overflow in sdhci_sdma_transfer_multi_blocks

2024-12-12 Thread Jamin Lin via
How to reproduce it: 1. The value of "s->blksie" was 0x7200. The bits[14:12] was "111", so the buffer boundary was 0x8.(512Kbytes). This SDMA buffer boundary was the same as u-boot default value. The bit[11:0] was "0010", so the block size was 0x200.(512bytes) 2. The SDMA addre