DEFINE_PROP_ENDIAN_NODEFAULT() macro uses ENDIAN_MODE_UNSPECIFIED
which is defined in "qapi/qapi-types-common.h".
Fixes: 4ec96630f93 ("hw/qdev-properties-system: Introduce EndianMode QAPI enum")
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/qdev-properties-system.h | 1 +
1 file changed,
All instances of TYPE_IMX_USDHC set vendor=SDHCI_VENDOR_IMX.
No need to special-case it.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/sdhci-internal.h | 1 -
include/hw/sd/sdhci.h | 4
hw/arm/fsl-imx25.c | 2 --
hw/arm/fsl-imx6.c | 2 --
hw/arm/fsl-imx6ul.c| 2 --
hw/a
Since v3:
- Fix "hw/qdev-properties-system.h" (first patch)
- Convert to EndianMode (patch #10)
Rainy saturday, time for some hobbyist contributions :)
In this series we try to address the issue Zoltan reported
and try to fix in [*], but using a more generic approach.
The SDHCI code ends up bette
Per the MPC8569E reference manual, its SDHC I/O range is 4KiB
wide, mapped in big endian order, and it only accepts 32-bit
aligned access. Set the default register reset values.
Reported-by: BALATON Zoltan
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/sd/sdhci.h | 2 ++
hw/sd/sdhci.c
Note, sdhci_mmio_le_ops[] was missing .impl.access_size = 4.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/sdhci.c | 46 --
1 file changed, 20 insertions(+), 26 deletions(-)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index a2e7162e289..23af3958a1d 1
On Sat, 8 Mar 2025, Philippe Mathieu-Daudé wrote:
TYPE_SYSBUS_SDHCI is a bit odd because it uses an union
to work with both SysBus / PCI parent. As this is not a
normal use, introduce SDHCIClass in its own commit.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/sd/sdhci.h | 9 +
hw/
Be ready to have SDHC implementations to cover
a wider I/O address range.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/sd/sdhci.h | 1 +
hw/sd/sdhci.c | 10 --
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
in
Add MemoryRegionOps as a class property. For now it is only
used by TYPE_IMX_USDHC.
Otherwise the default remains in little endian.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/sd/sdhci.h | 1 +
hw/sd/sdhci.c | 22 --
2 files changed, 9 insertions(+), 14 dele
EndianMode enum is preferred over DEVICE_BIG/LITTLE_ENDIAN
values because it is a QAPI type.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/sdhci-internal.h | 3 ++-
include/hw/sd/sdhci.h | 3 ++-
hw/ppc/e500.c | 2 +-
hw/sd/sdhci-pci.c | 2 +-
hw/sd/sdhci.c | 7 ++-
All TYPE_IMX_USDHC instances use the quirk:
move it to the class layer.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/sd/sdhci.h | 3 ++-
hw/sd/sdhci.c | 15 +--
2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhc
TYPE_SYSBUS_SDHCI is a bit odd because it uses an union
to work with both SysBus / PCI parent. As this is not a
normal use, introduce SDHCIClass in its own commit.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/sd/sdhci.h | 9 +
hw/sd/sdhci.c | 1 +
2 files changed, 10 inse
On 6/3/25 19:23, BALATON Zoltan wrote:
On Mon, 3 Mar 2025, BALATON Zoltan wrote:
On Mon, 3 Mar 2025, Philippe Mathieu-Daudé wrote:
Hi Zoltan,
On 10/2/25 17:03, BALATON Zoltan wrote:
The interrupt enable registers are not reset to 0 on Freescale eSDHC
but some bits are enabled on reset. At lea
Rainy saturday, time for some hobbyist contributions :)
In this series we try to address the issue Zoltan reported
and try to fix in [*], but using a more generic approach.
The SDHCI code ends up better consolidated and ready to
scale for more vendor implementations.
I expect (with few QOM knowle
TYPE_SYSBUS_SDHCI is a bit odd because it uses an union
to work with both SysBus / PCI parent. As this is not a
normal use, introduce SDHCIClass in its own commit.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/sd/sdhci.h | 9 +
hw/sd/sdhci.c | 1 +
2 files changed, 10 inse
All instances of TYPE_IMX_USDHC set vendor=SDHCI_VENDOR_IMX.
No need to special-case it.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/sdhci-internal.h | 1 -
include/hw/sd/sdhci.h | 4
hw/arm/fsl-imx25.c | 2 --
hw/arm/fsl-imx6.c | 2 --
hw/arm/fsl-imx6ul.c| 2 --
hw/a
All TYPE_IMX_USDHC instances use the quirk:
move it to the class layer.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/sd/sdhci.h | 3 ++-
hw/sd/sdhci.c | 15 +--
2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhc
Be ready to have SDHC implementations to cover
a wider I/O address range.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/sd/sdhci.h | 1 +
hw/sd/sdhci.c | 9 +++--
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
index
Note, sdhci_mmio_le_ops[] was missing .impl.access_size = 4.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/sdhci.c | 41 -
1 file changed, 16 insertions(+), 25 deletions(-)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index d115e88c4b9..15e6976220f 100644
Capability register is read-only.
Since we allow instances to clear/set extra bits, log when
read-only bits normally set by hardware are cleared at
board level.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/sd/sdhci.h | 5 +
hw/sd/sdhci.c | 6 ++
2 files changed, 11 inser
While little endianness is the default, ome controllers
might be only implemented in big endianness.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/sdhci.c | 18 --
1 file changed, 4 insertions(+), 14 deletions(-)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index d87a7bb45a4..d1
As Zoltan reported, some U-Boot versions seem to expect
correctly initialized registers before expecting interrupts.
Now than we have a proper Freescale eSDHC implementation,
use it.
Reported-by: BALATON Zoltan
Signed-off-by: Philippe Mathieu-Daudé
---
hw/ppc/e500.c | 10 +-
1 file cha
While little endianness is the default, ome controllers
might be only implemented in big endianness.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/sdhci.c | 18 --
1 file changed, 4 insertions(+), 14 deletions(-)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index ae485f90dfe..a2
This is the default, but better be safe than sorry.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/sdhci-pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/sd/sdhci-pci.c b/hw/sd/sdhci-pci.c
index 5268c0dee50..5f82178a76f 100644
--- a/hw/sd/sdhci-pci.c
+++ b/hw/sd/sdhci-pci.c
@@ -32,6
As Zoltan reported, some U-Boot versions seem to expect
correctly initialized registers before expecting interrupts.
Now than we have a proper Freescale eSDHC implementation,
use it.
Reported-by: BALATON Zoltan
Signed-off-by: Philippe Mathieu-Daudé
---
hw/ppc/e500.c | 10 +-
1 file cha
For the registers which are not zeroed at reset, allow the
different implementations to set particular reset values.
Remove the misleading values commented in sdhci-internal.h.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/sdhci-internal.h | 24
include/hw/sd/sdhci.h
Capability register is read-only.
Since we allow instances to clear/set extra bits, log when
read-only bits normally set by hardware are cleared at
board level.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/sd/sdhci.h | 5 +
hw/sd/sdhci.c | 6 ++
2 files changed, 11 inser
On Sun, 9 Mar 2025, Philippe Mathieu-Daudé wrote:
On 8/3/25 23:34, BALATON Zoltan wrote:
On Sat, 8 Mar 2025, Philippe Mathieu-Daudé wrote:
TYPE_SYSBUS_SDHCI is a bit odd because it uses an union
to work with both SysBus / PCI parent. As this is not a
normal use, introduce SDHCIClass in its own
On Sat, 8 Mar 2025, Philippe Mathieu-Daudé wrote:
While little endianness is the default, ome controllers
Typo, ome -> some.
Regards,
BALATON Zoltan
might be only implemented in big endianness.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/sdhci.c | 18 --
1 file changed,
On 8/3/25 23:34, BALATON Zoltan wrote:
On Sat, 8 Mar 2025, Philippe Mathieu-Daudé wrote:
TYPE_SYSBUS_SDHCI is a bit odd because it uses an union
to work with both SysBus / PCI parent. As this is not a
normal use, introduce SDHCIClass in its own commit.
Signed-off-by: Philippe Mathieu-Daudé
---
For the registers which are not zeroed at reset, allow the
different implementations to set particular reset values.
Remove the misleading values commented in sdhci-internal.h.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/sdhci-internal.h | 24
include/hw/sd/sdhci.h
Per the MPC8569E reference manual, its SDHC I/O range is 4KiB
wide, mapped in big endian order, and it only accepts 32-bit
aligned access. Set the default register reset values.
Reported-by: BALATON Zoltan
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/sd/sdhci.h | 2 ++
hw/sd/sdhci.c
This is the default, but better be safe than sorry.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/sdhci-pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/sd/sdhci-pci.c b/hw/sd/sdhci-pci.c
index 5268c0dee50..5f82178a76f 100644
--- a/hw/sd/sdhci-pci.c
+++ b/hw/sd/sdhci-pci.c
@@ -32,6
Add MemoryRegionOps as a class property. For now it is only
used by TYPE_IMX_USDHC.
Otherwise the default remains in little endian.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/sd/sdhci.h | 1 +
hw/sd/sdhci.c | 22 --
2 files changed, 9 insertions(+), 14 dele
From: Zhu Yangyang
In the disable branch of qmp_block_set_io_throttle(), we call
bdrv_drained_begin().
We know that bdrv_drained_begin() is a blocking interface used to wait for all
submitted
I/O operations to complete, i.e., to wait until bs->in_flight becomes zero.
Theoretically, once we sto
From: Zhu Yangyang
bdrv_drained_begin() is blocked for a long time when network storage is used
and the network link has just failed.
Therefore, the timeout period is set here.
Signed-off-by: Zhu Yangyang
---
block/block-backend.c | 14 +-
block/qapi-system.c
From: Zhu Yangyang
The bdrv_drained_begin() function is a blocking function. In scenarios where
network storage
is used and network links fail, it may block for a long time.
Therefore, we add a timeout parameter to control the duration of the block.
Since bdrv_drained_begin() has been widely ad
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