Re: [PATCH v3 3/3] hw/arm/aspeed: Invert sdhci write protected pin for AST2600 EVB

2025-01-07 Thread Philippe Mathieu-Daudé
On 14/11/24 10:48, Jamin Lin wrote: The Write Protect pin of SDHCI model is default active low to match the SDHCI spec. So, write enable the bit 19 should be 1 and write protected the bit 19 should be 0 at the Present State Register (0x24). According to the design of AST2600 EVB, the Write Prote

[PATCH v3 3/3] hw/arm/aspeed: Invert sdhci write protected pin for AST2600 EVB

2024-11-14 Thread Jamin Lin via
The Write Protect pin of SDHCI model is default active low to match the SDHCI spec. So, write enable the bit 19 should be 1 and write protected the bit 19 should be 0 at the Present State Register (0x24). According to the design of AST2600 EVB, the Write Protected pin is active high by default. To