Michael wrote:
> Practical examples are great, I'd seen that you'd introduced conversion to
> verilog some time back, but it wasn't clear how much was synthesisable.
I'll try to clarify. Hardware synthesis is a rather "closed" technology,
with several competing, expensive tools and relatively few
Jan Decaluwe wrote:
> Michael wrote:
...
>>* http://article.gmane.org/gmane.comp.python.myhdl/19/match=mu0
>>
>> One question I've got, mainly because it strikes me as very intriguing is
>> do you know if the MU0 processor as described is synthesisable or have a
>> feeling as to how much work
Randall Parker wrote:
> Jan,
>
> What do you see as the main advantage for using MyHDL rather than VHDL
> for coding up a chip design?
The fact that MyHDL is technically just another Python application.
So it makes all typical Python advantages available to hardware
designers. No need to discuss
Jan,
What do you see as the main advantage for using MyHDL rather than VHDL
for coding up a chip design?
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Michael wrote:
> Jan Decaluwe wrote:
>
>
>>I'm pleased to announce the release of MyHDL 0.5.
>>
>>MyHDL is an open-source package for using Python as a hardware
>>description and verification language. Moreover, it can convert
>>a design to Verilog. Thus, MyHDL provides a complete path
>>from Pyt
Jan Decaluwe wrote:
> I'm pleased to announce the release of MyHDL 0.5.
>
> MyHDL is an open-source package for using Python as a hardware
> description and verification language. Moreover, it can convert
> a design to Verilog. Thus, MyHDL provides a complete path
> from Python to silicon.
Jan,
