Michael wrote:
> Practical examples are great, I'd seen that you'd introduced conversion to
> verilog some time back, but it wasn't clear how much was synthesisable.
I'll try to clarify. Hardware synthesis is a rather "closed" technology,
with several competing, expensive tools and relatively few
Jan Decaluwe wrote:
> Michael wrote:
...
>>* http://article.gmane.org/gmane.comp.python.myhdl/19/match=mu0
>>
>> One question I've got, mainly because it strikes me as very intriguing is
>> do you know if the MU0 processor as described is synthesisable or have a
>> feeling as to how much work
Michael wrote:
> Jan Decaluwe wrote:
>
>
>>I'm pleased to announce the release of MyHDL 0.5.
>>
>>MyHDL is an open-source package for using Python as a hardware
>>description and verification language. Moreover, it can convert
>>a design to Verilog. Thus, MyHDL provides a complete path
>>from Pyt
Jan Decaluwe wrote:
> I'm pleased to announce the release of MyHDL 0.5.
>
> MyHDL is an open-source package for using Python as a hardware
> description and verification language. Moreover, it can convert
> a design to Verilog. Thus, MyHDL provides a complete path
> from Python to silicon.
Jan,
