Oleksandr Pavlyk added the comment:
So where getauxval(AT_MINSIGSTKSZ) < SIGSTKSZ the merged changes actually
resulted in decrease of the allocated signal deliver stack.
On Sapphire Rapids due to tile registers size we have getauxval(AT_MINSIGSTKSZ)
> SIGSTKSZ.
This is why the i
Change by Oleksandr Pavlyk :
--
keywords: +patch
pull_requests: +29893
stage: -> patch review
pull_request: https://github.com/python/cpython/pull/31789
___
Python tracker
<https://bugs.python.org/issu
New submission from Oleksandr Pavlyk :
The following snippet illustrates request by an extension to use AMX registers:
```
// no increase sigaltstack size fix will not wark till we fix python
void enable_amx_no_fix()
{
unsigned long bitmask;
long rc;
rc = syscall(SYS_arch_prctl
