- Original Message -
From: "Bruce Momjian" <[EMAIL PROTECTED]>
To: <[EMAIL PROTECTED]>
Cc: "Tom Lane" <[EMAIL PROTECTED]>; <[EMAIL PROTECTED]>
>
> We would have to understand how the SGI code is better than our existing
> code on SMP machines.
>
I've been searching for data from SGI's Or
"Luis Alberto Amigo Navarro" <[EMAIL PROTECTED]> writes:
> if you want postgres to run fine on this machines I think (it's not tested
> yet) it would be neccesary to implement native shared arenas instead of IPC
> shared memory in order to let IRIX make a fine load-balance.
In CVS tip, the direct
> We would have to understand how the SGI code is better than our existing
> code on SMP machines.
there is a big problem with postgres on SGI NUMA architectures, on UMA
systems postgres works fine, but NUMA Origins need a native shared memory
management. It scales fine over old challenges, but s
Robert E. Bruccoleri wrote:
> Dear Tom,
> Thank you for the explanation. I did not understand what was
> going on in lwlock.c.
Yes, as Tom said, using the pre-7.2 code on SMP machines, if one backend
had a spinlock, the other backend would TAS loop trying to get the lock
until its timeslice
- Original Message -
From: "Robert E. Bruccoleri" <[EMAIL PROTECTED]>
To: "Luis Alberto Amigo Navarro" <[EMAIL PROTECTED]>
Cc: <[EMAIL PROTECTED]>; <[EMAIL PROTECTED]>; <[EMAIL PROTECTED]>
Sent: Monday, July 29, 2002 2:48 AM
Subject: R
Dear Luis,
I would be very interested. Replacing the IPC shared memory
with an arena make a lot of sense. --Bob
>
> Hi Bob:
> We're have been working with an sproc version of postgres and it has improve
> performance over a NUMA3 origin 3000 due to IRIX implements round_robin by
> defaul
Dear Tom,
Thank you for the explanation. I did not understand what was
going on in lwlock.c.
My systems are all SGI Origins having between 8 and 32
processors, and I've been running PostgreSQL on them for about 5
years. These machines do provide a number of good mechanisms for hig
"Robert E. Bruccoleri" <[EMAIL PROTECTED]> writes:
> Tom Lane writes:
>> If you're saying that we don't have an implementation of TAS for
>> SGI hardware, then feel free to contribute one. If you are wanting to
>> replace LWLocks with spinlocks, then you are sadly mistaken, IMHO.
> This touches
uot; <[EMAIL PROTECTED]>
Cc: <[EMAIL PROTECTED]>; <[EMAIL PROTECTED]>
Sent: Sunday, July 28, 2002 5:45 AM
Subject: Re: [HACKERS] Question about LWLockAcquire's use of semaphores
instead of spinlocks
> Tom Lane writes:
> >
> >
> > "Robert E. Bruccoler
Tom Lane writes:
>
>
> "Robert E. Bruccoleri" <[EMAIL PROTECTED]> writes:
> > On SGI multiprocessor machines, I suspect that a spinlock
> > implementation of LWLockAcquire would give better performance than
> > using IPC semaphores. Is there any specific reason that a spinlock
> > could not be
"Robert E. Bruccoleri" <[EMAIL PROTECTED]> writes:
> On SGI multiprocessor machines, I suspect that a spinlock
> implementation of LWLockAcquire would give better performance than
> using IPC semaphores. Is there any specific reason that a spinlock
> could not be used in this context?
Are you co
On SGI multiprocessor machines, I suspect that a spinlock
implementation of LWLockAcquire would give better performance than
using IPC semaphores. Is there any specific reason that a spinlock
could not be used in this context?
+-++
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