Re: Remove Instruction Synchronization Barrier in spin_delay() for ARM64 architecture

2025-05-01 Thread Salvatore Dipietro
On Thu, 1 May 2025 at 13:08, Tom Lane wrote: > Oh! That's an excellent point. The OP didn't mention if their tests > were done before or after 3d0b4b1, but that might well matter. The benchmarks we conducted are based on REL_17_2 branch which do not include the TAS_SPIN(lock) change for ARM yet

Re: Remove Instruction Synchronization Barrier in spin_delay() for ARM64 architecture

2025-05-01 Thread Nathan Bossart
On Thu, May 01, 2025 at 04:08:06PM -0400, Tom Lane wrote: > Nathan Bossart writes: >> ... commit 3d0b4b1 recently added a non-locking >> initial test in AArch64's TAS_SPIN, so I wonder if the ISB is still >> appropriate. It'd be interesting to see the performance difference of >> removing the ISB

Re: Remove Instruction Synchronization Barrier in spin_delay() for ARM64 architecture

2025-05-01 Thread Tom Lane
Nathan Bossart writes: > ... commit 3d0b4b1 recently added a non-locking > initial test in AArch64's TAS_SPIN, so I wonder if the ISB is still > appropriate. It'd be interesting to see the performance difference of > removing the ISB with and without commit 3d0b4b1 applied. Oh! That's an excell

Re: Remove Instruction Synchronization Barrier in spin_delay() for ARM64 architecture

2025-05-01 Thread Nathan Bossart
On Thu, May 01, 2025 at 02:48:59PM -0400, Tom Lane wrote: > Robert Haas writes: >> On Wed, Apr 30, 2025 at 4:53 AM Salvatore Dipietro >> wrote: >>> we would like to propose the removal of the Instruction >>> Synchronization Barrier (isb) for aarch64 architectures. Based on our >>> testing on Grav

Re: Remove Instruction Synchronization Barrier in spin_delay() for ARM64 architecture

2025-05-01 Thread Tom Lane
Robert Haas writes: > On Wed, Apr 30, 2025 at 4:53 AM Salvatore Dipietro > wrote: >> we would like to propose the removal of the Instruction >> Synchronization Barrier (isb) for aarch64 architectures. Based on our >> testing on Graviton instances (m7g.16xlarge), we can see on average >> over mult

Re: Remove Instruction Synchronization Barrier in spin_delay() for ARM64 architecture

2025-05-01 Thread Robert Haas
On Wed, Apr 30, 2025 at 4:53 AM Salvatore Dipietro wrote: > we would like to propose the removal of the Instruction > Synchronization Barrier (isb) for aarch64 architectures. Based on our > testing on Graviton instances (m7g.16xlarge), we can see on average > over multiple iterations up to 12% bet

Remove Instruction Synchronization Barrier in spin_delay() for ARM64 architecture

2025-04-30 Thread Salvatore Dipietro
Hi, we would like to propose the removal of the Instruction Synchronization Barrier (isb) for aarch64 architectures. Based on our testing on Graviton instances (m7g.16xlarge), we can see on average over multiple iterations up to 12% better performance using PGBench select-only and up to 9% with Sys