On Mon, 19 May 2025 at 09:38, Nathan Bossart wrote:
> Could you retry your tests on v18devel? It might also be useful to
repeat the tests on a variety of hardware to ensure
> it's a win across the board.
Hi Nathan,
Thanks for your clarification. As you requested, I have performed more
tests on
On Thu, 1 May 2025 at 14:50, Nathan Bossart wrote:
> So...
>
> * The ISB does seem to have a positive effect without commit 3d0b4b1
> applied.
>
> * With commit 3d0b4b1 applied, removing the ISB seems to have a positive
> effect at high concurrencies. This is especially pronounced in the
>
On Thu, 1 May 2025 at 13:08, Tom Lane wrote:
> Oh! That's an excellent point. The OP didn't mention if their tests
> were done before or after 3d0b4b1, but that might well matter.
The benchmarks we conducted are based on REL_17_2 branch which do not
include the TAS_SPIN(lock) change for ARM yet
Hi,
we would like to propose the removal of the Instruction
Synchronization Barrier (isb) for aarch64 architectures. Based on our
testing on Graviton instances (m7g.16xlarge), we can see on average
over multiple iterations up to 12% better performance using PGBench
select-only and up to 9% with Sys
