Hi,
I'm currently doing some benchmarking on a Maramba T5240. With cpustat, I have
seen that TLB misses are quite an issue. Now I want to know whether these
misses mainly occur in 8k or 4m pages. However, trapstat -T is not working
properly: It only reports some tsb misses, but the columns for
Nicolas Michael wrote:
> trapstat -T is not working properly: It only reports some tsb misses,
> but the columns for tlb misses are all 0 (instruction and data).
This is the expected result. The T2 processor handles TLB misses in
hardware, by accessing the TSB directly. If the mapping is not fo
Steve Sistare wrote:
> Nicolas Michael wrote:
> > trapstat -T is not working properly: It only reports some tsb misses,
> > but the columns for tlb misses are all 0 (instruction and data).
>
> This is the expected result. The T2 processor handles TLB misses in
> hardware, by accessing the TSB di
Nicolas Michael wrote:
> Steve Sistare wrote:
>> Nicolas Michael wrote:
>>> trapstat -T is not working properly: It only reports some tsb misses,
>>> but the columns for tlb misses are all 0 (instruction and data).
>> This is the expected result. The T2 processor handles TLB misses in
>> hardware
